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Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +02003 */
stroesebea8e842004-12-16 19:10:22 +00004/*----------------------------------------------------------------------------- */
5/* Function: ext_bus_cntlr_init */
6/* Description: Initializes the External Bus Controller for the external */
7/* peripherals. IMPORTANT: For pass1 this code must run from */
8/* cache since you can not reliably change a peripheral banks */
9/* timing register (pbxap) while running code from that bank. */
10/* For ex., since we are running from ROM on bank 0, we can NOT */
11/* execute the code that modifies bank 0 timings from ROM, so */
12/* we run it from cache. */
13/* Bank 0 - Flash and SRAM */
14/* Bank 1 - NVRAM/RTC */
15/* Bank 2 - Keyboard/Mouse controller */
16/* Bank 3 - IR controller */
17/* Bank 4 - not used */
18/* Bank 5 - not used */
19/* Bank 6 - not used */
20/* Bank 7 - FPGA registers */
21/*----------------------------------------------------------------------------- */
Stefan Roeseb36df562010-09-09 19:18:00 +020022#include <asm/ppc4xx.h>
stroesebea8e842004-12-16 19:10:22 +000023
24#include <ppc_asm.tmpl>
25#include <ppc_defs.h>
26
27#include <asm/cache.h>
28#include <asm/mmu.h>
29
30
31 .globl write_without_sync
32write_without_sync:
33 /*
34 * Write one values to host via pci busmastering
wdenkefe2a4d2004-12-16 21:44:03 +000035 * ptr = 0xc0000000 -> 0x01000000 (PCI)
36 * *ptr = 0x01234567;
stroesebea8e842004-12-16 19:10:22 +000037 */
wdenkefe2a4d2004-12-16 21:44:03 +000038 addi r31,0,0
39 lis r31,0xc000
stroesebea8e842004-12-16 19:10:22 +000040
41start1:
wdenkefe2a4d2004-12-16 21:44:03 +000042 lis r0,0x0123
43 ori r0,r0,0x4567
44 stw r0,0(r31)
stroesebea8e842004-12-16 19:10:22 +000045
46 /*
47 * Read one value back
wdenkefe2a4d2004-12-16 21:44:03 +000048 * ptr = (volatile unsigned long *)addr;
49 * val = *ptr;
stroesebea8e842004-12-16 19:10:22 +000050 */
51
wdenkefe2a4d2004-12-16 21:44:03 +000052 lwz r0,0(r31)
stroesebea8e842004-12-16 19:10:22 +000053
54 /*
55 * One pci config write
wdenkefe2a4d2004-12-16 21:44:03 +000056 * ibmPciConfigWrite(0x2e, 2, 0x1234);
stroesebea8e842004-12-16 19:10:22 +000057 */
58 /* subsystem id */
59
wdenkefe2a4d2004-12-16 21:44:03 +000060 li r4,0x002C
61 oris r4,r4,0x8000
62 lis r3,0xEEC0
63 stwbrx r4,0,r3
stroesebea8e842004-12-16 19:10:22 +000064
wdenkefe2a4d2004-12-16 21:44:03 +000065 li r5,0x1234
66 ori r3,r3,0x4
67 stwbrx r5,0,r3
stroesebea8e842004-12-16 19:10:22 +000068
wdenkefe2a4d2004-12-16 21:44:03 +000069 b start1
stroesebea8e842004-12-16 19:10:22 +000070
71 blr /* never reached !!!! */
72
stroesebea8e842004-12-16 19:10:22 +000073 .globl write_with_sync
74write_with_sync:
75 /*
76 * Write one values to host via pci busmastering
wdenkefe2a4d2004-12-16 21:44:03 +000077 * ptr = 0xc0000000 -> 0x01000000 (PCI)
78 * *ptr = 0x01234567;
stroesebea8e842004-12-16 19:10:22 +000079 */
wdenkefe2a4d2004-12-16 21:44:03 +000080 addi r31,0,0
81 lis r31,0xc000
stroesebea8e842004-12-16 19:10:22 +000082
83start2:
wdenkefe2a4d2004-12-16 21:44:03 +000084 lis r0,0x0123
85 ori r0,r0,0x4567
86 stw r0,0(r31)
stroesebea8e842004-12-16 19:10:22 +000087
88 /*
89 * Read one value back
wdenkefe2a4d2004-12-16 21:44:03 +000090 * ptr = (volatile unsigned long *)addr;
91 * val = *ptr;
stroesebea8e842004-12-16 19:10:22 +000092 */
93
wdenkefe2a4d2004-12-16 21:44:03 +000094 lwz r0,0(r31)
stroesebea8e842004-12-16 19:10:22 +000095
96 /*
97 * One pci config write
wdenkefe2a4d2004-12-16 21:44:03 +000098 * ibmPciConfigWrite(0x2e, 2, 0x1234);
stroesebea8e842004-12-16 19:10:22 +000099 */
100 /* subsystem id */
101
wdenkefe2a4d2004-12-16 21:44:03 +0000102 li r4,0x002C
103 oris r4,r4,0x8000
104 lis r3,0xEEC0
105 stwbrx r4,0,r3
106 sync
stroesebea8e842004-12-16 19:10:22 +0000107
wdenkefe2a4d2004-12-16 21:44:03 +0000108 li r5,0x1234
109 ori r3,r3,0x4
110 stwbrx r5,0,r3
111 sync
stroesebea8e842004-12-16 19:10:22 +0000112
wdenkefe2a4d2004-12-16 21:44:03 +0000113 b start2
stroesebea8e842004-12-16 19:10:22 +0000114
115 blr /* never reached !!!! */
116
stroesebea8e842004-12-16 19:10:22 +0000117 .globl write_with_less_sync
118write_with_less_sync:
119 /*
120 * Write one values to host via pci busmastering
wdenkefe2a4d2004-12-16 21:44:03 +0000121 * ptr = 0xc0000000 -> 0x01000000 (PCI)
122 * *ptr = 0x01234567;
stroesebea8e842004-12-16 19:10:22 +0000123 */
wdenkefe2a4d2004-12-16 21:44:03 +0000124 addi r31,0,0
125 lis r31,0xc000
stroesebea8e842004-12-16 19:10:22 +0000126
127start2b:
wdenkefe2a4d2004-12-16 21:44:03 +0000128 lis r0,0x0123
129 ori r0,r0,0x4567
130 stw r0,0(r31)
stroesebea8e842004-12-16 19:10:22 +0000131
132 /*
133 * Read one value back
wdenkefe2a4d2004-12-16 21:44:03 +0000134 * ptr = (volatile unsigned long *)addr;
135 * val = *ptr;
stroesebea8e842004-12-16 19:10:22 +0000136 */
137
wdenkefe2a4d2004-12-16 21:44:03 +0000138 lwz r0,0(r31)
stroesebea8e842004-12-16 19:10:22 +0000139
140 /*
141 * One pci config write
wdenkefe2a4d2004-12-16 21:44:03 +0000142 * ibmPciConfigWrite(0x2e, 2, 0x1234);
stroesebea8e842004-12-16 19:10:22 +0000143 */
144 /* subsystem id */
145
wdenkefe2a4d2004-12-16 21:44:03 +0000146 li r4,0x002C
147 oris r4,r4,0x8000
148 lis r3,0xEEC0
149 stwbrx r4,0,r3
150 sync
stroesebea8e842004-12-16 19:10:22 +0000151
wdenkefe2a4d2004-12-16 21:44:03 +0000152 li r5,0x1234
153 ori r3,r3,0x4
154 stwbrx r5,0,r3
stroesebea8e842004-12-16 19:10:22 +0000155/* sync */
156
wdenkefe2a4d2004-12-16 21:44:03 +0000157 b start2b
stroesebea8e842004-12-16 19:10:22 +0000158
159 blr /* never reached !!!! */
160
stroesebea8e842004-12-16 19:10:22 +0000161 .globl write_with_more_sync
162write_with_more_sync:
163 /*
164 * Write one values to host via pci busmastering
wdenkefe2a4d2004-12-16 21:44:03 +0000165 * ptr = 0xc0000000 -> 0x01000000 (PCI)
166 * *ptr = 0x01234567;
stroesebea8e842004-12-16 19:10:22 +0000167 */
wdenkefe2a4d2004-12-16 21:44:03 +0000168 addi r31,0,0
169 lis r31,0xc000
stroesebea8e842004-12-16 19:10:22 +0000170
171start3:
wdenkefe2a4d2004-12-16 21:44:03 +0000172 lis r0,0x0123
173 ori r0,r0,0x4567
174 stw r0,0(r31)
175 sync
stroesebea8e842004-12-16 19:10:22 +0000176
177 /*
178 * Read one value back
wdenkefe2a4d2004-12-16 21:44:03 +0000179 * ptr = (volatile unsigned long *)addr;
180 * val = *ptr;
stroesebea8e842004-12-16 19:10:22 +0000181 */
182
wdenkefe2a4d2004-12-16 21:44:03 +0000183 lwz r0,0(r31)
184 sync
stroesebea8e842004-12-16 19:10:22 +0000185
186 /*
187 * One pci config write
wdenkefe2a4d2004-12-16 21:44:03 +0000188 * ibmPciConfigWrite(0x2e, 2, 0x1234);
stroesebea8e842004-12-16 19:10:22 +0000189 */
190 /* subsystem id (PCIC0_SBSYSVID)*/
191
wdenkefe2a4d2004-12-16 21:44:03 +0000192 li r4,0x002C
193 oris r4,r4,0x8000
194 lis r3,0xEEC0
195 stwbrx r4,0,r3
196 sync
stroesebea8e842004-12-16 19:10:22 +0000197
wdenkefe2a4d2004-12-16 21:44:03 +0000198 li r5,0x1234
199 ori r3,r3,0x4
200 stwbrx r5,0,r3
201 sync
stroesebea8e842004-12-16 19:10:22 +0000202
wdenkefe2a4d2004-12-16 21:44:03 +0000203 b start3
stroesebea8e842004-12-16 19:10:22 +0000204
205 blr /* never reached !!!! */