| Stephen Warren | 6238935 | 2016-05-13 15:50:29 -0600 | [diff] [blame] | 1 | menu "Mailbox Controller Support" |
| 2 | |
| 3 | config DM_MAILBOX |
| 4 | bool "Enable mailbox controllers using Driver Model" |
| 5 | depends on DM && OF_CONTROL |
| 6 | help |
| 7 | Enable support for the mailbox driver class. Mailboxes provide the |
| 8 | ability to transfer small messages and/or notifications from one |
| 9 | CPU to another CPU, or sometimes to dedicated HW modules. They form |
| 10 | the basis of a variety of inter-process/inter-CPU communication |
| 11 | protocols. |
| 12 | |
| Stephen Warren | 8961b52 | 2016-05-16 17:41:37 -0600 | [diff] [blame] | 13 | config SANDBOX_MBOX |
| 14 | bool "Enable the sandbox mailbox test driver" |
| 15 | depends on DM_MAILBOX && SANDBOX |
| 16 | help |
| 17 | Enable support for a test mailbox implementation, which simply echos |
| 18 | back a modified version of any message that is sent. |
| 19 | |
| Stephen Warren | 0f67e23 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 20 | config TEGRA_HSP |
| 21 | bool "Enable Tegra HSP controller support" |
| 22 | depends on DM_MAILBOX && TEGRA |
| 23 | help |
| 24 | This enables support for the NVIDIA Tegra HSP Hw module, which |
| 25 | implements doorbells, mailboxes, semaphores, and shared interrupts. |
| 26 | |
| Fabien Dessenne | 01964d8 | 2019-05-14 11:20:34 +0200 | [diff] [blame] | 27 | config STM32_IPCC |
| 28 | bool "Enable STM32 IPCC controller support" |
| 29 | depends on DM_MAILBOX && ARCH_STM32MP |
| 30 | help |
| 31 | This enables support for the STM32MP IPCC Hw module, which |
| 32 | implements doorbells between 2 processors. |
| 33 | |
| Lokesh Vutla | f9aa410 | 2018-08-27 15:57:48 +0530 | [diff] [blame] | 34 | config K3_SEC_PROXY |
| 35 | bool "Texas Instruments K3 Secure Proxy Driver" |
| 36 | depends on DM_MAILBOX && ARCH_K3 |
| 37 | help |
| 38 | An implementation of Secure proxy slave driver for K3 SoCs from |
| 39 | Texas Instruments. Secure proxy is a communication entity mainly |
| 40 | used for communication between multiple processors with the SoC. |
| 41 | Select this driver if your platform has support for this hardware |
| 42 | block. |
| 43 | |
| Ibai Erkiaga | 660b0c7 | 2019-09-27 11:36:56 +0100 | [diff] [blame] | 44 | config ZYNQMP_IPI |
| 45 | bool "Xilinx ZynqMP IPI controller support" |
| 46 | depends on DM_MAILBOX && ARCH_ZYNQMP |
| 47 | help |
| 48 | This enables support for the Xilinx ZynqMP Inter Processor Interrupt |
| 49 | communication controller. |
| Stephen Warren | 6238935 | 2016-05-13 15:50:29 -0600 | [diff] [blame] | 50 | endmenu |