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stroese1bc0f142004-12-16 18:20:14 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27#include <malloc.h>
28
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029DECLARE_GLOBAL_DATA_PTR;
stroese1bc0f142004-12-16 18:20:14 +000030
31#if 0
32#define FPGA_DEBUG
33#endif
34
35extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
36extern void lxt971_no_sleep(void);
37
38/* fpga configuration data - gzip compressed and generated by bin2c */
39const unsigned char fpgadata[] =
40{
41#include "fpgadata.c"
42};
43
44/*
45 * include common fpga code (for esd boards)
46 */
47#include "../common/fpga.c"
48
49
50/* Prototypes */
51int gunzip(void *, int, unsigned char *, unsigned long *);
52
53
54#ifdef CONFIG_LCD_USED
55/* logo bitmap data - gzip compressed and generated by bin2c */
56unsigned char logo_bmp[] =
57{
58#include CFG_LCD_LOGO_NAME
59};
60
61/*
62 * include common lcd code (for esd boards)
63 */
64#include "../common/lcd.c"
65
stroese04e93ec2005-04-13 10:06:07 +000066#include CFG_LCD_HEADER_NAME
stroese1bc0f142004-12-16 18:20:14 +000067#endif /* CONFIG_LCD_USED */
68
69
stroese04e93ec2005-04-13 10:06:07 +000070int board_revision(void)
71{
72 unsigned long cntrl0Reg;
73 unsigned long value;
74
75 /*
76 * Get version of APC405 board from GPIO's
77 */
78
79 /*
80 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
81 */
82 cntrl0Reg = mfdcr(cntrl0);
83 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
84 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
85 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
86 udelay(1000); /* wait some time before reading input */
87 value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
88
89 /*
90 * Restore GPIO settings
91 */
92 mtdcr(cntrl0, cntrl0Reg);
93
94 switch (value) {
95 case 0x00180000:
96 /* CS2==1 && CS3==1 -> version <= 1.2 */
97 return 2;
98 case 0x00080000:
99 /* CS2==0 && CS3==1 -> version 1.3 */
100 return 3;
101#if 0 /* not yet manufactured ! */
102 case 0x00100000:
103 /* CS2==1 && CS3==0 -> version 1.4 */
104 return 4;
105 case 0x00000000:
106 /* CS2==0 && CS3==0 -> version 1.5 */
107 return 5;
108#endif
109 default:
110 /* should not be reached! */
111 return 0;
112 }
113}
114
115
stroese1bc0f142004-12-16 18:20:14 +0000116int board_early_init_f (void)
117{
118 /*
119 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
120 */
121 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
122 out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
123 out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
124 out32(GPIO0_OR, 0); /* pull prg low */
125
126 /*
127 * IRQ 0-15 405GP internally generated; active high; level sensitive
128 * IRQ 16 405GP internally generated; active low; level sensitive
129 * IRQ 17-24 RESERVED
130 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
131 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
132 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
133 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
134 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
135 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
136 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
137 */
138 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
139 mtdcr(uicer, 0x00000000); /* disable all ints */
140 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
141 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
142 mtdcr(uictr, 0x10000000); /* set int trigger levels */
143 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
144 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
145
146 /*
147 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
148 */
149#if 1 /* test-only */
150 mtebc (epcr, 0xa8400000); /* ebc always driven */
151#else
152 mtebc (epcr, 0x28400000); /* ebc in high-z */
153#endif
154
155 return 0;
156}
157
158
159/* ------------------------------------------------------------------------- */
160
161int misc_init_f (void)
162{
163 return 0; /* dummy implementation */
164}
165
166
167int misc_init_r (void)
168{
169 volatile unsigned short *fpga_mode =
170 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
stroese04e93ec2005-04-13 10:06:07 +0000171 volatile unsigned short *fpga_ctrl2 =
172 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
stroese1bc0f142004-12-16 18:20:14 +0000173 volatile unsigned char *duart0_mcr =
174 (unsigned char *)((ulong)DUART0_BA + 4);
175 volatile unsigned char *duart1_mcr =
176 (unsigned char *)((ulong)DUART1_BA + 4);
177 volatile unsigned short *fuji_lcdbl_pwm =
178 (unsigned short *)((ulong)0xf0100200 + 0xa0);
179 unsigned char *dst;
180 ulong len = sizeof(fpgadata);
181 int status;
182 int index;
183 int i;
184 unsigned long cntrl0Reg;
185
186 /*
187 * Setup GPIO pins (CS6+CS7 as GPIO)
188 */
189 cntrl0Reg = mfdcr(cntrl0);
190 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
191
192 dst = malloc(CFG_FPGA_MAX_SIZE);
193 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
194 printf ("GUNZIP ERROR - must RESET board to recover\n");
195 do_reset (NULL, 0, 0, NULL);
196 }
197
198 status = fpga_boot(dst, len);
199 if (status != 0) {
200 printf("\nFPGA: Booting failed ");
201 switch (status) {
202 case ERROR_FPGA_PRG_INIT_LOW:
203 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
204 break;
205 case ERROR_FPGA_PRG_INIT_HIGH:
206 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
207 break;
208 case ERROR_FPGA_PRG_DONE:
209 printf("(Timeout: DONE not high after programming FPGA)\n ");
210 break;
211 }
212
213 /* display infos on fpgaimage */
214 index = 15;
215 for (i=0; i<4; i++) {
216 len = dst[index];
217 printf("FPGA: %s\n", &(dst[index+1]));
218 index += len+3;
219 }
220 putc ('\n');
221 /* delayed reboot */
222 for (i=20; i>0; i--) {
223 printf("Rebooting in %2d seconds \r",i);
224 for (index=0;index<1000;index++)
225 udelay(1000);
226 }
227 putc ('\n');
228 do_reset(NULL, 0, 0, NULL);
229 }
230
231 /* restore gpio/cs settings */
232 mtdcr(cntrl0, cntrl0Reg);
233
234 puts("FPGA: ");
235
236 /* display infos on fpgaimage */
237 index = 15;
238 for (i=0; i<4; i++) {
239 len = dst[index];
240 printf("%s ", &(dst[index+1]));
241 index += len+3;
242 }
243 putc ('\n');
244
245 free(dst);
246
247 /*
248 * Reset FPGA via FPGA_DATA pin
249 */
250 SET_FPGA(FPGA_PRG | FPGA_CLK);
251 udelay(1000); /* wait 1ms */
252 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
253 udelay(1000); /* wait 1ms */
254
255 /*
stroese04e93ec2005-04-13 10:06:07 +0000256 * Write board revision in FPGA
257 */
258 *fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
259
260 /*
stroese1bc0f142004-12-16 18:20:14 +0000261 * Enable power on PS/2 interface (with reset)
262 */
263 *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
264 for (i=0;i<100;i++)
265 udelay(1000);
266 udelay(1000);
267 *fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;
268
269 /*
270 * Enable interrupts in exar duart mcr[3]
271 */
272 *duart0_mcr = 0x08;
273 *duart1_mcr = 0x08;
274
275 /*
276 * Init lcd interface and display logo
277 */
278 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
279 regs_13806_640_480_16bpp,
280 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
281 logo_bmp, sizeof(logo_bmp));
282
283 /*
stroese04e93ec2005-04-13 10:06:07 +0000284 * Reset microcontroller and setup backlight PWM controller
stroese1bc0f142004-12-16 18:20:14 +0000285 */
stroese04e93ec2005-04-13 10:06:07 +0000286 *fpga_mode |= 0x0014;
287 for (i=0;i<10;i++)
288 udelay(1000);
stroese1bc0f142004-12-16 18:20:14 +0000289 *fpga_mode |= 0x001c;
290 *fuji_lcdbl_pwm = 0x00ff;
291
292 return (0);
293}
294
295
296/*
297 * Check Board Identity:
298 */
299
300int checkboard (void)
301{
302 unsigned char str[64];
303 int i = getenv_r ("serial#", str, sizeof(str));
304
305 puts ("Board: ");
306
307 if (i == -1) {
308 puts ("### No HW ID - assuming APC405");
309 } else {
310 puts(str);
311 }
312
stroese04e93ec2005-04-13 10:06:07 +0000313 gd->board_type = board_revision();
314 printf(", Rev 1.%ld\n", gd->board_type);
stroese1bc0f142004-12-16 18:20:14 +0000315
316 /*
317 * Disable sleep mode in LXT971
318 */
319 lxt971_no_sleep();
320
321 return 0;
322}
323
324/* ------------------------------------------------------------------------- */
325
326long int initdram (int board_type)
327{
328 unsigned long val;
329
330 mtdcr(memcfga, mem_mb0cf);
331 val = mfdcr(memcfgd);
332
333#if 0
334 printf("\nmb0cf=%x\n", val); /* test-only */
335 printf("strap=%x\n", mfdcr(strap)); /* test-only */
336#endif
337
338 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
339}
340
341/* ------------------------------------------------------------------------- */
342
343int testdram (void)
344{
345 /* TODO: XXX XXX XXX */
346 printf ("test: 16 MB - ok\n");
347
348 return (0);
349}
350
351/* ------------------------------------------------------------------------- */
352
353#ifdef CONFIG_IDE_RESET
354
355void ide_set_reset(int on)
356{
357 volatile unsigned short *fpga_mode =
358 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
359
360 /*
361 * Assert or deassert CompactFlash Reset Pin
362 */
363 if (on) { /* assert RESET */
364 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
365 } else { /* release RESET */
366 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
367 }
368}
369
370#endif /* CONFIG_IDE_RESET */
371
372/* ------------------------------------------------------------------------- */