Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / de180e6daa529dc78668c99bdf17a9cdd440782d / . / board / csb226 / memsetup.S
blob: 5a584c153814c31ee8d56a8ca9c3ab507d6eaa65 [file] [log] [blame]
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1/*
2 * Most of this taken from Redboot hal_platform_setup.h with cleanup
3 *
4 * NOTE: I haven't clean this up considerably, just enough to get it
5 * running. See hal_platform_setup.h for the source. See
6 * board/cradle/memsetup.S for another PXA250 setup that is
7 * much cleaner.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29#include <version.h>
30#include <asm/arch/pxa-regs.h>
31
32DRAM_SIZE: .long CFG_DRAM_SIZE
33
34/* wait for coprocessor write complete */
35 .macro CPWAIT reg
36 mrc p15,0,\reg,c2,c0,0
37 mov \reg,\reg
38 sub pc,pc,#4
39 .endm
40
41
42/*
43 * Memory setup
44 */
45
46.globl memsetup
47memsetup:
48
49 mov r10, lr
50
51 /* Set up GPIO pins first ----------------------------------------- */
52
53 ldr r0, =GPSR0
54 ldr r1, =CFG_GPSR0_VAL
55 str r1, [r0]
56
57 ldr r0, =GPSR1
58 ldr r1, =CFG_GPSR1_VAL
59 str r1, [r0]
60
61 ldr r0, =GPSR2
62 ldr r1, =CFG_GPSR2_VAL
63 str r1, [r0]
64
65 ldr r0, =GPCR0
66 ldr r1, =CFG_GPCR0_VAL
67 str r1, [r0]
68
69 ldr r0, =GPCR1
70 ldr r1, =CFG_GPCR1_VAL
71 str r1, [r0]
72
73 ldr r0, =GPCR2
74 ldr r1, =CFG_GPCR2_VAL
75 str r1, [r0]
76
77 ldr r0, =GPDR0
78 ldr r1, =CFG_GPDR0_VAL
79 str r1, [r0]
80
81 ldr r0, =GPDR1
82 ldr r1, =CFG_GPDR1_VAL
83 str r1, [r0]
84
85 ldr r0, =GPDR2
86 ldr r1, =CFG_GPDR2_VAL
87 str r1, [r0]
88
89 ldr r0, =GAFR0_L
90 ldr r1, =CFG_GAFR0_L_VAL
91 str r1, [r0]
92
93 ldr r0, =GAFR0_U
94 ldr r1, =CFG_GAFR0_U_VAL
95 str r1, [r0]
96
97 ldr r0, =GAFR1_L
98 ldr r1, =CFG_GAFR1_L_VAL
99 str r1, [r0]
100
101 ldr r0, =GAFR1_U
102 ldr r1, =CFG_GAFR1_U_VAL
103 str r1, [r0]
104
105 ldr r0, =GAFR2_L
106 ldr r1, =CFG_GAFR2_L_VAL
107 str r1, [r0]
108
109 ldr r0, =GAFR2_U
110 ldr r1, =CFG_GAFR2_U_VAL
111 str r1, [r0]
112
113 ldr r0, =PSSR /* enable GPIO pins */
114 ldr r1, =CFG_PSSR_VAL
115 str r1, [r0]
116
117/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
118/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
119/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
120/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
121/* */
122/* ldr r1, =LED_BLANK */
123/* mov r0, #0xFF */
124/* str r0, [r1] / turn on hex leds */
125/* */
126/*loop: */
127/* */
128/* ldr r0, =0xB0070001 */
129/* ldr r1, =_LED */
130/* str r0, [r1] / hex display */
131
132
133 /* ---------------------------------------------------------------- */
134 /* Enable memory interface */
135 /* */
136 /* The sequence below is based on the recommended init steps */
137 /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
138 /* Chapter 10. */
139 /* ---------------------------------------------------------------- */
140
141 /* ---------------------------------------------------------------- */
142 /* Step 1: Wait for at least 200 microsedonds to allow internal */
143 /* clocks to settle. Only necessary after hard reset... */
144 /* FIXME: can be optimized later */
145 /* ---------------------------------------------------------------- */
146
147 ldr r3, =OSCR /* reset the OS Timer Count to zero */
148 mov r2, #0
149 str r2, [r3]
150 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
151 /* so 0x300 should be plenty */
1521:
153 ldr r2, [r3]
154 cmp r4, r2
155 bgt 1b
156
157mem_init:
158
159 ldr r1, =MEMC_BASE /* get memory controller base addr. */
160
161 /* ---------------------------------------------------------------- */
162 /* Step 2a: Initialize Asynchronous static memory controller */
163 /* ---------------------------------------------------------------- */
164
165 /* MSC registers: timing, bus width, mem type */
166
167 /* MSC0: nCS(0,1) */
168 ldr r2, =CFG_MSC0_VAL
169 str r2, [r1, #MSC0_OFFSET]
170 ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
171 /* that data latches */
172 /* MSC1: nCS(2,3) */
173 ldr r2, =CFG_MSC1_VAL
174 str r2, [r1, #MSC1_OFFSET]
175 ldr r2, [r1, #MSC1_OFFSET]
176
177 /* MSC2: nCS(4,5) */
178 ldr r2, =CFG_MSC2_VAL
179 str r2, [r1, #MSC2_OFFSET]
180 ldr r2, [r1, #MSC2_OFFSET]
181
182 /* ---------------------------------------------------------------- */
183 /* Step 2b: Initialize Card Interface */
184 /* ---------------------------------------------------------------- */
185
186 /* MECR: Memory Expansion Card Register */
187 ldr r2, =CFG_MECR_VAL
188 str r2, [r1, #MECR_OFFSET]
189 ldr r2, [r1, #MECR_OFFSET]
190
191 /* MCMEM0: Card Interface slot 0 timing */
192 ldr r2, =CFG_MCMEM0_VAL
193 str r2, [r1, #MCMEM0_OFFSET]
194 ldr r2, [r1, #MCMEM0_OFFSET]
195
196 /* MCMEM1: Card Interface slot 1 timing */
197 ldr r2, =CFG_MCMEM1_VAL
198 str r2, [r1, #MCMEM1_OFFSET]
199 ldr r2, [r1, #MCMEM1_OFFSET]
200
201 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
202 ldr r2, =CFG_MCATT0_VAL
203 str r2, [r1, #MCATT0_OFFSET]
204 ldr r2, [r1, #MCATT0_OFFSET]
205
206 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
207 ldr r2, =CFG_MCATT1_VAL
208 str r2, [r1, #MCATT1_OFFSET]
209 ldr r2, [r1, #MCATT1_OFFSET]
210
211 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
212 ldr r2, =CFG_MCIO0_VAL
213 str r2, [r1, #MCIO0_OFFSET]
214 ldr r2, [r1, #MCIO0_OFFSET]
215
216 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
217 ldr r2, =CFG_MCIO1_VAL
218 str r2, [r1, #MCIO1_OFFSET]
219 ldr r2, [r1, #MCIO1_OFFSET]
220
221 /* ---------------------------------------------------------------- */
222 /* Step 2c: Write FLYCNFG FIXME: what's that??? */
223 /* ---------------------------------------------------------------- */
224
225
226 /* ---------------------------------------------------------------- */
227 /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
228 /* ---------------------------------------------------------------- */
229
230 /* Before accessing MDREFR we need a valid DRI field, so we set */
231 /* this to power on defaults + DIR field. */
232
233 ldr r4, =0x03ca4fff
234 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
235 ldr r4, [r1, #MDREFR_OFFSET]
236
237 ldr r4, =0x03ca4030
238 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
239 ldr r4, [r1, #MDREFR_OFFSET]
240
241 /* Note: preserve the mdrefr value in r4 */
242
243
244 /* ---------------------------------------------------------------- */
245 /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
246 /* ---------------------------------------------------------------- */
247
248 /* Initialize SXCNFG register. Assert the enable bits */
249
250 /* Write SXMRS to cause an MRS command to all enabled banks of */
251 /* synchronous static memory. Note that SXLCR need not be written */
252 /* at this time. */
253
254 /* FIXME: we use async mode for now */
255
256
257 /* ---------------------------------------------------------------- */
258 /* Step 4: Initialize SDRAM */
259 /* ---------------------------------------------------------------- */
260
261 /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */
262 /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
263
264 orr r4, r4, #(MDREFR_K1RUN|MDREFR_K2RUN|MDREFR_K0RUN)
265
266 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
267 ldr r4, [r1, #MDREFR_OFFSET]
268
269
270 /* Step 4b: de-assert MDREFR:SLFRSH. */
271
272 bic r4, r4, #(MDREFR_SLFRSH)
273
274 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
275 ldr r4, [r1, #MDREFR_OFFSET]
276
277
278 /* Step 4c: assert MDREFR:E1PIN and E0PIO */
279
280 orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
281
282 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
283 ldr r4, [r1, #MDREFR_OFFSET]
284
285
286 /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
287 /* configure but not enable each SDRAM partition pair. */
288
289 ldr r4, [r1, #MDCNFG_OFFSET]
290 bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
291
292 str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
293 ldr r4, [r1, #MDCNFG_OFFSET]
294
295
296 /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
297 /* 100..200 µsec. */
298
299 ldr r3, =OSCR /* reset the OS Timer Count to zero */
300 mov r2, #0
301 str r2, [r3]
302 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
303 /* so 0x300 should be plenty */
3041:
305 ldr r2, [r3]
306 cmp r4, r2
307 bgt 1b
308
309
310 /* Step 4f: Trigger a number (usually 8) refresh cycles by */
311 /* attempting non-burst read or write accesses to disabled */
312 /* SDRAM, as commonly specified in the power up sequence */
313 /* documented in SDRAM data sheets. The address(es) used */
314 /* for this purpose must not be cacheable. */
315
316 ldr r3, =CFG_DRAM_BASE
317 str r2, [r3]
318 str r2, [r3]
319 str r2, [r3]
320 str r2, [r3]
321 str r2, [r3]
322 str r2, [r3]
323 str r2, [r3]
324 str r2, [r3]
325
326
327 /* Step 4g: Write MDCNFG with enable bits asserted */
328 /* (MDCNFG:DEx set to 1). */
329
330 ldr r3, [r1, #MDCNFG_OFFSET]
331 orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
332 str r3, [r1, #MDCNFG_OFFSET]
333
334 /* Step 4h: Write MDMRS. */
335
336 ldr r2, =CFG_MDMRS_VAL
337 str r2, [r1, #MDMRS_OFFSET]
338
339
340 /* We are finished with Intel's memory controller initialisation */
341
342
343 /* ---------------------------------------------------------------- */
344 /* Disable (mask) all interrupts at interrupt controller */
345 /* ---------------------------------------------------------------- */
346
347initirqs:
348
349 mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
350 ldr r2, =ICLR
351 str r1, [r2]
352
353 ldr r2, =ICMR /* mask all interrupts at the controller */
354 str r1, [r2]
355
356
357 /* ---------------------------------------------------------------- */
358 /* Clock initialisation */
359 /* ---------------------------------------------------------------- */
360
361initclks:
362
363 /* Disable the peripheral clocks, and set the core clock frequency */
364 /* (hard-coding at 398.12MHz for now). */
365
366 /* Turn Off ALL on-chip peripheral clocks for re-configuration */
367 /* Note: See label 'ENABLECLKS' for the re-enabling */
368 ldr r1, =CKEN
369 mov r2, #0
370 str r2, [r1]
371
372
373 /* default value in case no valid rotary switch setting is found */
374 ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
375
376 /* ... and write the core clock config register */
377 ldr r1, =CCCR
378 str r2, [r1]
379
380 /* enable the 32Khz oscillator for RTC and PowerManager */
381 ldr r1, =OSCC
382 mov r2, #OSCC_OON
383 str r2, [r1]
384
385 /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
386 /* has settled. */
38760:
388 ldr r2, [r1]
389 ands r2, r2, #1
390 beq 60b
391
392 /* ---------------------------------------------------------------- */
393 /* */
394 /* ---------------------------------------------------------------- */
395
396 /* Save SDRAM size */
397 ldr r1, =DRAM_SIZE
398 str r8, [r1]
399
400 /* Interrupt init: Mask all interrupts */
401 ldr r0, =ICMR /* enable no sources */
402 mov r1, #0
403 str r1, [r0]
404
405 /* FIXME */
406
407#define NODEBUG
408#ifdef NODEBUG
409 /*Disable software and data breakpoints */
410 mov r0,#0
411 mcr p15,0,r0,c14,c8,0 /* ibcr0 */
412 mcr p15,0,r0,c14,c9,0 /* ibcr1 */
413 mcr p15,0,r0,c14,c4,0 /* dbcon */
414
415 /*Enable all debug functionality */
416 mov r0,#0x80000000
417 mcr p14,0,r0,c10,c0,0 /* dcsr */
418
419#endif
420
421 /* ---------------------------------------------------------------- */
422 /* End memsetup */
423 /* ---------------------------------------------------------------- */
424
425endmemsetup:
426
427 mov pc, lr
428