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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
stroesea20b27a2004-12-16 18:05:42 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
Stefan Roese82f4c6a2005-08-12 16:52:47 +020019#define CONFIG_IDENT_STRING " $Name: $"
stroesea20b27a2004-12-16 18:05:42 +000020
21#define CONFIG_405EP 1 /* This is a PPC405 CPU */
22#define CONFIG_4xx 1 /* ...member of PPC4xx family */
23#define CONFIG_WUH405 1 /* ...on a WUH405 board */
24
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26
stroesea20b27a2004-12-16 18:05:42 +000027#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
28#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
29
30#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
31
32#define CONFIG_BAUDRATE 9600
33#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
34
35#undef CONFIG_BOOTARGS
36#undef CONFIG_BOOTCOMMAND
37
38#define CONFIG_PREBOOT /* enable preboot variable */
39
40#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +000042
Ben Warren96e21f82008-10-27 23:50:15 -070043#define CONFIG_PPC4xx_EMAC
stroesea20b27a2004-12-16 18:05:42 +000044#define CONFIG_MII 1 /* MII PHY management */
45#define CONFIG_PHY_ADDR 0 /* PHY address */
46#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
47
48#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
49
stroesea20b27a2004-12-16 18:05:42 +000050
Jon Loeligera5562902007-07-08 15:31:57 -050051/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050052 * BOOTP options
53 */
54#define CONFIG_BOOTP_BOOTFILESIZE
55#define CONFIG_BOOTP_BOOTPATH
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58
59
60/*
Jon Loeligera5562902007-07-08 15:31:57 -050061 * Command line configuration.
62 */
63#include <config_cmd_default.h>
64
65#define CONFIG_CMD_DHCP
66#define CONFIG_CMD_IRQ
67#define CONFIG_CMD_ELF
68#define CONFIG_CMD_NAND
69#define CONFIG_CMD_DATE
70#define CONFIG_CMD_I2C
71#define CONFIG_CMD_MII
72#define CONFIG_CMD_PING
73#define CONFIG_CMD_EEPROM
74
stroesea20b27a2004-12-16 18:05:42 +000075
76#undef CONFIG_WATCHDOG /* watchdog disabled */
77
78#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroesea20b27a2004-12-16 18:05:42 +000080
81#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
82
83/*
84 * Miscellaneous configurable options
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_LONGHELP /* undef to save memory */
stroesea20b27a2004-12-16 18:05:42 +000087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
stroesea20b27a2004-12-16 18:05:42 +000089
Jon Loeligera5562902007-07-08 15:31:57 -050090#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +000092#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +000094#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
96#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
97#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea20b27a2004-12-16 18:05:42 +0000102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
104#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000105
Stefan Roese550650d2010-09-20 16:05:31 +0200106#define CONFIG_CONS_INDEX 2 /* Use UART1 */
107#define CONFIG_SYS_NS16550
108#define CONFIG_SYS_NS16550_SERIAL
109#define CONFIG_SYS_NS16550_REG_SIZE 1
110#define CONFIG_SYS_NS16550_CLK get_serial_clock()
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000114
115/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea20b27a2004-12-16 18:05:42 +0000117 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
118 57600, 115200, 230400, 460800, 921600 }
119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
121#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000122
stroesea20b27a2004-12-16 18:05:42 +0000123#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
124
125#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000128
129/*-----------------------------------------------------------------------
130 * NAND-FLASH stuff
131 *-----------------------------------------------------------------------
132 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200135#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
138#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
139#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
140#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroesea20b27a2004-12-16 18:05:42 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
stroesea20b27a2004-12-16 18:05:42 +0000143
144/*-----------------------------------------------------------------------
145 * PCI stuff
146 *-----------------------------------------------------------------------
147 */
148#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
149#define PCI_HOST_FORCE 1 /* configure as pci host */
150#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
151
152#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000153#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
stroesea20b27a2004-12-16 18:05:42 +0000154#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
155#undef CONFIG_PCI_PNP /* do pci plug-and-play */
156 /* resource configuration */
157
158#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
161#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
162#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
163#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
164#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
165#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
166#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
167#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
168#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroesea20b27a2004-12-16 18:05:42 +0000169
170/*-----------------------------------------------------------------------
171 * Start addresses for the final memory configuration
172 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_SDRAM_BASE 0x00000000
176#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
177#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
178#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
179#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
stroesea20b27a2004-12-16 18:05:42 +0000180
181/*
182 * For booting Linux, the board info and command line data
183 * have to be in the first 8 MB of memory, since this is
184 * the maximum mapped by the Linux kernel during initialization.
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000187/*-----------------------------------------------------------------------
188 * FLASH organization
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
191#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea20b27a2004-12-16 18:05:42 +0000192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
194#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
197#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
198#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea20b27a2004-12-16 18:05:42 +0000199/*
200 * The following defines are added for buggy IOP480 byte interface.
201 * All other boards should use the standard values (CPCI405 etc.)
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
204#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
205#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea20b27a2004-12-16 18:05:42 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000208
209#if 0 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
211#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroesea20b27a2004-12-16 18:05:42 +0000212#endif
213
214/*-----------------------------------------------------------------------
215 * Environment Variable setup
216 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200217#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
219#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000220 /* total size of a CAT24WC16 is 2048 bytes */
221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
223#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
stroesea20b27a2004-12-16 18:05:42 +0000224
225/*-----------------------------------------------------------------------
226 * I2C EEPROM (CAT24WC16) for environment
227 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000228#define CONFIG_SYS_I2C
229#define CONFIG_SYS_I2C_PPC4XX
230#define CONFIG_SYS_I2C_PPC4XX_CH0
231#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
232#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
235#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000236/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
238#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000239 /* 16 byte page write mode using*/
240 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000242
stroesea20b27a2004-12-16 18:05:42 +0000243/*
244 * Init Memory Controller:
245 *
246 * BR0/1 and OR0/1 (FLASH)
247 */
248
249#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
250
251/*-----------------------------------------------------------------------
252 * External Bus Controller (EBC) Setup
253 */
254
255/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_EBC_PB0AP 0x92015480
257/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
258#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000259
260/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_EBC_PB1AP 0x92015480
262#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000263
264/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
266#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000267
268/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
270#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000271
272#define CAN_BA 0xF0000000 /* CAN Base Address */
273#define DUART0_BA 0xF0000400 /* DUART Base Address */
274#define DUART1_BA 0xF0000408 /* DUART Base Address */
275#define DUART2_BA 0xF0000410 /* DUART Base Address */
276#define DUART3_BA 0xF0000418 /* DUART Base Address */
277#define RTC_BA 0xF0000500 /* RTC Base Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_NAND_BASE 0xF4000000
stroesea20b27a2004-12-16 18:05:42 +0000279
280/*-----------------------------------------------------------------------
281 * FPGA stuff
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
284#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroesea20b27a2004-12-16 18:05:42 +0000285
286/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
288#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
289#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
290#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
291#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000292
293/*-----------------------------------------------------------------------
294 * Definitions for initial stack pointer and data area (in data cache)
295 */
296/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_TEMP_STACK_OCM 1
stroesea20b27a2004-12-16 18:05:42 +0000298
299/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
301#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
302#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200303#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroesea20b27a2004-12-16 18:05:42 +0000304
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200305#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000307
308/*-----------------------------------------------------------------------
309 * Definitions for GPIO setup (PPC405EP specific)
310 *
311 * GPIO0[0] - External Bus Controller BLAST output
312 * GPIO0[1-9] - Instruction trace outputs -> GPIO
313 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
314 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
315 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
316 * GPIO0[24-27] - UART0 control signal inputs/outputs
317 * GPIO0[28-29] - UART1 data signal input/output
318 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
319 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200320#define CONFIG_SYS_GPIO0_OSRL 0x40000550
321#define CONFIG_SYS_GPIO0_OSRH 0x00000110
322#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
323#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200325#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
stroesea20b27a2004-12-16 18:05:42 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
stroesea20b27a2004-12-16 18:05:42 +0000329
330/*
stroesea20b27a2004-12-16 18:05:42 +0000331 * Default speed selection (cpu_plb_opb_ebc) in mhz.
332 * This value will be set if iic boot eprom is disabled.
333 */
334#if 0
335#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
336#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
337#endif
338#if 1
339#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
340#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
341#endif
342#if 0
343#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
344#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
345#endif
346
347#endif /* __CONFIG_H */