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wdenkda27dcf2002-09-10 19:19:06 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the LUBBOCK board.
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenkda27dcf2002-09-10 19:19:06 +000012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*
wdenkda27dcf2002-09-10 19:19:06 +000018 * High Level Configuration Options
19 * (easy to change)
20 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010021#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
wdenk71f95112003-06-15 22:40:42 +000022#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
23#define CONFIG_LCD 1
wdenk63cfcbb2004-10-09 22:32:26 +000024#ifdef CONFIG_LCD
Jeroen Hofstee06980952013-01-22 10:44:10 +000025#define CONFIG_PXA_LCD
wdenk63cfcbb2004-10-09 22:32:26 +000026#define CONFIG_SHARP_LM8V31
27#endif
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +010028#define CONFIG_MMC
Helmut Raiger9660e442011-10-20 04:19:47 +000029#define CONFIG_BOARD_LATE_INIT
Jean-Christophe PLAGNIOL-VILLARD10cdb8d2007-10-19 00:24:59 +020030#define CONFIG_DOS_PARTITION
Marek Vasut3c43ca22010-10-20 20:55:44 +020031#define CONFIG_SYS_TEXT_BASE 0x0
wdenkda27dcf2002-09-10 19:19:06 +000032
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020033/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000034#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020035
wdenkda27dcf2002-09-10 19:19:06 +000036/*
37 * Size of malloc() pool
38 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenkda27dcf2002-09-10 19:19:06 +000040
41/*
42 * Hardware drivers
43 */
Nishanth Menonac6b3622009-10-16 00:06:37 -050044#define CONFIG_LAN91C96
wdenk45219c42003-05-12 21:50:16 +000045#define CONFIG_LAN91C96_BASE 0x0C000000
wdenkda27dcf2002-09-10 19:19:06 +000046
47/*
48 * select serial console configuration
49 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020050#define CONFIG_PXA_SERIAL
wdenk71f95112003-06-15 22:40:42 +000051#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
Marek Vasutce6971c2012-09-12 12:36:25 +020052#define CONFIG_CONS_INDEX 3
wdenkda27dcf2002-09-10 19:19:06 +000053
54/* allow to overwrite serial and ethaddr */
55#define CONFIG_ENV_OVERWRITE
56
wdenk71f95112003-06-15 22:40:42 +000057#define CONFIG_BAUDRATE 115200
wdenkda27dcf2002-09-10 19:19:06 +000058
wdenkda27dcf2002-09-10 19:19:06 +000059
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050060/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050061 * BOOTP options
62 */
63#define CONFIG_BOOTP_BOOTFILESIZE
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_GATEWAY
66#define CONFIG_BOOTP_HOSTNAME
67
68
69/*
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050070 * Command line configuration.
71 */
72#include <config_cmd_default.h>
73
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050074#define CONFIG_CMD_FAT
75
wdenkda27dcf2002-09-10 19:19:06 +000076
wdenk71f95112003-06-15 22:40:42 +000077#define CONFIG_BOOTDELAY 3
78#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
79#define CONFIG_NETMASK 255.255.0.0
80#define CONFIG_IPADDR 192.168.0.21
81#define CONFIG_SERVERIP 192.168.0.250
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +020082#define CONFIG_BOOTCOMMAND "bootm 80000"
wdenk71f95112003-06-15 22:40:42 +000083#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
84#define CONFIG_CMDLINE_TAG
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +020085#define CONFIG_TIMESTAMP
wdenkda27dcf2002-09-10 19:19:06 +000086
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050087#if defined(CONFIG_CMD_KGDB)
wdenk71f95112003-06-15 22:40:42 +000088#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenkda27dcf2002-09-10 19:19:06 +000089#endif
90
91/*
92 * Miscellaneous configurable options
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_HUSH_PARSER 1
wdenk71f95112003-06-15 22:40:42 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_LONGHELP /* undef to save memory */
97#ifdef CONFIG_SYS_HUSH_PARSER
98#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
wdenk71f95112003-06-15 22:40:42 +000099#else
wdenk71f95112003-06-15 22:40:42 +0000100#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
102#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
103#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
104#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
105#define CONFIG_SYS_DEVICE_NULLDEV 1
wdenkda27dcf2002-09-10 19:19:06 +0000106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
108#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenkda27dcf2002-09-10 19:19:06 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
wdenkda27dcf2002-09-10 19:19:06 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
wdenkda27dcf2002-09-10 19:19:06 +0000113
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100114#ifdef CONFIG_MMC
Marek Vasut831f8492012-09-30 10:09:49 +0000115#define CONFIG_GENERIC_MMC
116#define CONFIG_PXA_MMC_GENERIC
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100117#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100119#endif
wdenkda27dcf2002-09-10 19:19:06 +0000120
121/*
wdenkda27dcf2002-09-10 19:19:06 +0000122 * Physical Memory Map
123 */
wdenk71f95112003-06-15 22:40:42 +0000124#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
125#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
126#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
127#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
128#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
129#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
130#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
131#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
132#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
wdenkda27dcf2002-09-10 19:19:06 +0000133
wdenk71f95112003-06-15 22:40:42 +0000134#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
135#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
136#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
137#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
138#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
wdenkda27dcf2002-09-10 19:19:06 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_DRAM_BASE 0xa0000000
141#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenkda27dcf2002-09-10 19:19:06 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkda27dcf2002-09-10 19:19:06 +0000144
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200145#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Marek Vasut00d5ec92011-11-26 12:04:11 +0100146#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200147
wdenkda27dcf2002-09-10 19:19:06 +0000148#define FPGA_REGS_BASE_PHYSICAL 0x08000000
149
150/*
151 * GPIO settings
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_GPSR0_VAL 0x00008000
154#define CONFIG_SYS_GPSR1_VAL 0x00FC0382
155#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF
156#define CONFIG_SYS_GPCR0_VAL 0x00000000
157#define CONFIG_SYS_GPCR1_VAL 0x00000000
158#define CONFIG_SYS_GPCR2_VAL 0x00000000
159#define CONFIG_SYS_GPDR0_VAL 0x0060A800
160#define CONFIG_SYS_GPDR1_VAL 0x00FF0382
161#define CONFIG_SYS_GPDR2_VAL 0x0001C000
162#define CONFIG_SYS_GAFR0_L_VAL 0x98400000
163#define CONFIG_SYS_GAFR0_U_VAL 0x00002950
164#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558
165#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
166#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
167#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenkda27dcf2002-09-10 19:19:06 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_PSSR_VAL 0x20
wdenkda27dcf2002-09-10 19:19:06 +0000170
Marek Vasut3c43ca22010-10-20 20:55:44 +0200171#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
172#define CONFIG_SYS_CKEN 0x0
173
wdenkda27dcf2002-09-10 19:19:06 +0000174/*
175 * Memory settings
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MSC0_VAL 0x23F223F2
178#define CONFIG_SYS_MSC1_VAL 0x3FF1A441
179#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
180#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
181#define CONFIG_SYS_MDREFR_VAL 0x00018018
182#define CONFIG_SYS_MDMRS_VAL 0x00000000
wdenkda27dcf2002-09-10 19:19:06 +0000183
Marek Vasut3c43ca22010-10-20 20:55:44 +0200184#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
185#define CONFIG_SYS_SXCNFG_VAL 0x00000000
186
wdenkda27dcf2002-09-10 19:19:06 +0000187/*
188 * PCMCIA and CF Interfaces
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MECR_VAL 0x00000000
191#define CONFIG_SYS_MCMEM0_VAL 0x00010504
192#define CONFIG_SYS_MCMEM1_VAL 0x00010504
193#define CONFIG_SYS_MCATT0_VAL 0x00010504
194#define CONFIG_SYS_MCATT1_VAL 0x00010504
195#define CONFIG_SYS_MCIO0_VAL 0x00004715
196#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenkda27dcf2002-09-10 19:19:06 +0000197
wdenk71f95112003-06-15 22:40:42 +0000198#define _LED 0x08000010
199#define LED_BLANK 0x08000040
wdenkda27dcf2002-09-10 19:19:06 +0000200
201/*
202 * FLASH and environment organization
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
205#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkda27dcf2002-09-10 19:19:06 +0000206
207/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
209#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkda27dcf2002-09-10 19:19:06 +0000210
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +0200211/* NOTE: many default partitioning schemes assume the kernel starts at the
212 * second sector, not an environment. You have been warned!
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200215#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200216#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
217#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
218#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
wdenkda27dcf2002-09-10 19:19:06 +0000219
220
221/*
222 * FPGA Offsets
223 */
wdenk71f95112003-06-15 22:40:42 +0000224#define WHOAMI_OFFSET 0x00
225#define HEXLED_OFFSET 0x10
226#define BLANKLED_OFFSET 0x40
227#define DISCRETELED_OFFSET 0x40
228#define CNFG_SWITCHES_OFFSET 0x50
229#define USER_SWITCHES_OFFSET 0x60
230#define MISC_WR_OFFSET 0x80
231#define MISC_RD_OFFSET 0x90
232#define INT_MASK_OFFSET 0xC0
233#define INT_CLEAR_OFFSET 0xD0
234#define GP_OFFSET 0x100
wdenkda27dcf2002-09-10 19:19:06 +0000235
wdenk71f95112003-06-15 22:40:42 +0000236#endif /* __CONFIG_H */