blob: 532746dd88df1812a7693230521e096c3114b405 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302/**
3 * core.h - DesignWare USB3 DRD Core Header
4 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +05305 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05306 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +053010 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported
11 * to uboot.
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053012 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +053013 * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable
14 *
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053015 */
16
17#ifndef __DRIVERS_USB_DWC3_CORE_H
18#define __DRIVERS_USB_DWC3_CORE_H
19
Simon Glasscd93d622020-05-10 11:40:13 -060020#include <linux/bitops.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053021#include <linux/ioport.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053022
23#include <linux/usb/ch9.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053024#include <linux/usb/otg.h>
Frank Wang64697942020-05-26 11:34:30 +080025#include <linux/usb/phy.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053026
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053027#define DWC3_MSG_MAX 500
28
29/* Global constants */
30#define DWC3_EP0_BOUNCE_SIZE 512
31#define DWC3_ENDPOINTS_NUM 32
32#define DWC3_XHCI_RESOURCES_NUM 2
33
34#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
35#define DWC3_EVENT_SIZE 4 /* bytes */
36#define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
37#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
38#define DWC3_EVENT_TYPE_MASK 0xfe
39
40#define DWC3_EVENT_TYPE_DEV 0
41#define DWC3_EVENT_TYPE_CARKIT 3
42#define DWC3_EVENT_TYPE_I2C 4
43
44#define DWC3_DEVICE_EVENT_DISCONNECT 0
45#define DWC3_DEVICE_EVENT_RESET 1
46#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
47#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
48#define DWC3_DEVICE_EVENT_WAKEUP 4
49#define DWC3_DEVICE_EVENT_HIBER_REQ 5
50#define DWC3_DEVICE_EVENT_EOPF 6
51#define DWC3_DEVICE_EVENT_SOF 7
52#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
53#define DWC3_DEVICE_EVENT_CMD_CMPL 10
54#define DWC3_DEVICE_EVENT_OVERFLOW 11
55
56#define DWC3_GEVNTCOUNT_MASK 0xfffc
57#define DWC3_GSNPSID_MASK 0xffff0000
58#define DWC3_GSNPSREV_MASK 0xffff
59
60/* DWC3 registers memory space boundries */
61#define DWC3_XHCI_REGS_START 0x0
62#define DWC3_XHCI_REGS_END 0x7fff
63#define DWC3_GLOBALS_REGS_START 0xc100
64#define DWC3_GLOBALS_REGS_END 0xc6ff
65#define DWC3_DEVICE_REGS_START 0xc700
66#define DWC3_DEVICE_REGS_END 0xcbff
67#define DWC3_OTG_REGS_START 0xcc00
68#define DWC3_OTG_REGS_END 0xccff
69
70/* Global Registers */
71#define DWC3_GSBUSCFG0 0xc100
72#define DWC3_GSBUSCFG1 0xc104
73#define DWC3_GTXTHRCFG 0xc108
74#define DWC3_GRXTHRCFG 0xc10c
75#define DWC3_GCTL 0xc110
76#define DWC3_GEVTEN 0xc114
77#define DWC3_GSTS 0xc118
Jagan Tekidc184132020-05-26 11:33:48 +080078#define DWC3_GUCTL1 0xc11c
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053079#define DWC3_GSNPSID 0xc120
80#define DWC3_GGPIO 0xc124
81#define DWC3_GUID 0xc128
82#define DWC3_GUCTL 0xc12c
83#define DWC3_GBUSERRADDR0 0xc130
84#define DWC3_GBUSERRADDR1 0xc134
85#define DWC3_GPRTBIMAP0 0xc138
86#define DWC3_GPRTBIMAP1 0xc13c
87#define DWC3_GHWPARAMS0 0xc140
88#define DWC3_GHWPARAMS1 0xc144
89#define DWC3_GHWPARAMS2 0xc148
90#define DWC3_GHWPARAMS3 0xc14c
91#define DWC3_GHWPARAMS4 0xc150
92#define DWC3_GHWPARAMS5 0xc154
93#define DWC3_GHWPARAMS6 0xc158
94#define DWC3_GHWPARAMS7 0xc15c
95#define DWC3_GDBGFIFOSPACE 0xc160
96#define DWC3_GDBGLTSSM 0xc164
97#define DWC3_GPRTBIMAP_HS0 0xc180
98#define DWC3_GPRTBIMAP_HS1 0xc184
99#define DWC3_GPRTBIMAP_FS0 0xc188
100#define DWC3_GPRTBIMAP_FS1 0xc18c
101
102#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
103#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
104
105#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
106
107#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
108
109#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
110#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
111
112#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
113#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
114#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
115#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
116
117#define DWC3_GHWPARAMS8 0xc600
Michael Walled274cbb2021-10-15 15:15:21 +0200118#define DWC3_GFLADJ 0xc630
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530119
120/* Device Registers */
121#define DWC3_DCFG 0xc700
122#define DWC3_DCTL 0xc704
123#define DWC3_DEVTEN 0xc708
124#define DWC3_DSTS 0xc70c
125#define DWC3_DGCMDPAR 0xc710
126#define DWC3_DGCMD 0xc714
127#define DWC3_DALEPENA 0xc720
128#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
129#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
130#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
131#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
132
133/* OTG Registers */
134#define DWC3_OCFG 0xcc00
135#define DWC3_OCTL 0xcc04
136#define DWC3_OEVT 0xcc08
137#define DWC3_OEVTEN 0xcc0C
138#define DWC3_OSTS 0xcc10
139
140/* Bit fields */
141
Michael Wallef150b8d2021-10-15 15:15:22 +0200142/* Global SoC Bus Configuration INCRx Register 0 */
143#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
144#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
145#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
146#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
147#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
148#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
149#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
150#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
151#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
152
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530153/* Global Configuration Register */
154#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
155#define DWC3_GCTL_U2RSTECN (1 << 16)
156#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
157#define DWC3_GCTL_CLK_BUS (0)
158#define DWC3_GCTL_CLK_PIPE (1)
159#define DWC3_GCTL_CLK_PIPEHALF (2)
160#define DWC3_GCTL_CLK_MASK (3)
161
162#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
163#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
164#define DWC3_GCTL_PRTCAP_HOST 1
165#define DWC3_GCTL_PRTCAP_DEVICE 2
166#define DWC3_GCTL_PRTCAP_OTG 3
167
168#define DWC3_GCTL_CORESOFTRESET (1 << 11)
169#define DWC3_GCTL_SOFITPSYNC (1 << 10)
170#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
171#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
172#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
173#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
174#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
175#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
176
Jagan Tekifafaa022020-05-26 11:34:29 +0800177/* Global User Control Register */
178#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
179
Jagan Tekidc184132020-05-26 11:33:48 +0800180/* Global User Control 1 Register */
181#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
182#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
183
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530184/* Global USB2 PHY Configuration Register */
185#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
Frank Wangb34f8b52020-05-26 11:33:47 +0800186#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530187#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
Frank Wang7bb62702020-05-26 11:33:46 +0800188#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
Jagan Teki5c207282019-12-18 13:00:02 +0530189#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
190#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
191#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
192#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
193#define USBTRDTIM_UTMI_8_BIT 9
194#define USBTRDTIM_UTMI_16_BIT 5
195#define UTMI_PHYIF_16_BIT 1
196#define UTMI_PHYIF_8_BIT 0
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530197
198/* Global USB3 PIPE Control Register */
199#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
200#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
201#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
202#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
203#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
204#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
205#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
206#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
207#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
208#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
209#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
210#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
211
212/* Global TX Fifo Size Register */
213#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
214#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
215
216/* Global Event Size Registers */
217#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
218#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
219
220/* Global HWPARAMS1 Register */
221#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
222#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
223#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
224#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
225#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
226#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
227
228/* Global HWPARAMS3 Register */
229#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
230#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
231#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
232#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
233#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
234#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
235#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
236#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
237#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
238#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
239#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
240
241/* Global HWPARAMS4 Register */
242#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
243#define DWC3_MAX_HIBER_SCRATCHBUFS 15
244
245/* Global HWPARAMS6 Register */
246#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
247
Michael Walled274cbb2021-10-15 15:15:21 +0200248/* Global Frame Length Adjustment Register */
249#define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
250#define DWC3_GFLADJ_30MHZ_MASK 0x3f
Sean Andersonc55ac512022-11-27 15:31:55 +0100251#define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8)
252#define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24)
253#define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31)
Michael Walled274cbb2021-10-15 15:15:21 +0200254
Balaji Prakash J57548e82022-11-27 15:31:53 +0100255/* Global User Control Register*/
256#define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000
257#define DWC3_GUCTL_REFCLKPER_SEL 22
258
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530259/* Device Configuration Register */
260#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
261#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
262
263#define DWC3_DCFG_SPEED_MASK (7 << 0)
264#define DWC3_DCFG_SUPERSPEED (4 << 0)
265#define DWC3_DCFG_HIGHSPEED (0 << 0)
266#define DWC3_DCFG_FULLSPEED2 (1 << 0)
267#define DWC3_DCFG_LOWSPEED (2 << 0)
268#define DWC3_DCFG_FULLSPEED1 (3 << 0)
269
270#define DWC3_DCFG_LPM_CAP (1 << 22)
271
272/* Device Control Register */
273#define DWC3_DCTL_RUN_STOP (1 << 31)
274#define DWC3_DCTL_CSFTRST (1 << 30)
275#define DWC3_DCTL_LSFTRST (1 << 29)
276
277#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
278#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
279
280#define DWC3_DCTL_APPL1RES (1 << 23)
281
282/* These apply for core versions 1.87a and earlier */
283#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
284#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
285#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
286#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
287#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
288#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
289#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
290
291/* These apply for core versions 1.94a and later */
292#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
293#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
294
295#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
296#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
297#define DWC3_DCTL_CRS (1 << 17)
298#define DWC3_DCTL_CSS (1 << 16)
299
300#define DWC3_DCTL_INITU2ENA (1 << 12)
301#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
302#define DWC3_DCTL_INITU1ENA (1 << 10)
303#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
304#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
305
306#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
307#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
308
309#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
310#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
311#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
312#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
313#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
314#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
315#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
316
317/* Device Event Enable Register */
318#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
319#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
320#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
321#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
322#define DWC3_DEVTEN_SOFEN (1 << 7)
323#define DWC3_DEVTEN_EOPFEN (1 << 6)
324#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
325#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
326#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
327#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
328#define DWC3_DEVTEN_USBRSTEN (1 << 1)
329#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
330
331/* Device Status Register */
332#define DWC3_DSTS_DCNRD (1 << 29)
333
334/* This applies for core versions 1.87a and earlier */
335#define DWC3_DSTS_PWRUPREQ (1 << 24)
336
337/* These apply for core versions 1.94a and later */
338#define DWC3_DSTS_RSS (1 << 25)
339#define DWC3_DSTS_SSS (1 << 24)
340
341#define DWC3_DSTS_COREIDLE (1 << 23)
342#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
343
344#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
345#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
346
347#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
348
349#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
350#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
351
352#define DWC3_DSTS_CONNECTSPD (7 << 0)
353
354#define DWC3_DSTS_SUPERSPEED (4 << 0)
355#define DWC3_DSTS_HIGHSPEED (0 << 0)
356#define DWC3_DSTS_FULLSPEED2 (1 << 0)
357#define DWC3_DSTS_LOWSPEED (2 << 0)
358#define DWC3_DSTS_FULLSPEED1 (3 << 0)
359
360/* Device Generic Command Register */
361#define DWC3_DGCMD_SET_LMP 0x01
362#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
363#define DWC3_DGCMD_XMIT_FUNCTION 0x03
364
365/* These apply for core versions 1.94a and later */
366#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
367#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
368
369#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
370#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
371#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
372#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
373
374#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
375#define DWC3_DGCMD_CMDACT (1 << 10)
376#define DWC3_DGCMD_CMDIOC (1 << 8)
377
378/* Device Generic Command Parameter Register */
379#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
380#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
381#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
382#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
383#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
384#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
385
386/* Device Endpoint Command Register */
387#define DWC3_DEPCMD_PARAM_SHIFT 16
388#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
389#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
390#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
391#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
392#define DWC3_DEPCMD_CMDACT (1 << 10)
393#define DWC3_DEPCMD_CMDIOC (1 << 8)
394
395#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
396#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
397#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
398#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
399#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
400#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
401/* This applies for core versions 1.90a and earlier */
402#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
403/* This applies for core versions 1.94a and later */
404#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
405#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
406#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
407
408/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
409#define DWC3_DALEPENA_EP(n) (1 << n)
410
411#define DWC3_DEPCMD_TYPE_CONTROL 0
412#define DWC3_DEPCMD_TYPE_ISOC 1
413#define DWC3_DEPCMD_TYPE_BULK 2
414#define DWC3_DEPCMD_TYPE_INTR 3
415
416/* Structures */
417
418struct dwc3_trb;
419
420/**
421 * struct dwc3_event_buffer - Software event buffer representation
422 * @buf: _THE_ buffer
423 * @length: size of this buffer
424 * @lpos: event offset
425 * @count: cache of last read event count register
426 * @flags: flags related to this event buffer
427 * @dma: dma_addr_t
428 * @dwc: pointer to DWC controller
429 */
430struct dwc3_event_buffer {
431 void *buf;
432 unsigned length;
433 unsigned int lpos;
434 unsigned int count;
435 unsigned int flags;
436
Lukasz Majewski2252d152015-03-03 17:32:08 +0100437#define DWC3_EVENT_PENDING (1UL << 0)
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530438
439 dma_addr_t dma;
440
441 struct dwc3 *dwc;
442};
443
444#define DWC3_EP_FLAG_STALLED (1 << 0)
445#define DWC3_EP_FLAG_WEDGED (1 << 1)
446
447#define DWC3_EP_DIRECTION_TX true
448#define DWC3_EP_DIRECTION_RX false
449
450#define DWC3_TRB_NUM 32
451#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
452
453/**
454 * struct dwc3_ep - device side endpoint representation
455 * @endpoint: usb endpoint
456 * @request_list: list of requests for this endpoint
457 * @req_queued: list of requests on this ep which have TRBs setup
458 * @trb_pool: array of transaction buffers
459 * @trb_pool_dma: dma address of @trb_pool
460 * @free_slot: next slot which is going to be used
461 * @busy_slot: first slot which is owned by HW
462 * @desc: usb_endpoint_descriptor pointer
463 * @dwc: pointer to DWC controller
464 * @saved_state: ep state saved during hibernation
465 * @flags: endpoint flags (wedged, stalled, ...)
466 * @current_trb: index of current used trb
467 * @number: endpoint number (1 - 15)
468 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
469 * @resource_index: Resource transfer index
470 * @interval: the interval on which the ISOC transfer is started
471 * @name: a human readable name e.g. ep1out-bulk
472 * @direction: true for TX, false for RX
473 * @stream_capable: true when streams are enabled
474 */
475struct dwc3_ep {
476 struct usb_ep endpoint;
477 struct list_head request_list;
478 struct list_head req_queued;
479
480 struct dwc3_trb *trb_pool;
481 dma_addr_t trb_pool_dma;
482 u32 free_slot;
483 u32 busy_slot;
484 const struct usb_ss_ep_comp_descriptor *comp_desc;
485 struct dwc3 *dwc;
486
487 u32 saved_state;
488 unsigned flags;
489#define DWC3_EP_ENABLED (1 << 0)
490#define DWC3_EP_STALL (1 << 1)
491#define DWC3_EP_WEDGE (1 << 2)
492#define DWC3_EP_BUSY (1 << 4)
493#define DWC3_EP_PENDING_REQUEST (1 << 5)
494#define DWC3_EP_MISSED_ISOC (1 << 6)
495
496 /* This last one is specific to EP0 */
497#define DWC3_EP0_DIR_IN (1 << 31)
498
499 unsigned current_trb;
500
501 u8 number;
502 u8 type;
503 u8 resource_index;
504 u32 interval;
505
506 char name[20];
507
508 unsigned direction:1;
509 unsigned stream_capable:1;
510};
511
512enum dwc3_phy {
513 DWC3_PHY_UNKNOWN = 0,
514 DWC3_PHY_USB3,
515 DWC3_PHY_USB2,
516};
517
518enum dwc3_ep0_next {
519 DWC3_EP0_UNKNOWN = 0,
520 DWC3_EP0_COMPLETE,
521 DWC3_EP0_NRDY_DATA,
522 DWC3_EP0_NRDY_STATUS,
523};
524
525enum dwc3_ep0_state {
526 EP0_UNCONNECTED = 0,
527 EP0_SETUP_PHASE,
528 EP0_DATA_PHASE,
529 EP0_STATUS_PHASE,
530};
531
532enum dwc3_link_state {
533 /* In SuperSpeed */
534 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
535 DWC3_LINK_STATE_U1 = 0x01,
536 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
537 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
538 DWC3_LINK_STATE_SS_DIS = 0x04,
539 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
540 DWC3_LINK_STATE_SS_INACT = 0x06,
541 DWC3_LINK_STATE_POLL = 0x07,
542 DWC3_LINK_STATE_RECOV = 0x08,
543 DWC3_LINK_STATE_HRESET = 0x09,
544 DWC3_LINK_STATE_CMPLY = 0x0a,
545 DWC3_LINK_STATE_LPBK = 0x0b,
546 DWC3_LINK_STATE_RESET = 0x0e,
547 DWC3_LINK_STATE_RESUME = 0x0f,
548 DWC3_LINK_STATE_MASK = 0x0f,
549};
550
551/* TRB Length, PCM and Status */
552#define DWC3_TRB_SIZE_MASK (0x00ffffff)
553#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
554#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
555#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
556
557#define DWC3_TRBSTS_OK 0
558#define DWC3_TRBSTS_MISSED_ISOC 1
559#define DWC3_TRBSTS_SETUP_PENDING 2
560#define DWC3_TRB_STS_XFER_IN_PROG 4
561
562/* TRB Control */
563#define DWC3_TRB_CTRL_HWO (1 << 0)
564#define DWC3_TRB_CTRL_LST (1 << 1)
565#define DWC3_TRB_CTRL_CHN (1 << 2)
566#define DWC3_TRB_CTRL_CSP (1 << 3)
567#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
568#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
569#define DWC3_TRB_CTRL_IOC (1 << 11)
570#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
571
572#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
573#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
574#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
575#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
576#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
577#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
578#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
579#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
580
581/**
582 * struct dwc3_trb - transfer request block (hw format)
583 * @bpl: DW0-3
584 * @bph: DW4-7
585 * @size: DW8-B
586 * @trl: DWC-F
587 */
588struct dwc3_trb {
589 u32 bpl;
590 u32 bph;
591 u32 size;
592 u32 ctrl;
593} __packed;
594
595/**
596 * dwc3_hwparams - copy of HWPARAMS registers
597 * @hwparams0 - GHWPARAMS0
598 * @hwparams1 - GHWPARAMS1
599 * @hwparams2 - GHWPARAMS2
600 * @hwparams3 - GHWPARAMS3
601 * @hwparams4 - GHWPARAMS4
602 * @hwparams5 - GHWPARAMS5
603 * @hwparams6 - GHWPARAMS6
604 * @hwparams7 - GHWPARAMS7
605 * @hwparams8 - GHWPARAMS8
606 */
607struct dwc3_hwparams {
608 u32 hwparams0;
609 u32 hwparams1;
610 u32 hwparams2;
611 u32 hwparams3;
612 u32 hwparams4;
613 u32 hwparams5;
614 u32 hwparams6;
615 u32 hwparams7;
616 u32 hwparams8;
617};
618
619/* HWPARAMS0 */
620#define DWC3_MODE(n) ((n) & 0x7)
621
622#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
623
624/* HWPARAMS1 */
625#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
626
627/* HWPARAMS3 */
628#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
629#define DWC3_NUM_EPS_MASK (0x3f << 12)
630#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
631 (DWC3_NUM_EPS_MASK)) >> 12)
632#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
633 (DWC3_NUM_IN_EPS_MASK)) >> 18)
634
635/* HWPARAMS7 */
636#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
637
638struct dwc3_request {
639 struct usb_request request;
640 struct list_head list;
641 struct dwc3_ep *dep;
642 u32 start_slot;
643
644 u8 epnum;
645 struct dwc3_trb *trb;
646 dma_addr_t trb_dma;
647
648 unsigned direction:1;
649 unsigned mapped:1;
650 unsigned queued:1;
651};
652
653/*
654 * struct dwc3_scratchpad_array - hibernation scratchpad array
655 * (format defined by hw)
656 */
657struct dwc3_scratchpad_array {
658 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
659};
660
661/**
662 * struct dwc3 - representation of our controller
663 * @ctrl_req: usb control request which is used for ep0
664 * @ep0_trb: trb which is used for the ctrl_req
665 * @ep0_bounce: bounce buffer for ep0
666 * @setup_buf: used while precessing STD USB requests
667 * @ctrl_req_addr: dma address of ctrl_req
668 * @ep0_trb: dma address of ep0_trb
669 * @ep0_usb_req: dummy req used while handling STD USB requests
670 * @ep0_bounce_addr: dma address of ep0_bounce
671 * @scratch_addr: dma address of scratchbuf
672 * @lock: for synchronizing
673 * @dev: pointer to our struct device
674 * @xhci: pointer to our xHCI child
675 * @event_buffer_list: a list of event buffers
676 * @gadget: device side representation of the peripheral controller
677 * @gadget_driver: pointer to the gadget driver
Marek Vasut8ae84e62022-11-27 15:31:52 +0100678 * @ref_clk: reference clock
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530679 * @regs: base address for our registers
680 * @regs_size: address space size
Balaji Prakash J57548e82022-11-27 15:31:53 +0100681 * @ref_clk_per: reference clock period configuration
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530682 * @nr_scratch: number of scratch buffers
683 * @num_event_buffers: calculated number of event buffers
684 * @u1u2: only used on revisions <1.83a for workaround
685 * @maximum_speed: maximum speed requested (mainly for testing purposes)
686 * @revision: revision register contents
687 * @dr_mode: requested mode of operation
Frank Wang64697942020-05-26 11:34:30 +0800688 * @hsphy_mode: UTMI phy mode, one of following:
689 * - USBPHY_INTERFACE_MODE_UTMI
690 * - USBPHY_INTERFACE_MODE_UTMIW
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530691 * @dcfg: saved contents of DCFG register
692 * @gctl: saved contents of GCTL register
693 * @isoch_delay: wValue from Set Isochronous Delay request;
694 * @u2sel: parameter from Set SEL request.
695 * @u2pel: parameter from Set SEL request.
696 * @u1sel: parameter from Set SEL request.
697 * @u1pel: parameter from Set SEL request.
698 * @num_out_eps: number of out endpoints
699 * @num_in_eps: number of in endpoints
700 * @ep0_next_event: hold the next expected event
701 * @ep0state: state of endpoint zero
702 * @link_state: link state
703 * @speed: device speed (super, high, full, low)
704 * @mem: points to start of memory which is used for this struct.
705 * @hwparams: copy of hwparams registers
706 * @root: debugfs root folder pointer
707 * @regset: debugfs pointer to regdump file
708 * @test_mode: true when we're entering a USB test mode
709 * @test_mode_nr: test feature selector
710 * @lpm_nyet_threshold: LPM NYET response threshold
711 * @hird_threshold: HIRD threshold
712 * @delayed_status: true when gadget driver asks for delayed status
713 * @ep0_bounced: true when we used bounce buffer
714 * @ep0_expect_in: true when we expect a DATA IN transfer
715 * @has_hibernation: true when dwc3 was configured with Hibernation
716 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
717 * there's now way for software to detect this in runtime.
718 * @is_utmi_l1_suspend: the core asserts output signal
Wolfgang Denk0cf207e2021-09-27 17:42:39 +0200719 * 0 - utmi_sleep_n
720 * 1 - utmi_l1_suspend_n
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530721 * @is_selfpowered: true when we are selfpowered
722 * @is_fpga: true when we are using the FPGA board
723 * @needs_fifo_resize: not all users might want fifo resizing, flag it
724 * @pullups_connected: true when Run/Stop bit is set
725 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
726 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
727 * @start_config_issued: true when StartConfig command has been issued
728 * @three_stage_setup: set if we perform a three phase setup
729 * @disable_scramble_quirk: set if we enable the disable scramble quirk
730 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
731 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
732 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
733 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
734 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
735 * @lfps_filter_quirk: set if we enable LFPS filter quirk
736 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
737 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
738 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
739 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
740 * @tx_de_emphasis: Tx de-emphasis value
Wolfgang Denk0cf207e2021-09-27 17:42:39 +0200741 * 0 - -6dB de-emphasis
742 * 1 - -3.5dB de-emphasis
743 * 2 - No de-emphasis
744 * 3 - Reserved
Kishon Vijay Abraham I793d3472015-02-23 18:40:05 +0530745 * @index: index of _this_ controller
746 * @list: to maintain the list of dwc3 controllers
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530747 */
748struct dwc3 {
749 struct usb_ctrlrequest *ctrl_req;
750 struct dwc3_trb *ep0_trb;
751 void *ep0_bounce;
752 void *scratchbuf;
753 u8 *setup_buf;
754 dma_addr_t ctrl_req_addr;
755 dma_addr_t ep0_trb_addr;
756 dma_addr_t ep0_bounce_addr;
757 dma_addr_t scratch_addr;
758 struct dwc3_request ep0_usb_req;
759
760 /* device lock */
761 spinlock_t lock;
762
Sven Schwermerfd09c202018-11-21 08:43:56 +0100763#if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB)
Mugunthan V N23ba2d62018-05-18 13:15:04 +0200764 struct udevice *dev;
765#else
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530766 struct device *dev;
Mugunthan V N23ba2d62018-05-18 13:15:04 +0200767#endif
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530768
769 struct platform_device *xhci;
770 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
771
772 struct dwc3_event_buffer **ev_buffs;
773 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
774
775 struct usb_gadget gadget;
776 struct usb_gadget_driver *gadget_driver;
777
Marek Vasut8ae84e62022-11-27 15:31:52 +0100778 struct clk *ref_clk;
779
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530780 void __iomem *regs;
781 size_t regs_size;
782
783 enum usb_dr_mode dr_mode;
Frank Wang64697942020-05-26 11:34:30 +0800784 enum usb_phy_interface hsphy_mode;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530785
786 /* used for suspend/resume */
787 u32 dcfg;
788 u32 gctl;
789
790 u32 nr_scratch;
791 u32 num_event_buffers;
792 u32 u1u2;
793 u32 maximum_speed;
794 u32 revision;
795
796#define DWC3_REVISION_173A 0x5533173a
797#define DWC3_REVISION_175A 0x5533175a
798#define DWC3_REVISION_180A 0x5533180a
799#define DWC3_REVISION_183A 0x5533183a
800#define DWC3_REVISION_185A 0x5533185a
801#define DWC3_REVISION_187A 0x5533187a
802#define DWC3_REVISION_188A 0x5533188a
803#define DWC3_REVISION_190A 0x5533190a
804#define DWC3_REVISION_194A 0x5533194a
805#define DWC3_REVISION_200A 0x5533200a
806#define DWC3_REVISION_202A 0x5533202a
807#define DWC3_REVISION_210A 0x5533210a
808#define DWC3_REVISION_220A 0x5533220a
809#define DWC3_REVISION_230A 0x5533230a
810#define DWC3_REVISION_240A 0x5533240a
811#define DWC3_REVISION_250A 0x5533250a
812#define DWC3_REVISION_260A 0x5533260a
813#define DWC3_REVISION_270A 0x5533270a
814#define DWC3_REVISION_280A 0x5533280a
Jagan Tekidc184132020-05-26 11:33:48 +0800815#define DWC3_REVISION_290A 0x5533290a
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530816
817 enum dwc3_ep0_next ep0_next_event;
818 enum dwc3_ep0_state ep0state;
819 enum dwc3_link_state link_state;
820
821 u16 isoch_delay;
822 u16 u2sel;
823 u16 u2pel;
824 u8 u1sel;
825 u8 u1pel;
826
827 u8 speed;
828
829 u8 num_out_eps;
830 u8 num_in_eps;
831
832 void *mem;
833
834 struct dwc3_hwparams hwparams;
835 struct dentry *root;
836 struct debugfs_regset32 *regset;
837
838 u8 test_mode;
839 u8 test_mode_nr;
840 u8 lpm_nyet_threshold;
841 u8 hird_threshold;
Michael Walled274cbb2021-10-15 15:15:21 +0200842 u32 fladj;
Balaji Prakash J57548e82022-11-27 15:31:53 +0100843 u32 ref_clk_per;
Michael Wallef150b8d2021-10-15 15:15:22 +0200844 u8 incrx_mode;
845 u32 incrx_size;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530846
847 unsigned delayed_status:1;
848 unsigned ep0_bounced:1;
849 unsigned ep0_expect_in:1;
850 unsigned has_hibernation:1;
851 unsigned has_lpm_erratum:1;
852 unsigned is_utmi_l1_suspend:1;
853 unsigned is_selfpowered:1;
854 unsigned is_fpga:1;
855 unsigned needs_fifo_resize:1;
856 unsigned pullups_connected:1;
857 unsigned resize_fifos:1;
858 unsigned setup_packet_pending:1;
859 unsigned start_config_issued:1;
860 unsigned three_stage_setup:1;
861
862 unsigned disable_scramble_quirk:1;
863 unsigned u2exit_lfps_quirk:1;
864 unsigned u2ss_inp3_quirk:1;
865 unsigned req_p1p2p3_quirk:1;
866 unsigned del_p1p2p3_quirk:1;
867 unsigned del_phy_power_chg_quirk:1;
868 unsigned lfps_filter_quirk:1;
869 unsigned rx_detect_poll_quirk:1;
870 unsigned dis_u3_susphy_quirk:1;
871 unsigned dis_u2_susphy_quirk:1;
Jagan Teki73ca0142020-05-06 13:20:25 +0530872 unsigned dis_del_phy_power_chg_quirk:1;
Jagan Tekidc184132020-05-26 11:33:48 +0800873 unsigned dis_tx_ipgap_linecheck_quirk:1;
Frank Wang7bb62702020-05-26 11:33:46 +0800874 unsigned dis_enblslpm_quirk:1;
Frank Wangb34f8b52020-05-26 11:33:47 +0800875 unsigned dis_u2_freeclk_exists_quirk:1;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530876
877 unsigned tx_de_emphasis_quirk:1;
878 unsigned tx_de_emphasis:2;
Kishon Vijay Abraham I793d3472015-02-23 18:40:05 +0530879 int index;
880 struct list_head list;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530881};
882
Michael Wallef150b8d2021-10-15 15:15:22 +0200883#define INCRX_BURST_MODE 0
884#define INCRX_UNDEF_LENGTH_BURST_MODE 1
885
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530886/* -------------------------------------------------------------------------- */
887
888/* -------------------------------------------------------------------------- */
889
890struct dwc3_event_type {
891 u32 is_devspec:1;
892 u32 type:7;
893 u32 reserved8_31:24;
894} __packed;
895
896#define DWC3_DEPEVT_XFERCOMPLETE 0x01
897#define DWC3_DEPEVT_XFERINPROGRESS 0x02
898#define DWC3_DEPEVT_XFERNOTREADY 0x03
899#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
900#define DWC3_DEPEVT_STREAMEVT 0x06
901#define DWC3_DEPEVT_EPCMDCMPLT 0x07
902
903/**
Kishon Vijay Abraham Ib6d959a2015-02-23 18:40:00 +0530904 * dwc3_ep_event_string - returns event name
905 * @event: then event code
906 */
907static inline const char *dwc3_ep_event_string(u8 event)
908{
909 switch (event) {
910 case DWC3_DEPEVT_XFERCOMPLETE:
911 return "Transfer Complete";
912 case DWC3_DEPEVT_XFERINPROGRESS:
913 return "Transfer In-Progress";
914 case DWC3_DEPEVT_XFERNOTREADY:
915 return "Transfer Not Ready";
916 case DWC3_DEPEVT_RXTXFIFOEVT:
917 return "FIFO";
918 case DWC3_DEPEVT_STREAMEVT:
919 return "Stream";
920 case DWC3_DEPEVT_EPCMDCMPLT:
921 return "Endpoint Command Complete";
922 }
923
924 return "UNKNOWN";
925}
926
927/**
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530928 * struct dwc3_event_depvt - Device Endpoint Events
929 * @one_bit: indicates this is an endpoint event (not used)
930 * @endpoint_number: number of the endpoint
931 * @endpoint_event: The event we have:
932 * 0x00 - Reserved
933 * 0x01 - XferComplete
934 * 0x02 - XferInProgress
935 * 0x03 - XferNotReady
936 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
937 * 0x05 - Reserved
938 * 0x06 - StreamEvt
939 * 0x07 - EPCmdCmplt
940 * @reserved11_10: Reserved, don't use.
941 * @status: Indicates the status of the event. Refer to databook for
942 * more information.
943 * @parameters: Parameters of the current event. Refer to databook for
944 * more information.
945 */
946struct dwc3_event_depevt {
947 u32 one_bit:1;
948 u32 endpoint_number:5;
949 u32 endpoint_event:4;
950 u32 reserved11_10:2;
951 u32 status:4;
952
953/* Within XferNotReady */
954#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
955
956/* Within XferComplete */
957#define DEPEVT_STATUS_BUSERR (1 << 0)
958#define DEPEVT_STATUS_SHORT (1 << 1)
959#define DEPEVT_STATUS_IOC (1 << 2)
960#define DEPEVT_STATUS_LST (1 << 3)
961
962/* Stream event only */
963#define DEPEVT_STREAMEVT_FOUND 1
964#define DEPEVT_STREAMEVT_NOTFOUND 2
965
966/* Control-only Status */
967#define DEPEVT_STATUS_CONTROL_DATA 1
968#define DEPEVT_STATUS_CONTROL_STATUS 2
969
970 u32 parameters:16;
971} __packed;
972
973/**
974 * struct dwc3_event_devt - Device Events
975 * @one_bit: indicates this is a non-endpoint event (not used)
976 * @device_event: indicates it's a device event. Should read as 0x00
977 * @type: indicates the type of device event.
978 * 0 - DisconnEvt
979 * 1 - USBRst
980 * 2 - ConnectDone
981 * 3 - ULStChng
982 * 4 - WkUpEvt
983 * 5 - Reserved
984 * 6 - EOPF
985 * 7 - SOF
986 * 8 - Reserved
987 * 9 - ErrticErr
988 * 10 - CmdCmplt
989 * 11 - EvntOverflow
990 * 12 - VndrDevTstRcved
991 * @reserved15_12: Reserved, not used
992 * @event_info: Information about this event
993 * @reserved31_25: Reserved, not used
994 */
995struct dwc3_event_devt {
996 u32 one_bit:1;
997 u32 device_event:7;
998 u32 type:4;
999 u32 reserved15_12:4;
1000 u32 event_info:9;
1001 u32 reserved31_25:7;
1002} __packed;
1003
1004/**
1005 * struct dwc3_event_gevt - Other Core Events
1006 * @one_bit: indicates this is a non-endpoint event (not used)
1007 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1008 * @phy_port_number: self-explanatory
1009 * @reserved31_12: Reserved, not used.
1010 */
1011struct dwc3_event_gevt {
1012 u32 one_bit:1;
1013 u32 device_event:7;
1014 u32 phy_port_number:4;
1015 u32 reserved31_12:20;
1016} __packed;
1017
1018/**
1019 * union dwc3_event - representation of Event Buffer contents
1020 * @raw: raw 32-bit event
1021 * @type: the type of the event
1022 * @depevt: Device Endpoint Event
1023 * @devt: Device Event
1024 * @gevt: Global Event
1025 */
1026union dwc3_event {
1027 u32 raw;
1028 struct dwc3_event_type type;
1029 struct dwc3_event_depevt depevt;
1030 struct dwc3_event_devt devt;
1031 struct dwc3_event_gevt gevt;
1032};
1033
1034/**
1035 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1036 * parameters
1037 * @param2: third parameter
1038 * @param1: second parameter
1039 * @param0: first parameter
1040 */
1041struct dwc3_gadget_ep_cmd_params {
1042 u32 param2;
1043 u32 param1;
1044 u32 param0;
1045};
1046
1047/*
1048 * DWC3 Features to be used as Driver Data
1049 */
1050
1051#define DWC3_HAS_PERIPHERAL BIT(0)
1052#define DWC3_HAS_XHCI BIT(1)
1053#define DWC3_HAS_OTG BIT(3)
1054
1055/* prototypes */
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301056int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
Jean-Jacques Hiblotba6c5f72019-09-11 11:33:52 +02001057void dwc3_of_parse(struct dwc3 *dwc);
Mugunthan V N23ba2d62018-05-18 13:15:04 +02001058int dwc3_init(struct dwc3 *dwc);
1059void dwc3_remove(struct dwc3 *dwc);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301060
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301061static inline int dwc3_host_init(struct dwc3 *dwc)
1062{ return 0; }
1063static inline void dwc3_host_exit(struct dwc3 *dwc)
1064{ }
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301065
Kishon Vijay Abraham I9848e572015-02-23 18:39:54 +05301066#ifdef CONFIG_USB_DWC3_GADGET
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301067int dwc3_gadget_init(struct dwc3 *dwc);
1068void dwc3_gadget_exit(struct dwc3 *dwc);
1069int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1070int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1071int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1072int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1073 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1074int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1075#else
1076static inline int dwc3_gadget_init(struct dwc3 *dwc)
1077{ return 0; }
1078static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1079{ }
1080static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1081{ return 0; }
1082static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1083{ return 0; }
1084static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1085 enum dwc3_link_state state)
1086{ return 0; }
1087
1088static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1089 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1090{ return 0; }
1091static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1092 int cmd, u32 param)
1093{ return 0; }
1094#endif
1095
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301096#endif /* __DRIVERS_USB_DWC3_CORE_H */