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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / e31dc61e7dc89ce900426828c936208a6638cf8c / . / drivers / net / ftgmac100.h
blob: 46b7369c8304ccd359c8556cb660b02a8074425e [file] [log] [blame]
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800[diff] [blame]1/*
2 * Faraday FTGMAC100 Ethernet
3 *
4 * (C) Copyright 2010 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
6 *
7 * (C) Copyright 2010 Andes Technology
8 * Macpaul Lin <macpaul@andestech.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __FTGMAC100_H
26#define __FTGMAC100_H
27
28/* The registers offset table of ftgmac100 */
29struct ftgmac100 {
30 unsigned int isr; /* 0x00 */
31 unsigned int ier; /* 0x04 */
32 unsigned int mac_madr; /* 0x08 */
33 unsigned int mac_ladr; /* 0x0c */
34 unsigned int maht0; /* 0x10 */
35 unsigned int maht1; /* 0x14 */
36 unsigned int txpd; /* 0x18 */
37 unsigned int rxpd; /* 0x1c */
38 unsigned int txr_badr; /* 0x20 */
39 unsigned int rxr_badr; /* 0x24 */
40 unsigned int hptxpd; /* 0x28 */
41 unsigned int hptxpd_badr; /* 0x2c */
42 unsigned int itc; /* 0x30 */
43 unsigned int aptc; /* 0x34 */
44 unsigned int dblac; /* 0x38 */
45 unsigned int dmafifos; /* 0x3c */
46 unsigned int revr; /* 0x40 */
47 unsigned int fear; /* 0x44 */
48 unsigned int tpafcr; /* 0x48 */
49 unsigned int rbsr; /* 0x4c */
50 unsigned int maccr; /* 0x50 */
51 unsigned int macsr; /* 0x54 */
52 unsigned int tm; /* 0x58 */
53 unsigned int resv1; /* 0x5c */ /* not defined in spec */
54 unsigned int phycr; /* 0x60 */
55 unsigned int phydata; /* 0x64 */
56 unsigned int fcr; /* 0x68 */
57 unsigned int bpr; /* 0x6c */
58 unsigned int wolcr; /* 0x70 */
59 unsigned int wolsr; /* 0x74 */
60 unsigned int wfcrc; /* 0x78 */
61 unsigned int resv2; /* 0x7c */ /* not defined in spec */
62 unsigned int wfbm1; /* 0x80 */
63 unsigned int wfbm2; /* 0x84 */
64 unsigned int wfbm3; /* 0x88 */
65 unsigned int wfbm4; /* 0x8c */
66 unsigned int nptxr_ptr; /* 0x90 */
67 unsigned int hptxr_ptr; /* 0x94 */
68 unsigned int rxr_ptr; /* 0x98 */
69 unsigned int resv3; /* 0x9c */ /* not defined in spec */
70 unsigned int tx; /* 0xa0 */
71 unsigned int tx_mcol_scol; /* 0xa4 */
72 unsigned int tx_ecol_fail; /* 0xa8 */
73 unsigned int tx_lcol_und; /* 0xac */
74 unsigned int rx; /* 0xb0 */
75 unsigned int rx_bc; /* 0xb4 */
76 unsigned int rx_mc; /* 0xb8 */
77 unsigned int rx_pf_aep; /* 0xbc */
78 unsigned int rx_runt; /* 0xc0 */
79 unsigned int rx_crcer_ftl; /* 0xc4 */
80 unsigned int rx_col_lost; /* 0xc8 */
81};
82
83/*
84 * Interrupt status register & interrupt enable register
85 */
86#define FTGMAC100_INT_RPKT_BUF (1 << 0)
87#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
88#define FTGMAC100_INT_NO_RXBUF (1 << 2)
89#define FTGMAC100_INT_RPKT_LOST (1 << 3)
90#define FTGMAC100_INT_XPKT_ETH (1 << 4)
91#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
92#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
93#define FTGMAC100_INT_XPKT_LOST (1 << 7)
94#define FTGMAC100_INT_AHB_ERR (1 << 8)
95#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
96#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
97
98/*
99 * Interrupt timer control register
100 */
101#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
102#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
103#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
104#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
105#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
106#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
107
108/*
109 * Automatic polling timer control register
110 */
111#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
112#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
113#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
114#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
115
116/*
117 * DMA burst length and arbitration control register
118 */
119#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
120#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
121#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
122#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
123#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
124#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
125#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
126#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
127#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
128
129/*
130 * DMA FIFO status register
131 */
132#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf)
133#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf)
134#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7)
135#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
136#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
137#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
138#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
139#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
140#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
141#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
142#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
143#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
144
145/*
146 * Receive buffer size register
147 */
148#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff)
149
150/*
151 * MAC control register
152 */
153#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
154#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
155#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
156#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
157#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
158#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
159#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
160#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
161#define FTGMAC100_MACCR_FULLDUP (1 << 8)
162#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
163#define FTGMAC100_MACCR_CRC_APD (1 << 10)
164#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
165#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
166#define FTGMAC100_MACCR_RX_ALL (1 << 14)
167#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
168#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
169#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
170#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
171#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
172#define FTGMAC100_MACCR_SW_RST (1 << 31)
173
174/*
175 * PHY control register
176 */
177#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f
178#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
179#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
180#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
181#define FTGMAC100_PHYCR_MIIRD (1 << 26)
182#define FTGMAC100_PHYCR_MIIWR (1 << 27)
183
184/*
185 * PHY data register
186 */
187#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
188#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff)
189
190/*
191 * Transmit descriptor, aligned to 16 bytes
192 */
193struct ftgmac100_txdes {
194 unsigned int txdes0;
195 unsigned int txdes1;
196 unsigned int txdes2; /* not used by HW */
197 unsigned int txdes3; /* TXBUF_BADR */
198} __attribute__ ((aligned(16)));
199
200#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
201#define FTGMAC100_TXDES0_EDOTR (1 << 15)
202#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
203#define FTGMAC100_TXDES0_LTS (1 << 28)
204#define FTGMAC100_TXDES0_FTS (1 << 29)
205#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
206
207#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
208#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
209#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
210#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
211#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
212#define FTGMAC100_TXDES1_LLC (1 << 22)
213#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
214#define FTGMAC100_TXDES1_TXIC (1 << 31)
215
216/*
217 * Receive descriptor, aligned to 16 bytes
218 */
219struct ftgmac100_rxdes {
220 unsigned int rxdes0;
221 unsigned int rxdes1;
222 unsigned int rxdes2; /* not used by HW */
223 unsigned int rxdes3; /* RXBUF_BADR */
224} __attribute__ ((aligned(16)));
225
226#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
227#define FTGMAC100_RXDES0_EDORR (1 << 15)
228#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
229#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
230#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
231#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
232#define FTGMAC100_RXDES0_FTL (1 << 20)
233#define FTGMAC100_RXDES0_RUNT (1 << 21)
234#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
235#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
236#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
237#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
238#define FTGMAC100_RXDES0_LRS (1 << 28)
239#define FTGMAC100_RXDES0_FRS (1 << 29)
240#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
241
242#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
243#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
244#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
245#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
246#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
247#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
248#define FTGMAC100_RXDES1_LLC (1 << 22)
249#define FTGMAC100_RXDES1_DF (1 << 23)
250#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
251#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
252#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
253#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
254
255#endif /* __FTGMAC100_H */