blob: a4aa05b3fa8a4846ff5a8d98e92dd1e0b2e214ef [file] [log] [blame]
TsiChungLiew4a442d32007-08-16 19:23:50 -05001/*
2 *
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wangc6d88632012-03-26 21:49:06 +00006 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiew4a442d32007-08-16 19:23:50 -05007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew4a442d32007-08-16 19:23:50 -050010 */
11
12#include <common.h>
13#include <asm/processor.h>
14
15#include <asm/immap.h>
Alison Wangc6d88632012-03-26 21:49:06 +000016#include <asm/io.h>
TsiChungLiew4a442d32007-08-16 19:23:50 -050017
18DECLARE_GLOBAL_DATA_PTR;
19/*
20 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
21 */
22int get_clocks(void)
23{
Alison Wangc6d88632012-03-26 21:49:06 +000024 pll_t *pll = (pll_t *)(MMAP_PLL);
TsiChungLiew4a442d32007-08-16 19:23:50 -050025
Alison Wangc6d88632012-03-26 21:49:06 +000026 out_be32(&pll->syncr, PLL_SYNCR_MFD(1));
TsiChungLiew4a442d32007-08-16 19:23:50 -050027
Alison Wangc6d88632012-03-26 21:49:06 +000028 while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
29 ;
Stefan Roese8280f6a2007-08-18 14:33:02 +020030
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031 gd->bus_clk = CONFIG_SYS_CLK;
TsiChungLiew4a442d32007-08-16 19:23:50 -050032 gd->cpu_clk = (gd->bus_clk * 2);
Stefan Roese8280f6a2007-08-18 14:33:02 +020033
Heiko Schocher00f792e2012-10-24 13:48:22 +020034#ifdef CONFIG_SYS_I2C_FSL
Simon Glass609e6ec2012-12-13 20:48:49 +000035 gd->arch.i2c1_clk = gd->bus_clk;
TsiChung Lieweec567a2008-08-19 03:01:19 +060036#endif
37
TsiChungLiew4a442d32007-08-16 19:23:50 -050038 return (0);
39}