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wdenk5c952cf2004-10-10 21:27:30 +00001/*
2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __NIOS2_H__
25#define __NIOS2_H__
26
27/*------------------------------------------------------------------------
28 * Control registers -- use with wrctl() & rdctl()
29 *----------------------------------------------------------------------*/
30#define CTL_STATUS 0 /* Processor status reg */
31#define CTL_ESTATUS 1 /* Exception status reg */
32#define CTL_BSTATUS 2 /* Break status reg */
33#define CTL_IENABLE 3 /* Interrut enable reg */
34#define CTL_IPENDING 4 /* Interrut pending reg */
35
36/*------------------------------------------------------------------------
37 * Access to control regs
38 *----------------------------------------------------------------------*/
39#define _str_(x) #x
40
41#define rdctl(reg)\
42 ({unsigned int val;\
43 asm volatile( "rdctl %0, ctl" _str_(reg)\
44 : "=r" (val) ); val;})
45
46#define wrctl(reg,val)\
47 asm volatile( "wrctl ctl" _str_(reg) ",%0"\
48 : : "r" (val))
49
50/*------------------------------------------------------------------------
51 * Control reg bit masks
52 *----------------------------------------------------------------------*/
53#define STATUS_IE (1<<0) /* Interrupt enable */
54#define STATUS_U (1<<1) /* User-mode */
55
56/*------------------------------------------------------------------------
57 * Bit-31 Cache bypass -- only valid for data access. When data cache
58 * is not implemented, bit 31 is ignored for compatibility.
59 *----------------------------------------------------------------------*/
60#define CACHE_BYPASS(a) ((a) | 0x80000000)
61#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000)
62
63#endif /* __NIOS2_H__ */