blob: 24c6f0d9869f6940f563398f361ab1aae9a85c0e [file] [log] [blame]
wdenkcd0a9de2004-02-23 20:48:38 +00001/*
2 * (C) Copyright 2004
3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
wdenkcd0a9de2004-02-23 20:48:38 +000024#include <common.h>
wdenk4d13cba2004-03-14 14:09:05 +000025#include <asm/processor.h>
wdenkcd0a9de2004-02-23 20:48:38 +000026#include <i2c.h>
27#include <miiphy.h>
Stefan Roesed6c61aa2005-08-16 18:18:00 +020028#include <ppc4xx_enet.h>
wdenkcd0a9de2004-02-23 20:48:38 +000029
30/*
31 * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
32 *
33 * CLKA output => Epson LCD Controller
34 * CLKB output => Not Connected
35 * CLKC output => Ethernet
36 * CLKD output => UART external clock
37 *
38 * Note: these values are obtained from device after init by micromonitor
39*/
40uchar pll_fs6377_regs[16] = {
41 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
42 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
43
44/*
45 * pll_init: Initialize AMIS IC FS6377-01 PLL
46 *
47 * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
48 *
49 */
50int pll_init(void)
51{
52 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
53
54 return i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
55 (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
56}
57
58/*
wdenk4d13cba2004-03-14 14:09:05 +000059 * board_early_init_f: do early board initialization
wdenkcd0a9de2004-02-23 20:48:38 +000060 *
61 */
wdenk4d13cba2004-03-14 14:09:05 +000062int board_early_init_f(void)
wdenkcd0a9de2004-02-23 20:48:38 +000063{
64 /* initialize PLL so UART, LCD, Ethernet clocked at correctly */
65 (void) get_clocks();
66 pll_init();
67
68 /*-------------------------------------------------------------------------+
69 | Interrupt controller setup for the Walnut board.
70 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
71 | IRQ 16 405GP internally generated; active low; level sensitive
72 | IRQ 17-24 RESERVED
73 | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
74 | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
75 | IRQ 27 (EXT IRQ 2) Not Used
76 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
77 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
78 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
79 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
80 | Note for Walnut board:
81 | An interrupt taken for the FPGA (IRQ 25) indicates that either
82 | the Mouse, Keyboard, IRDA, or External Expansion caused the
83 | interrupt. The FPGA must be read to determine which device
84 | caused the interrupt. The default setting of the FPGA clears
85 |
86 +-------------------------------------------------------------------------*/
87
88 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
89 mtdcr (uicer, 0x00000000); /* disable all ints */
90 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
91 mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
92 mtdcr (uictr, 0x10000000); /* set int trigger levels */
93 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
94 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
95
96 mtebc (epcr, 0xa8400000); /* EBC always driven */
97
98 return 0; /* success */
99}
100
101/*
102 * checkboard: identify/verify the board we are running
103 *
104 * Remark: we just assume it is correct board here!
105 *
106 */
107int checkboard(void)
108{
109 printf("BOARD: Cogent CSB272\n");
110
111 return 0; /* success */
112}
113
114/*
115 * initram: Determine the size of mounted DRAM
116 *
117 * Size is determined by reading SDRAM configuration registers as
118 * configured by initialization code
119 *
120 */
121long initdram (int board_type)
122{
123 ulong tot_size;
124 ulong bank_size;
125 ulong tmp;
126
127 tot_size = 0;
128
129 mtdcr (memcfga, mem_mb0cf);
130 tmp = mfdcr (memcfgd);
131 if (tmp & 0x00000001) {
132 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
133 tot_size += bank_size;
134 }
135
136 mtdcr (memcfga, mem_mb1cf);
137 tmp = mfdcr (memcfgd);
138 if (tmp & 0x00000001) {
139 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
140 tot_size += bank_size;
141 }
142
143 mtdcr (memcfga, mem_mb2cf);
144 tmp = mfdcr (memcfgd);
145 if (tmp & 0x00000001) {
146 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
147 tot_size += bank_size;
148 }
149
150 mtdcr (memcfga, mem_mb3cf);
151 tmp = mfdcr (memcfgd);
152 if (tmp & 0x00000001) {
153 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
154 tot_size += bank_size;
155 }
156
157 return tot_size;
158}
159
160/*
161 * last_stage_init: final configurations (such as PHY etc)
162 *
163 */
164int last_stage_init(void)
165{
166 /* initialize the PHY */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200167 miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
168
169 /* AUTO neg */
170 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
171 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
172
173 /* LEDs */
174 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
175
wdenkcd0a9de2004-02-23 20:48:38 +0000176
177 return 0; /* success */
178}