blob: 13fad8119bb5d133867360b6143d472cafbfe228 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Thomas Chouf6569882010-04-15 22:32:38 +08002/*
3 * Opencore 10/100 ethernet mac driver
4 *
5 * Copyright (C) 2007-2008 Avionic Design Development GmbH
6 * Copyright (C) 2008-2009 Avionic Design GmbH
7 * Thierry Reding <thierry.reding@avionic-design.de>
8 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
Max Filippov5d43fea2016-08-05 18:26:17 +03009 * Copyright (C) 2016 Cadence Design Systems Inc.
Thomas Chouf6569882010-04-15 22:32:38 +080010 */
11
12#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070013#include <cpu_func.h>
Simon Glass9d922452017-05-17 17:18:03 -060014#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060015#include <log.h>
Max Filippov5d43fea2016-08-05 18:26:17 +030016#include <dm/platform_data/net_ethoc.h>
Max Filippova84a7572016-08-05 18:26:16 +030017#include <linux/io.h>
Thomas Chouf6569882010-04-15 22:32:38 +080018#include <malloc.h>
19#include <net.h>
20#include <miiphy.h>
Thomas Chouf6569882010-04-15 22:32:38 +080021#include <asm/cache.h>
Max Filippov0d0779c2016-08-05 18:26:21 +030022#include <wait_bit.h>
Thomas Chouf6569882010-04-15 22:32:38 +080023
24/* register offsets */
25#define MODER 0x00
26#define INT_SOURCE 0x04
27#define INT_MASK 0x08
28#define IPGT 0x0c
29#define IPGR1 0x10
30#define IPGR2 0x14
31#define PACKETLEN 0x18
32#define COLLCONF 0x1c
33#define TX_BD_NUM 0x20
34#define CTRLMODER 0x24
35#define MIIMODER 0x28
36#define MIICOMMAND 0x2c
37#define MIIADDRESS 0x30
38#define MIITX_DATA 0x34
39#define MIIRX_DATA 0x38
40#define MIISTATUS 0x3c
41#define MAC_ADDR0 0x40
42#define MAC_ADDR1 0x44
43#define ETH_HASH0 0x48
44#define ETH_HASH1 0x4c
45#define ETH_TXCTRL 0x50
46
47/* mode register */
48#define MODER_RXEN (1 << 0) /* receive enable */
49#define MODER_TXEN (1 << 1) /* transmit enable */
50#define MODER_NOPRE (1 << 2) /* no preamble */
51#define MODER_BRO (1 << 3) /* broadcast address */
52#define MODER_IAM (1 << 4) /* individual address mode */
53#define MODER_PRO (1 << 5) /* promiscuous mode */
54#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
55#define MODER_LOOP (1 << 7) /* loopback */
56#define MODER_NBO (1 << 8) /* no back-off */
57#define MODER_EDE (1 << 9) /* excess defer enable */
58#define MODER_FULLD (1 << 10) /* full duplex */
59#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
60#define MODER_DCRC (1 << 12) /* delayed CRC enable */
61#define MODER_CRC (1 << 13) /* CRC enable */
62#define MODER_HUGE (1 << 14) /* huge packets enable */
63#define MODER_PAD (1 << 15) /* padding enabled */
64#define MODER_RSM (1 << 16) /* receive small packets */
65
66/* interrupt source and mask registers */
67#define INT_MASK_TXF (1 << 0) /* transmit frame */
68#define INT_MASK_TXE (1 << 1) /* transmit error */
69#define INT_MASK_RXF (1 << 2) /* receive frame */
70#define INT_MASK_RXE (1 << 3) /* receive error */
71#define INT_MASK_BUSY (1 << 4)
72#define INT_MASK_TXC (1 << 5) /* transmit control frame */
73#define INT_MASK_RXC (1 << 6) /* receive control frame */
74
75#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
76#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
77
78#define INT_MASK_ALL ( \
79 INT_MASK_TXF | INT_MASK_TXE | \
80 INT_MASK_RXF | INT_MASK_RXE | \
81 INT_MASK_TXC | INT_MASK_RXC | \
82 INT_MASK_BUSY \
83 )
84
85/* packet length register */
86#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
87#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
88#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
89 PACKETLEN_MAX(max))
90
91/* transmit buffer number register */
92#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
93
94/* control module mode register */
95#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
96#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
97#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
98
99/* MII mode register */
100#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
101#define MIIMODER_NOPRE (1 << 8) /* no preamble */
102
103/* MII command register */
104#define MIICOMMAND_SCAN (1 << 0) /* scan status */
105#define MIICOMMAND_READ (1 << 1) /* read status */
106#define MIICOMMAND_WRITE (1 << 2) /* write control data */
107
108/* MII address register */
109#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
110#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
111#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
112 MIIADDRESS_RGAD(reg))
113
114/* MII transmit data register */
115#define MIITX_DATA_VAL(x) ((x) & 0xffff)
116
117/* MII receive data register */
118#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
119
120/* MII status register */
121#define MIISTATUS_LINKFAIL (1 << 0)
122#define MIISTATUS_BUSY (1 << 1)
123#define MIISTATUS_INVALID (1 << 2)
124
125/* TX buffer descriptor */
126#define TX_BD_CS (1 << 0) /* carrier sense lost */
127#define TX_BD_DF (1 << 1) /* defer indication */
128#define TX_BD_LC (1 << 2) /* late collision */
129#define TX_BD_RL (1 << 3) /* retransmission limit */
130#define TX_BD_RETRY_MASK (0x00f0)
131#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
132#define TX_BD_UR (1 << 8) /* transmitter underrun */
133#define TX_BD_CRC (1 << 11) /* TX CRC enable */
134#define TX_BD_PAD (1 << 12) /* pad enable */
135#define TX_BD_WRAP (1 << 13)
136#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
137#define TX_BD_READY (1 << 15) /* TX buffer ready */
138#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
139#define TX_BD_LEN_MASK (0xffff << 16)
140
141#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
142 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
143
144/* RX buffer descriptor */
145#define RX_BD_LC (1 << 0) /* late collision */
146#define RX_BD_CRC (1 << 1) /* RX CRC error */
147#define RX_BD_SF (1 << 2) /* short frame */
148#define RX_BD_TL (1 << 3) /* too long */
149#define RX_BD_DN (1 << 4) /* dribble nibble */
150#define RX_BD_IS (1 << 5) /* invalid symbol */
151#define RX_BD_OR (1 << 6) /* receiver overrun */
152#define RX_BD_MISS (1 << 7)
153#define RX_BD_CF (1 << 8) /* control frame */
154#define RX_BD_WRAP (1 << 13)
155#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
156#define RX_BD_EMPTY (1 << 15)
157#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
158
159#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
160 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
161
162#define ETHOC_BUFSIZ 1536
163#define ETHOC_ZLEN 64
164#define ETHOC_BD_BASE 0x400
165#define ETHOC_TIMEOUT (HZ / 2)
166#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
Max Filippova84a7572016-08-05 18:26:16 +0300167#define ETHOC_IOSIZE 0x54
Thomas Chouf6569882010-04-15 22:32:38 +0800168
169/**
170 * struct ethoc - driver-private device structure
171 * @num_tx: number of send buffers
172 * @cur_tx: last send buffer written
173 * @dty_tx: last buffer actually sent
174 * @num_rx: number of receive buffers
175 * @cur_rx: current receive buffer
176 */
177struct ethoc {
178 u32 num_tx;
179 u32 cur_tx;
180 u32 dty_tx;
181 u32 num_rx;
182 u32 cur_rx;
Max Filippova84a7572016-08-05 18:26:16 +0300183 void __iomem *iobase;
Max Filippov59b7dfa2016-08-05 18:26:20 +0300184 void __iomem *packet;
185 phys_addr_t packet_phys;
Max Filippov0d0779c2016-08-05 18:26:21 +0300186
187#ifdef CONFIG_PHYLIB
188 struct mii_dev *bus;
189 struct phy_device *phydev;
190#endif
Thomas Chouf6569882010-04-15 22:32:38 +0800191};
192
193/**
194 * struct ethoc_bd - buffer descriptor
195 * @stat: buffer statistics
196 * @addr: physical memory address
197 */
198struct ethoc_bd {
199 u32 stat;
200 u32 addr;
201};
202
Max Filippov0d0779c2016-08-05 18:26:21 +0300203static inline u32 *ethoc_reg(struct ethoc *priv, size_t offset)
204{
205 return priv->iobase + offset;
206}
207
Max Filippova84a7572016-08-05 18:26:16 +0300208static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
Thomas Chouf6569882010-04-15 22:32:38 +0800209{
Max Filippov0d0779c2016-08-05 18:26:21 +0300210 return readl(ethoc_reg(priv, offset));
Thomas Chouf6569882010-04-15 22:32:38 +0800211}
212
Max Filippova84a7572016-08-05 18:26:16 +0300213static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
Thomas Chouf6569882010-04-15 22:32:38 +0800214{
Max Filippov0d0779c2016-08-05 18:26:21 +0300215 writel(data, ethoc_reg(priv, offset));
Thomas Chouf6569882010-04-15 22:32:38 +0800216}
217
Max Filippova84a7572016-08-05 18:26:16 +0300218static inline void ethoc_read_bd(struct ethoc *priv, int index,
Thomas Chouf6569882010-04-15 22:32:38 +0800219 struct ethoc_bd *bd)
220{
Vasili Galka9f680d22014-08-26 13:46:17 +0300221 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
Max Filippova84a7572016-08-05 18:26:16 +0300222 bd->stat = ethoc_read(priv, offset + 0);
223 bd->addr = ethoc_read(priv, offset + 4);
Thomas Chouf6569882010-04-15 22:32:38 +0800224}
225
Max Filippova84a7572016-08-05 18:26:16 +0300226static inline void ethoc_write_bd(struct ethoc *priv, int index,
Thomas Chouf6569882010-04-15 22:32:38 +0800227 const struct ethoc_bd *bd)
228{
Vasili Galka9f680d22014-08-26 13:46:17 +0300229 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
Max Filippova84a7572016-08-05 18:26:16 +0300230 ethoc_write(priv, offset + 0, bd->stat);
231 ethoc_write(priv, offset + 4, bd->addr);
Thomas Chouf6569882010-04-15 22:32:38 +0800232}
233
Max Filippov5d43fea2016-08-05 18:26:17 +0300234static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac)
Thomas Chouf6569882010-04-15 22:32:38 +0800235{
Max Filippova84a7572016-08-05 18:26:16 +0300236 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
Thomas Chouf6569882010-04-15 22:32:38 +0800237 (mac[4] << 8) | (mac[5] << 0));
Max Filippova84a7572016-08-05 18:26:16 +0300238 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
Thomas Chou3ac9d6c2010-04-27 20:20:27 +0800239 return 0;
Thomas Chouf6569882010-04-15 22:32:38 +0800240}
241
Max Filippova84a7572016-08-05 18:26:16 +0300242static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
Thomas Chouf6569882010-04-15 22:32:38 +0800243{
Max Filippova84a7572016-08-05 18:26:16 +0300244 ethoc_write(priv, INT_SOURCE, mask);
Thomas Chouf6569882010-04-15 22:32:38 +0800245}
246
Max Filippova84a7572016-08-05 18:26:16 +0300247static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
Thomas Chouf6569882010-04-15 22:32:38 +0800248{
Max Filippova84a7572016-08-05 18:26:16 +0300249 u32 mode = ethoc_read(priv, MODER);
Thomas Chouf6569882010-04-15 22:32:38 +0800250 mode |= MODER_RXEN | MODER_TXEN;
Max Filippova84a7572016-08-05 18:26:16 +0300251 ethoc_write(priv, MODER, mode);
Thomas Chouf6569882010-04-15 22:32:38 +0800252}
253
Max Filippova84a7572016-08-05 18:26:16 +0300254static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
Thomas Chouf6569882010-04-15 22:32:38 +0800255{
Max Filippova84a7572016-08-05 18:26:16 +0300256 u32 mode = ethoc_read(priv, MODER);
Thomas Chouf6569882010-04-15 22:32:38 +0800257 mode &= ~(MODER_RXEN | MODER_TXEN);
Max Filippova84a7572016-08-05 18:26:16 +0300258 ethoc_write(priv, MODER, mode);
Thomas Chouf6569882010-04-15 22:32:38 +0800259}
260
Max Filippova84a7572016-08-05 18:26:16 +0300261static int ethoc_init_ring(struct ethoc *priv)
Thomas Chouf6569882010-04-15 22:32:38 +0800262{
Thomas Chouf6569882010-04-15 22:32:38 +0800263 struct ethoc_bd bd;
Max Filippov59b7dfa2016-08-05 18:26:20 +0300264 phys_addr_t addr = priv->packet_phys;
Thomas Chouf6569882010-04-15 22:32:38 +0800265 int i;
266
267 priv->cur_tx = 0;
268 priv->dty_tx = 0;
269 priv->cur_rx = 0;
270
271 /* setup transmission buffers */
272 bd.stat = TX_BD_IRQ | TX_BD_CRC;
Max Filippov02a888b2016-08-05 18:26:19 +0300273 bd.addr = 0;
Thomas Chouf6569882010-04-15 22:32:38 +0800274
275 for (i = 0; i < priv->num_tx; i++) {
Max Filippov59b7dfa2016-08-05 18:26:20 +0300276 if (addr) {
277 bd.addr = addr;
278 addr += PKTSIZE_ALIGN;
279 }
Thomas Chouf6569882010-04-15 22:32:38 +0800280 if (i == priv->num_tx - 1)
281 bd.stat |= TX_BD_WRAP;
282
Max Filippova84a7572016-08-05 18:26:16 +0300283 ethoc_write_bd(priv, i, &bd);
Thomas Chouf6569882010-04-15 22:32:38 +0800284 }
285
286 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
287
288 for (i = 0; i < priv->num_rx; i++) {
Max Filippov59b7dfa2016-08-05 18:26:20 +0300289 if (addr) {
290 bd.addr = addr;
291 addr += PKTSIZE_ALIGN;
292 } else {
293 bd.addr = virt_to_phys(net_rx_packets[i]);
294 }
Thomas Chouf6569882010-04-15 22:32:38 +0800295 if (i == priv->num_rx - 1)
296 bd.stat |= RX_BD_WRAP;
297
Max Filippov02a888b2016-08-05 18:26:19 +0300298 flush_dcache_range((ulong)net_rx_packets[i],
299 (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
Max Filippova84a7572016-08-05 18:26:16 +0300300 ethoc_write_bd(priv, priv->num_tx + i, &bd);
Thomas Chouf6569882010-04-15 22:32:38 +0800301 }
302
303 return 0;
304}
305
Max Filippova84a7572016-08-05 18:26:16 +0300306static int ethoc_reset(struct ethoc *priv)
Thomas Chouf6569882010-04-15 22:32:38 +0800307{
308 u32 mode;
309
310 /* TODO: reset controller? */
311
Max Filippova84a7572016-08-05 18:26:16 +0300312 ethoc_disable_rx_and_tx(priv);
Thomas Chouf6569882010-04-15 22:32:38 +0800313
314 /* TODO: setup registers */
315
316 /* enable FCS generation and automatic padding */
Max Filippova84a7572016-08-05 18:26:16 +0300317 mode = ethoc_read(priv, MODER);
Thomas Chouf6569882010-04-15 22:32:38 +0800318 mode |= MODER_CRC | MODER_PAD;
Max Filippova84a7572016-08-05 18:26:16 +0300319 ethoc_write(priv, MODER, mode);
Thomas Chouf6569882010-04-15 22:32:38 +0800320
321 /* set full-duplex mode */
Max Filippova84a7572016-08-05 18:26:16 +0300322 mode = ethoc_read(priv, MODER);
Thomas Chouf6569882010-04-15 22:32:38 +0800323 mode |= MODER_FULLD;
Max Filippova84a7572016-08-05 18:26:16 +0300324 ethoc_write(priv, MODER, mode);
325 ethoc_write(priv, IPGT, 0x15);
Thomas Chouf6569882010-04-15 22:32:38 +0800326
Max Filippova84a7572016-08-05 18:26:16 +0300327 ethoc_ack_irq(priv, INT_MASK_ALL);
328 ethoc_enable_rx_and_tx(priv);
Thomas Chouf6569882010-04-15 22:32:38 +0800329 return 0;
330}
331
Max Filippov5d43fea2016-08-05 18:26:17 +0300332static int ethoc_init_common(struct ethoc *priv)
Thomas Chouf6569882010-04-15 22:32:38 +0800333{
Max Filippov0d0779c2016-08-05 18:26:21 +0300334 int ret = 0;
335
Thomas Chouf6569882010-04-15 22:32:38 +0800336 priv->num_tx = 1;
337 priv->num_rx = PKTBUFSRX;
Max Filippova84a7572016-08-05 18:26:16 +0300338 ethoc_write(priv, TX_BD_NUM, priv->num_tx);
339 ethoc_init_ring(priv);
340 ethoc_reset(priv);
Thomas Chouf6569882010-04-15 22:32:38 +0800341
Max Filippov0d0779c2016-08-05 18:26:21 +0300342#ifdef CONFIG_PHYLIB
343 ret = phy_startup(priv->phydev);
344 if (ret) {
345 printf("Could not initialize PHY %s\n",
346 priv->phydev->dev->name);
347 return ret;
348 }
349#endif
350 return ret;
351}
352
353static void ethoc_stop_common(struct ethoc *priv)
354{
355 ethoc_disable_rx_and_tx(priv);
356#ifdef CONFIG_PHYLIB
357 phy_shutdown(priv->phydev);
358#endif
Thomas Chouf6569882010-04-15 22:32:38 +0800359}
360
361static int ethoc_update_rx_stats(struct ethoc_bd *bd)
362{
363 int ret = 0;
364
365 if (bd->stat & RX_BD_TL) {
366 debug("ETHOC: " "RX: frame too long\n");
367 ret++;
368 }
369
370 if (bd->stat & RX_BD_SF) {
371 debug("ETHOC: " "RX: frame too short\n");
372 ret++;
373 }
374
375 if (bd->stat & RX_BD_DN)
376 debug("ETHOC: " "RX: dribble nibble\n");
377
378 if (bd->stat & RX_BD_CRC) {
379 debug("ETHOC: " "RX: wrong CRC\n");
380 ret++;
381 }
382
383 if (bd->stat & RX_BD_OR) {
384 debug("ETHOC: " "RX: overrun\n");
385 ret++;
386 }
387
388 if (bd->stat & RX_BD_LC) {
389 debug("ETHOC: " "RX: late collision\n");
390 ret++;
391 }
392
393 return ret;
394}
395
Max Filippov5d43fea2016-08-05 18:26:17 +0300396static int ethoc_rx_common(struct ethoc *priv, uchar **packetp)
Thomas Chouf6569882010-04-15 22:32:38 +0800397{
Max Filippov5d43fea2016-08-05 18:26:17 +0300398 struct ethoc_bd bd;
Max Filippov02a888b2016-08-05 18:26:19 +0300399 u32 i = priv->cur_rx % priv->num_rx;
400 u32 entry = priv->num_tx + i;
Thomas Chouf6569882010-04-15 22:32:38 +0800401
Max Filippov5d43fea2016-08-05 18:26:17 +0300402 ethoc_read_bd(priv, entry, &bd);
403 if (bd.stat & RX_BD_EMPTY)
404 return -EAGAIN;
Thomas Chouf6569882010-04-15 22:32:38 +0800405
Max Filippov5d43fea2016-08-05 18:26:17 +0300406 debug("%s(): RX buffer %d, %x received\n",
407 __func__, priv->cur_rx, bd.stat);
408 if (ethoc_update_rx_stats(&bd) == 0) {
409 int size = bd.stat >> 16;
Thomas Chouf6569882010-04-15 22:32:38 +0800410
Max Filippov5d43fea2016-08-05 18:26:17 +0300411 size -= 4; /* strip the CRC */
Max Filippov59b7dfa2016-08-05 18:26:20 +0300412 if (priv->packet)
413 *packetp = priv->packet + entry * PKTSIZE_ALIGN;
414 else
415 *packetp = net_rx_packets[i];
Max Filippov5d43fea2016-08-05 18:26:17 +0300416 return size;
417 } else {
418 return 0;
419 }
420}
Thomas Chouf6569882010-04-15 22:32:38 +0800421
Max Filippov5d43fea2016-08-05 18:26:17 +0300422static int ethoc_is_new_packet_received(struct ethoc *priv)
423{
424 u32 pending;
425
426 pending = ethoc_read(priv, INT_SOURCE);
427 ethoc_ack_irq(priv, pending);
428 if (pending & INT_MASK_BUSY)
429 debug("%s(): packet dropped\n", __func__);
430 if (pending & INT_MASK_RX) {
431 debug("%s(): rx irq\n", __func__);
432 return 1;
Thomas Chouf6569882010-04-15 22:32:38 +0800433 }
434
Max Filippov5d43fea2016-08-05 18:26:17 +0300435 return 0;
Thomas Chouf6569882010-04-15 22:32:38 +0800436}
437
438static int ethoc_update_tx_stats(struct ethoc_bd *bd)
439{
440 if (bd->stat & TX_BD_LC)
441 debug("ETHOC: " "TX: late collision\n");
442
443 if (bd->stat & TX_BD_RL)
444 debug("ETHOC: " "TX: retransmit limit\n");
445
446 if (bd->stat & TX_BD_UR)
447 debug("ETHOC: " "TX: underrun\n");
448
449 if (bd->stat & TX_BD_CS)
450 debug("ETHOC: " "TX: carrier sense lost\n");
451
452 return 0;
453}
454
Max Filippova84a7572016-08-05 18:26:16 +0300455static void ethoc_tx(struct ethoc *priv)
Thomas Chouf6569882010-04-15 22:32:38 +0800456{
Thomas Chouf6569882010-04-15 22:32:38 +0800457 u32 entry = priv->dty_tx % priv->num_tx;
458 struct ethoc_bd bd;
459
Max Filippova84a7572016-08-05 18:26:16 +0300460 ethoc_read_bd(priv, entry, &bd);
Thomas Chouf6569882010-04-15 22:32:38 +0800461 if ((bd.stat & TX_BD_READY) == 0)
462 (void)ethoc_update_tx_stats(&bd);
463}
464
Max Filippov5d43fea2016-08-05 18:26:17 +0300465static int ethoc_send_common(struct ethoc *priv, void *packet, int length)
Thomas Chouf6569882010-04-15 22:32:38 +0800466{
Thomas Chouf6569882010-04-15 22:32:38 +0800467 struct ethoc_bd bd;
468 u32 entry;
469 u32 pending;
470 int tmo;
471
472 entry = priv->cur_tx % priv->num_tx;
Max Filippova84a7572016-08-05 18:26:16 +0300473 ethoc_read_bd(priv, entry, &bd);
Thomas Chouf6569882010-04-15 22:32:38 +0800474 if (unlikely(length < ETHOC_ZLEN))
475 bd.stat |= TX_BD_PAD;
476 else
477 bd.stat &= ~TX_BD_PAD;
Thomas Chouf6569882010-04-15 22:32:38 +0800478
Max Filippov59b7dfa2016-08-05 18:26:20 +0300479 if (priv->packet) {
480 void *p = priv->packet + entry * PKTSIZE_ALIGN;
481
482 memcpy(p, packet, length);
483 packet = p;
484 } else {
485 bd.addr = virt_to_phys(packet);
486 }
Max Filippov02a888b2016-08-05 18:26:19 +0300487 flush_dcache_range((ulong)packet, (ulong)packet + length);
Thomas Chouf6569882010-04-15 22:32:38 +0800488 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
489 bd.stat |= TX_BD_LEN(length);
Max Filippova84a7572016-08-05 18:26:16 +0300490 ethoc_write_bd(priv, entry, &bd);
Thomas Chouf6569882010-04-15 22:32:38 +0800491
492 /* start transmit */
493 bd.stat |= TX_BD_READY;
Max Filippova84a7572016-08-05 18:26:16 +0300494 ethoc_write_bd(priv, entry, &bd);
Thomas Chouf6569882010-04-15 22:32:38 +0800495
496 /* wait for transfer to succeed */
497 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
498 while (1) {
Max Filippova84a7572016-08-05 18:26:16 +0300499 pending = ethoc_read(priv, INT_SOURCE);
500 ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
Thomas Chouf6569882010-04-15 22:32:38 +0800501 if (pending & INT_MASK_BUSY)
502 debug("%s(): packet dropped\n", __func__);
503
504 if (pending & INT_MASK_TX) {
Max Filippova84a7572016-08-05 18:26:16 +0300505 ethoc_tx(priv);
Thomas Chouf6569882010-04-15 22:32:38 +0800506 break;
507 }
508 if (get_timer(0) >= tmo) {
509 debug("%s(): timed out\n", __func__);
510 return -1;
511 }
512 }
513
514 debug("%s(): packet sent\n", __func__);
515 return 0;
516}
517
Max Filippov5d43fea2016-08-05 18:26:17 +0300518static int ethoc_free_pkt_common(struct ethoc *priv)
519{
Max Filippov5d43fea2016-08-05 18:26:17 +0300520 struct ethoc_bd bd;
Max Filippov02a888b2016-08-05 18:26:19 +0300521 u32 i = priv->cur_rx % priv->num_rx;
522 u32 entry = priv->num_tx + i;
Max Filippov59b7dfa2016-08-05 18:26:20 +0300523 void *src;
Max Filippov5d43fea2016-08-05 18:26:17 +0300524
Max Filippov5d43fea2016-08-05 18:26:17 +0300525 ethoc_read_bd(priv, entry, &bd);
526
Max Filippov59b7dfa2016-08-05 18:26:20 +0300527 if (priv->packet)
528 src = priv->packet + entry * PKTSIZE_ALIGN;
529 else
530 src = net_rx_packets[i];
Max Filippov5d43fea2016-08-05 18:26:17 +0300531 /* clear the buffer descriptor so it can be reused */
Max Filippov59b7dfa2016-08-05 18:26:20 +0300532 flush_dcache_range((ulong)src,
533 (ulong)src + PKTSIZE_ALIGN);
Max Filippov5d43fea2016-08-05 18:26:17 +0300534 bd.stat &= ~RX_BD_STATS;
535 bd.stat |= RX_BD_EMPTY;
536 ethoc_write_bd(priv, entry, &bd);
537 priv->cur_rx++;
538
539 return 0;
540}
541
Max Filippov0d0779c2016-08-05 18:26:21 +0300542#ifdef CONFIG_PHYLIB
543
544static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
545{
546 struct ethoc *priv = bus->priv;
547 int rc;
548
549 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
550 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
551
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100552 rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
553 MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
Max Filippov0d0779c2016-08-05 18:26:21 +0300554
555 if (rc == 0) {
556 u32 data = ethoc_read(priv, MIIRX_DATA);
557
558 /* reset MII command register */
559 ethoc_write(priv, MIICOMMAND, 0);
560 return data;
561 }
562 return rc;
563}
564
565static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
566 u16 val)
567{
568 struct ethoc *priv = bus->priv;
569 int rc;
570
571 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
572 ethoc_write(priv, MIITX_DATA, val);
573 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
574
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100575 rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
576 MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
Max Filippov0d0779c2016-08-05 18:26:21 +0300577
578 if (rc == 0) {
579 /* reset MII command register */
580 ethoc_write(priv, MIICOMMAND, 0);
581 }
582 return rc;
583}
584
585static int ethoc_mdio_init(const char *name, struct ethoc *priv)
586{
587 struct mii_dev *bus = mdio_alloc();
588 int ret;
589
590 if (!bus) {
591 printf("Failed to allocate MDIO bus\n");
592 return -ENOMEM;
593 }
594
595 bus->read = ethoc_mdio_read;
596 bus->write = ethoc_mdio_write;
597 snprintf(bus->name, sizeof(bus->name), "%s", name);
598 bus->priv = priv;
599
600 ret = mdio_register(bus);
601 if (ret < 0)
602 return ret;
603
604 priv->bus = miiphy_get_dev_by_name(name);
605 return 0;
606}
607
608static int ethoc_phy_init(struct ethoc *priv, void *dev)
609{
610 struct phy_device *phydev;
Marek Vasut8869a882023-05-31 00:51:21 +0200611 int mask = -1;
Max Filippov0d0779c2016-08-05 18:26:21 +0300612
613#ifdef CONFIG_PHY_ADDR
Marek Vasut8869a882023-05-31 00:51:21 +0200614 mask = CONFIG_PHY_ADDR;
Max Filippov0d0779c2016-08-05 18:26:21 +0300615#endif
616
Marek Vasut8869a882023-05-31 00:51:21 +0200617 phydev = phy_connect(priv->bus, mask, dev, PHY_INTERFACE_MODE_MII);
Max Filippov0d0779c2016-08-05 18:26:21 +0300618 if (!phydev)
619 return -ENODEV;
620
Max Filippov0d0779c2016-08-05 18:26:21 +0300621 phydev->supported &= PHY_BASIC_FEATURES;
622 phydev->advertising = phydev->supported;
623
624 priv->phydev = phydev;
625 phy_config(phydev);
626
627 return 0;
628}
629
630#else
631
632static inline int ethoc_mdio_init(const char *name, struct ethoc *priv)
633{
634 return 0;
635}
636
637static inline int ethoc_phy_init(struct ethoc *priv, void *dev)
638{
639 return 0;
640}
641
642#endif
643
Max Filippov5d43fea2016-08-05 18:26:17 +0300644static int ethoc_write_hwaddr(struct udevice *dev)
645{
Simon Glassc69cda22020-12-03 16:55:20 -0700646 struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
Max Filippov5d43fea2016-08-05 18:26:17 +0300647 struct ethoc *priv = dev_get_priv(dev);
648 u8 *mac = pdata->eth_pdata.enetaddr;
649
650 return ethoc_write_hwaddr_common(priv, mac);
651}
652
653static int ethoc_send(struct udevice *dev, void *packet, int length)
654{
655 return ethoc_send_common(dev_get_priv(dev), packet, length);
656}
657
658static int ethoc_free_pkt(struct udevice *dev, uchar *packet, int length)
659{
660 return ethoc_free_pkt_common(dev_get_priv(dev));
661}
662
663static int ethoc_recv(struct udevice *dev, int flags, uchar **packetp)
664{
665 struct ethoc *priv = dev_get_priv(dev);
666
667 if (flags & ETH_RECV_CHECK_DEVICE)
668 if (!ethoc_is_new_packet_received(priv))
669 return -EAGAIN;
670
671 return ethoc_rx_common(priv, packetp);
672}
673
674static int ethoc_start(struct udevice *dev)
675{
676 return ethoc_init_common(dev_get_priv(dev));
677}
678
679static void ethoc_stop(struct udevice *dev)
680{
Max Filippov0d0779c2016-08-05 18:26:21 +0300681 ethoc_stop_common(dev_get_priv(dev));
Max Filippov5d43fea2016-08-05 18:26:17 +0300682}
683
Simon Glassd1998a92020-12-03 16:55:21 -0700684static int ethoc_of_to_plat(struct udevice *dev)
Max Filippov2de18c82016-08-05 18:26:18 +0300685{
Simon Glassc69cda22020-12-03 16:55:20 -0700686 struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
Max Filippov59b7dfa2016-08-05 18:26:20 +0300687 fdt_addr_t addr;
Max Filippov2de18c82016-08-05 18:26:18 +0300688
Masahiro Yamada25484932020-07-17 14:36:48 +0900689 pdata->eth_pdata.iobase = dev_read_addr(dev);
Simon Glassa821c4a2017-05-17 17:18:05 -0600690 addr = devfdt_get_addr_index(dev, 1);
Max Filippov59b7dfa2016-08-05 18:26:20 +0300691 if (addr != FDT_ADDR_T_NONE)
692 pdata->packet_base = addr;
Max Filippov2de18c82016-08-05 18:26:18 +0300693 return 0;
694}
695
Max Filippov5d43fea2016-08-05 18:26:17 +0300696static int ethoc_probe(struct udevice *dev)
697{
Simon Glassc69cda22020-12-03 16:55:20 -0700698 struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
Max Filippov5d43fea2016-08-05 18:26:17 +0300699 struct ethoc *priv = dev_get_priv(dev);
700
701 priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
Max Filippov59b7dfa2016-08-05 18:26:20 +0300702 if (pdata->packet_base) {
703 priv->packet_phys = pdata->packet_base;
704 priv->packet = ioremap(pdata->packet_base,
705 (1 + PKTBUFSRX) * PKTSIZE_ALIGN);
706 }
Max Filippov0d0779c2016-08-05 18:26:21 +0300707
708 ethoc_mdio_init(dev->name, priv);
709 ethoc_phy_init(priv, dev);
710
Max Filippov5d43fea2016-08-05 18:26:17 +0300711 return 0;
712}
713
714static int ethoc_remove(struct udevice *dev)
715{
716 struct ethoc *priv = dev_get_priv(dev);
717
Max Filippov0d0779c2016-08-05 18:26:21 +0300718#ifdef CONFIG_PHYLIB
719 free(priv->phydev);
720 mdio_unregister(priv->bus);
721 mdio_free(priv->bus);
722#endif
Max Filippov5d43fea2016-08-05 18:26:17 +0300723 iounmap(priv->iobase);
724 return 0;
725}
726
727static const struct eth_ops ethoc_ops = {
728 .start = ethoc_start,
729 .stop = ethoc_stop,
730 .send = ethoc_send,
731 .recv = ethoc_recv,
732 .free_pkt = ethoc_free_pkt,
733 .write_hwaddr = ethoc_write_hwaddr,
734};
735
Max Filippov2de18c82016-08-05 18:26:18 +0300736static const struct udevice_id ethoc_ids[] = {
737 { .compatible = "opencores,ethoc" },
738 { }
739};
740
Max Filippov5d43fea2016-08-05 18:26:17 +0300741U_BOOT_DRIVER(ethoc) = {
742 .name = "ethoc",
743 .id = UCLASS_ETH,
Max Filippov2de18c82016-08-05 18:26:18 +0300744 .of_match = ethoc_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700745 .of_to_plat = ethoc_of_to_plat,
Max Filippov5d43fea2016-08-05 18:26:17 +0300746 .probe = ethoc_probe,
747 .remove = ethoc_remove,
748 .ops = &ethoc_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700749 .priv_auto = sizeof(struct ethoc),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700750 .plat_auto = sizeof(struct ethoc_eth_pdata),
Max Filippov5d43fea2016-08-05 18:26:17 +0300751};