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Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04001/*
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +00002 * Common configuration settings for IGEP technology based boards
3 *
4 * (C) Copyright 2012
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04005 * ISEE 2007 SL, <www.iseebcn.com>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04008 */
9
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +000010#ifndef __IGEP00X0_H
11#define __IGEP00X0_H
12
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +010013#ifdef CONFIG_BOOT_NAND
14#define CONFIG_NAND
15#endif
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040016
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +010017#define CONFIG_NR_DRAM_BANKS 2
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040018
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +010019#include <configs/ti_omap3_common.h>
Enric Balletbo i Serraaa127df2013-02-07 00:40:05 +000020#include <asm/mach-types.h>
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040021
22/*
23 * Display CPU and Board information
24 */
25#define CONFIG_DISPLAY_CPUINFO 1
26#define CONFIG_DISPLAY_BOARDINFO 1
27
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040028#define CONFIG_MISC_INIT_R
29
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040030#define CONFIG_REVISION_TAG 1
31
Enric Balletbo i Serraf3b4bc42015-01-28 15:01:32 +010032/* Status LED */
33#define CONFIG_STATUS_LED
34#define CONFIG_BOARD_SPECIFIC_LED
35#define CONFIG_GPIO_LED
36#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
37#define RED_LED_GPIO 27
Enric Balletbo i Serrad9aacf42013-02-07 00:40:06 +000038#endif
Enric Balletbo i Serraf3b4bc42015-01-28 15:01:32 +010039#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
40#define RED_LED_GPIO 16
41#endif
42#define RED_LED_DEV 0
43#define STATUS_LED_BIT RED_LED_GPIO
44#define STATUS_LED_STATE STATUS_LED_ON
45#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
46#define STATUS_LED_BOOT RED_LED_DEV
Javier Martinez Canillas9d4f5422012-12-27 03:36:01 +000047
Enric Balletbo i Serradd1e8582014-01-25 22:52:22 +010048/* GPIO banks */
49#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */
50#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
51#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
52
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040053/* USB */
54#define CONFIG_MUSB_UDC 1
55#define CONFIG_USB_OMAP3 1
56#define CONFIG_TWL4030_USB 1
57
58/* USB device configuration */
59#define CONFIG_USB_DEVICE 1
60#define CONFIG_USB_TTY 1
61#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
62
63/* Change these to suit your needs */
64#define CONFIG_USBD_VENDORID 0x0451
65#define CONFIG_USBD_PRODUCTID 0x5678
66#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
67#define CONFIG_USBD_PRODUCT_NAME "IGEP"
68
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040069#define CONFIG_CMD_CACHE
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +000070#ifdef CONFIG_BOOT_ONENAND
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040071#define CONFIG_CMD_ONENAND /* ONENAND support */
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +000072#endif
Enric Balletbo i Serrad9aacf42013-02-07 00:40:06 +000073#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
74 (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040075#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
Javier Martinez Canillas77eea282012-12-27 01:35:56 +000076#endif
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040077#define CONFIG_CMD_DHCP
78#define CONFIG_CMD_PING
79#define CONFIG_CMD_NFS /* NFS support */
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040080
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +010081/*#undef CONFIG_ENV_IS_NOWHERE*/
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040082
83#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -040084 "usbtty=cdc_acm\0" \
85 "loadaddr=0x82000000\0" \
Javier Martinez Canillasa2fa28b2013-08-07 17:53:19 +020086 "dtbaddr=0x81600000\0" \
87 "bootdir=/boot\0" \
88 "bootfile=zImage\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -040089 "usbtty=cdc_acm\0" \
Javier Martinez Canillase5e73c12012-06-29 02:45:40 +000090 "console=ttyO2,115200n8\0" \
Enric Balletbo i Serraf1e445c2012-04-25 02:34:31 +000091 "mpurate=auto\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -040092 "vram=12M\0" \
93 "dvimode=1024x768MR-16@60\0" \
94 "defaultdisplay=dvi\0" \
95 "mmcdev=0\0" \
96 "mmcroot=/dev/mmcblk0p2 rw\0" \
Javier Martinez Canillasb4ebeb82012-06-29 02:45:41 +000097 "mmcrootfstype=ext4 rootwait\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -040098 "nandroot=/dev/mtdblock4 rw\0" \
99 "nandrootfstype=jffs2\0" \
100 "mmcargs=setenv bootargs console=${console} " \
101 "mpurate=${mpurate} " \
102 "vram=${vram} " \
103 "omapfb.mode=dvi:${dvimode} " \
104 "omapfb.debug=y " \
105 "omapdss.def_disp=${defaultdisplay} " \
106 "root=${mmcroot} " \
107 "rootfstype=${mmcrootfstype}\0" \
108 "nandargs=setenv bootargs console=${console} " \
109 "mpurate=${mpurate} " \
110 "vram=${vram} " \
111 "omapfb.mode=dvi:${dvimode} " \
112 "omapfb.debug=y " \
113 "omapdss.def_disp=${defaultdisplay} " \
114 "root=${nandroot} " \
115 "rootfstype=${nandrootfstype}\0" \
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200116 "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
Enric Balletbo i Serra1b8ec012012-04-25 02:33:50 +0000117 "importbootenv=echo Importing environment from mmc ...; " \
118 "env import -t $loadaddr $filesize\0" \
Javier Martinez Canillasa2fa28b2013-08-07 17:53:19 +0200119 "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
120 "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400121 "mmcboot=echo Booting from mmc ...; " \
122 "run mmcargs; " \
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200123 "bootz ${loadaddr}\0" \
Javier Martinez Canillasa2fa28b2013-08-07 17:53:19 +0200124 "mmcbootfdt=echo Booting with DT from mmc ...; " \
125 "bootz ${loadaddr} - ${dtbaddr}\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400126 "nandboot=echo Booting from onenand ...; " \
127 "run nandargs; " \
128 "onenand read ${loadaddr} 280000 400000; " \
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200129 "bootz ${loadaddr}\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400130
131#define CONFIG_BOOTCOMMAND \
Andrew Bradford66968112012-10-01 05:06:52 +0000132 "mmc dev ${mmcdev}; if mmc rescan; then " \
Enric Balletbo i Serra1b8ec012012-04-25 02:33:50 +0000133 "echo SD/MMC found on device ${mmcdev};" \
134 "if run loadbootenv; then " \
135 "run importbootenv;" \
136 "fi;" \
137 "if test -n $uenvcmd; then " \
138 "echo Running uenvcmd ...;" \
139 "run uenvcmd;" \
140 "fi;" \
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200141 "if run loadzimage; then " \
Javier Martinez Canillasa2fa28b2013-08-07 17:53:19 +0200142 "if test -n $dtbfile; then " \
143 "if run loadfdt; then " \
144 "run mmcbootfdt;" \
145 "fi;" \
146 "fi;" \
Enric Balletbo i Serra1b8ec012012-04-25 02:33:50 +0000147 "run mmcboot;" \
148 "fi;" \
149 "fi;" \
150 "run nandboot;" \
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400151
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400152/*
153 * FLASH and environment organization
154 */
155
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +0000156#ifdef CONFIG_BOOT_ONENAND
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400157#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
158
159#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
160
161#define CONFIG_ENV_IS_IN_ONENAND 1
162#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
163#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +0000164#endif
165
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +0100166#ifdef CONFIG_NAND
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +0000167#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
168#define CONFIG_ENV_IS_IN_NAND 1
169#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
170#define CONFIG_ENV_ADDR NAND_ENV_OFFSET
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +0000171#endif
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400172
173/*
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400174 * SMSC911x Ethernet
175 */
176#if defined(CONFIG_CMD_NET)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400177#define CONFIG_SMC911X
178#define CONFIG_SMC911X_32_BIT
179#define CONFIG_SMC911X_BASE 0x2C000000
180#endif /* (CONFIG_CMD_NET) */
181
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +0100182/* OneNAND boot config */
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000183#ifdef CONFIG_BOOT_ONENAND
184#define CONFIG_SPL_ONENAND_SUPPORT
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000185#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
186#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
187#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
188#define CONFIG_SPL_ONENAND_LOAD_SIZE \
189 (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
190
191#endif
192
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000193/* NAND boot config */
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +0100194#ifdef CONFIG_NAND
pekon guptab80a6602014-05-06 00:46:19 +0530195#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000196#define CONFIG_SYS_NAND_5_ADDR_CYCLE
197#define CONFIG_SYS_NAND_PAGE_COUNT 64
198#define CONFIG_SYS_NAND_PAGE_SIZE 2048
199#define CONFIG_SYS_NAND_OOBSIZE 64
200#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
201#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
202#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
203 10, 11, 12, 13}
204#define CONFIG_SYS_NAND_ECCSIZE 512
205#define CONFIG_SYS_NAND_ECCBYTES 3
pekon gupta3f719062013-11-18 19:03:01 +0530206#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
pekon gupta434f2cf2014-07-18 17:59:42 +0530207#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
208/* NAND: SPL falcon mode configs */
209#ifdef CONFIG_SPL_OS_BOOT
210#define CONFIG_CMD_SPL_NAND_OFS 0x240000
211#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
212#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
213#endif
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000214#endif
215
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +0000216#endif /* __IGEP00X0_H */