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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ea5c50f297774ee7c7078a4138d84de3a6150dba / . / examples / standalone / test_burst_lib.S
blob: aef4e324224e7dfbb706e404f5e8564a25758b91 [file] [log] [blame]
wdenk931da932005-05-07 19:06:32 +0000[diff] [blame]1/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25
26#include <ppc_asm.tmpl>
27#include <ppc_defs.h>
28#include <asm/cache.h>
29#include <asm/mmu.h>
30#include "test_burst.h"
31
32 .text
33/*
34 * void mmu_init(void);
35 *
36 * This function turns the MMU on
37 *
38 * Three 8 MByte regions are mapped 1:1, uncached
39 * - SDRAM lower 8 MByte
40 * - SDRAM higher 8 MByte
41 * - IMMR
42 */
43 .global mmu_init
44mmu_init:
45 tlbia /* Invalidate all TLB entries */
46 li r8, 0
47 mtspr MI_CTR, r8 /* Set instruction control to zero */
48 lis r8, MD_RESETVAL@h
49 mtspr MD_CTR, r8 /* Set data TLB control */
50
51 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
52 * we can load the instruction and data TLB registers with the
53 * same values.
54 */
55 li r8, MI_EVALID /* Create EPN for address 0 */
56 mtspr MI_EPN, r8
57 mtspr MD_EPN, r8
58 li r8, MI_PS8MEG /* Set 8M byte page */
59 ori r8, r8, MI_SVALID /* Make it valid */
60 mtspr MI_TWC, r8
61 mtspr MD_TWC, r8
62 li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */
63 mtspr MI_RPN, r8 /* Store TLB entry */
64 mtspr MD_RPN, r8
65 lis r8, MI_Kp@h /* Set the protection mode */
66 mtspr MI_AP, r8
67 mtspr MD_AP, r8
68
69 /* Now map the higher 8 Meg into the TLBs. For this quick hack,
70 * we can load the instruction and data TLB registers with the
71 * same values.
72 */
Wolfgang Denke7670f62008-02-14 22:43:22 +0100[diff] [blame]73 lwz r9,20(r2) /* gd->ram_size */
wdenk931da932005-05-07 19:06:32 +0000[diff] [blame]74 addis r9,r9,-0x80
75
76 mr r8, r9 /* Higher 8 Meg in SDRAM */
77 ori r8, r8, MI_EVALID /* Mark page valid */
78 mtspr MI_EPN, r8
79 mtspr MD_EPN, r8
80 li r8, MI_PS8MEG /* Set 8M byte page */
81 ori r8, r8, MI_SVALID /* Make it valid */
82 mtspr MI_TWC, r8
83 mtspr MD_TWC, r8
84 mr r8, r9
85 ori r8, r8, MI_BOOTINIT|0x2
86 mtspr MI_RPN, r8 /* Store TLB entry */
87 mtspr MD_RPN, r8
88 lis r8, MI_Kp@h /* Set the protection mode */
89 mtspr MI_AP, r8
90 mtspr MD_AP, r8
91
92 /* Map another 8 MByte at the IMMR to get the processor
93 * internal registers (among other things).
94 */
95 mfspr r9, 638 /* Get current IMMR */
96 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
97
98 mr r8, r9 /* Create vaddr for TLB */
99 ori r8, r8, MD_EVALID /* Mark it valid */
100 mtspr MD_EPN, r8
101 li r8, MD_PS8MEG /* Set 8M byte page */
102 ori r8, r8, MD_SVALID /* Make it valid */
103 mtspr MD_TWC, r8
104 mr r8, r9 /* Create paddr for TLB */
105 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
106 mtspr MD_RPN, r8
107
108 /* We now have the lower and higher 8 Meg mapped into TLB entries,
109 * and the caches ready to work.
110 */
111 mfmsr r0
112 ori r0,r0,MSR_DR|MSR_IR
113 mtspr SRR1,r0
114 mflr r0
115 mtspr SRR0,r0
116 SYNC
117 rfi /* enables MMU */
118
119/*
120 * void caches_init(void);
121 */
122 .globl caches_init
123caches_init:
124 sync
125
126 mfspr r3, IC_CST /* Clear error bits */
127 mfspr r3, DC_CST
128
129 lis r3, IDC_UNALL@h /* Unlock all */
130 mtspr IC_CST, r3
131 mtspr DC_CST, r3
132
133 lis r3, IDC_INVALL@h /* Invalidate all */
134 mtspr IC_CST, r3
135 mtspr DC_CST, r3
136
137 lis r3, IDC_ENABLE@h /* Enable all */
138 mtspr IC_CST, r3
139 mtspr DC_CST, r3
140
141 blr
142
143/*
144 * void flush_dcache_range(unsigned long start, unsigned long stop);
145 */
146 .global flush_dcache_range
147flush_dcache_range:
148 li r5,CACHE_LINE_SIZE-1
149 andc r3,r3,r5
150 subf r4,r3,r4
151 add r4,r4,r5
152 srwi. r4,r4,LG_CACHE_LINE_SIZE
153 beqlr
154 mtctr r4
155
1561: dcbf 0,r3
157 addi r3,r3,CACHE_LINE_SIZE
158 bdnz 1b
159 sync /* wait for dcbf's to get to ram */
160 blr
161
162/*
163 * void disable_interrupts(void);
164 */
165 .global disable_interrupts
166disable_interrupts:
167 mfmsr r0
168 rlwinm r0,r0,0,17,15
169 mtmsr r0
170 blr