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Wolfgang Grandegger1ca56202011-11-11 14:03:36 +01001/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <common.h>
17#include <usb.h>
18#include <errno.h>
19#include <linux/compiler.h>
20#include <usb/ehci-fsl.h>
21#include <asm/io.h>
22#include <asm/arch/imx-regs.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/mx5x_pins.h>
Marek Vasut1b80f272011-11-24 05:14:00 +010025#include <asm/arch/iomux.h>
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010026
27#include "ehci.h"
28#include "ehci-core.h"
29
30#define MX5_USBOTHER_REGS_OFFSET 0x800
31
32
33#define MXC_OTG_OFFSET 0
34#define MXC_H1_OFFSET 0x200
35#define MXC_H2_OFFSET 0x400
36
37#define MXC_USBCTRL_OFFSET 0
38#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
39#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
40#define MXC_USB_CTRL_1_OFFSET 0x10
41#define MXC_USBH2CTRL_OFFSET 0x14
42
43/* USB_CTRL */
44#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
45#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
46#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
47#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
48#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
49
50/* USB_PHY_CTRL_FUNC */
51#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
52#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
53
54/* USBH2CTRL */
55#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
56#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
57#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
58
59/* USB_CTRL_1 */
60#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
61
Marek Vasut0f8c86b2011-11-24 04:22:17 +010062/* USB pin configuration */
63#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
64 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
65 PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
66
67#ifdef CONFIG_MX51
68/*
69 * Configure the MX51 USB H1 IOMUX
70 */
71void setup_iomux_usb_h1(void)
72{
73 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
74 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
75 mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
76 mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
77 mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
78 mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
79 mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
80 mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
81
82 mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
83 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
84 mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
85 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
86 mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
87 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
88 mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
89 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
90 mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
91 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
92 mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
93 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
94 mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
95 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
96 mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
97 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
98}
99
100/*
101 * Configure the MX51 USB H2 IOMUX
102 */
103void setup_iomux_usb_h2(void)
104{
105 mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
106 mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
107 mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
108 mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
109 mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
110 mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
111 mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
112 mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
113
114 mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
115 mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
116 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
117 mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
118 mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
119 mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
120 mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
121 mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
122 mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
123 mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
124 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
125 mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
126 mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
127 mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
128 mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
129 mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
130}
131#endif
132
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100133int mxc_set_usbcontrol(int port, unsigned int flags)
134{
135 unsigned int v;
136 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
137 void __iomem *usbother_base;
138 int ret = 0;
139
140 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
141
142 switch (port) {
143 case 0: /* OTG port */
144 if (flags & MXC_EHCI_INTERNAL_PHY) {
145 v = __raw_readl(usbother_base +
146 MXC_USB_PHY_CTR_FUNC_OFFSET);
147 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
148 /* OC/USBPWR is not used */
149 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
150 else
151 /* OC/USBPWR is used */
152 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
153 __raw_writel(v, usbother_base +
154 MXC_USB_PHY_CTR_FUNC_OFFSET);
155
156 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
157 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
158 v |= MXC_OTG_UCTRL_OPM_BIT;
159 else
160 v &= ~MXC_OTG_UCTRL_OPM_BIT;
161 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
162 }
163 break;
164 case 1: /* Host 1 Host ULPI */
165#ifdef CONFIG_MX51
166 /* The clock for the USBH1 ULPI port will come externally
167 from the PHY. */
168 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
169 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
170 MXC_USB_CTRL_1_OFFSET);
171#endif
172
173 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
174 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
175 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
176 else
177 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
178 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
179
180 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
181 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
182 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
183 else
184 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
185 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
186
187 break;
188 case 2: /* Host 2 ULPI */
189 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
190 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
191 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
192 else
193 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
194
195 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
196 break;
197 }
198
199 return ret;
200}
201
Marek Vasut1b80f272011-11-24 05:14:00 +0100202void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
203{
204}
205
206void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
207 __attribute((weak, alias("__board_ehci_hcd_postinit")));
208
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100209int ehci_hcd_init(void)
210{
211 struct usb_ehci *ehci;
212#ifdef CONFIG_MX53
213 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
214 u32 reg;
215
216 reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
217 /* derive USB PHY clock multiplexer from PLL3 */
218 reg |= 1 << 26;
219 __raw_writel(reg, &sc_regs->cscmr1);
220#endif
221
222 set_usboh3_clk();
223 enable_usboh3_clk(1);
224 set_usb_phy2_clk();
225 enable_usb_phy2_clk(1);
226 mdelay(1);
227
Marek Vasut1b80f272011-11-24 05:14:00 +0100228 /* Do board specific initialization */
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100229 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
230
231 ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
232 (0x200 * CONFIG_MXC_USB_PORT));
233 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
234 hcor = (struct ehci_hcor *)((uint32_t)hccr +
235 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
236 setbits_le32(&ehci->usbmode, CM_HOST);
237
238 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
239 setbits_le32(&ehci->portsc, USB_EN);
240
241 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100242 mdelay(10);
243
Marek Vasut1b80f272011-11-24 05:14:00 +0100244 /* Do board specific post-initialization */
245 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
246
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100247 return 0;
248}
249
250int ehci_hcd_stop(void)
251{
252 return 0;
253}