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Matthias Fuchs8ba132c2007-12-28 17:07:24 +01001/*
Matthias Fuchs76b565b2008-10-28 13:36:58 +01002 * (C) Copyright 2007-2008
Matthias Fuchs8ba132c2007-12-28 17:07:24 +01003 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on the sequoia configuration file.
5 *
6 * (C) Copyright 2006-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * (C) Copyright 2006
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010014 */
15
16/************************************************************************
17 * PMC440.h - configuration for esd PMC440 boards
18 ***********************************************************************/
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22/*-----------------------------------------------------------------------
23 * High Level Configuration Options
24 *----------------------------------------------------------------------*/
25#define CONFIG_440EPX 1 /* Specific PPC440EPx */
26#define CONFIG_440 1 /* ... PPC440 family */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010027
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#ifndef CONFIG_SYS_TEXT_BASE
29#define CONFIG_SYS_TEXT_BASE 0xFFF90000
30#endif
31
Matthias Fuchsf39c5d12014-10-24 12:44:40 +020032#define CONFIG_DISPLAY_BOARDINFO
33
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010034#define CONFIG_SYS_CLK_FREQ 33333400
35
Matthias Fuchsff41ffc2008-01-11 14:55:16 +010036#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010037#define CONFIG_4xx_DCACHE /* enable dcache */
Matthias Fuchsff41ffc2008-01-11 14:55:16 +010038#endif
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010039
40#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Matthias Fuchs76b565b2008-10-28 13:36:58 +010041#define CONFIG_MISC_INIT_F 1
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010042#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
43#define CONFIG_BOARD_TYPES 1 /* support board types */
44/*-----------------------------------------------------------------------
45 * Base addresses -- Note these are effective addresses where the
46 * actual resources get mapped (not physical addresses)
47 *----------------------------------------------------------------------*/
Wolfgang Denk14d0a022010-10-07 21:51:12 +020048#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010050
51#define CONFIG_PRAM 0 /* use pram variable to overwrite */
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
54#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
55#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
Wolfgang Denk14d0a022010-10-07 21:51:12 +020056#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
58#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
59#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
60#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
61#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
62#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
63#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
64#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
65#define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_USB2D0_BASE 0xe0000100
68#define CONFIG_SYS_USB_DEVICE 0xe0000000
69#define CONFIG_SYS_USB_HOST 0xe0000400
70#define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */
71#define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */
Matthias Fuchs76b565b2008-10-28 13:36:58 +010072#define CONFIG_SYS_RESET_BASE 0xef200000
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010073
74/*-----------------------------------------------------------------------
75 * Initial RAM & stack pointer
76 *----------------------------------------------------------------------*/
77/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020079#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020080#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020081#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010082
83/*-----------------------------------------------------------------------
84 * Serial Port
85 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020086#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese550650d2010-09-20 16:05:31 +020087#define CONFIG_SYS_NS16550_SERIAL
88#define CONFIG_SYS_NS16550_REG_SIZE 1
89#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010091#define CONFIG_BAUDRATE 115200
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_BAUDRATE_TABLE \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010094 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
95
96/*-----------------------------------------------------------------------
97 * Environment
98 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020099#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100100
101/*-----------------------------------------------------------------------
102 * RTC
103 *----------------------------------------------------------------------*/
104#define CONFIG_RTC_RX8025
105
106/*-----------------------------------------------------------------------
107 * FLASH related
108 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200110#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
115#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
118#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
121#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
124#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100125
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200126#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200127#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100129#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100130
131/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200132#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
133#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100134#endif
135
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200136#ifdef CONFIG_ENV_IS_IN_EEPROM
Matthias Fuchsf39c5d12014-10-24 12:44:40 +0200137#define CONFIG_I2C_ENV_EEPROM_BUS 0
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200138#define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
139#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100140#endif
141
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100142/*-----------------------------------------------------------------------
143 * DDR SDRAM
144 *----------------------------------------------------------------------*/
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100145#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Jean-Christophe PLAGNIOL-VILLARD3aed3aa2008-12-14 10:29:39 +0100146#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
147 /* 440EPx errata CHIP 11 */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100148
149/*-----------------------------------------------------------------------
150 * I2C
151 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000152#define CONFIG_SYS_I2C
153#define CONFIG_SYS_I2C_PPC4XX
154#define CONFIG_SYS_I2C_PPC4XX_CH0
155#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
156#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
157#define CONFIG_SYS_I2C_PPC4XX_CH1
158#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
159#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100160
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
163#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
164#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
165#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
166#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_EEPROM_WREN 1
169#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100170
171/*
172 * standard dtt sensor configuration - bottom bit will determine local or
173 * remote sensor of the TMP401
174 */
175#define CONFIG_DTT_SENSORS { 0, 1 }
176
177/*
178 * The PMC440 uses a TI TMP401 temperature sensor. This part
179 * is basically compatible to the ADM1021 that is supported
180 * by U-Boot.
181 *
182 * - i2c addr 0x4c
183 * - conversion rate 0x02 = 0.25 conversions/second
184 * - ALERT ouput disabled
185 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
186 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
187 */
188#define CONFIG_DTT_ADM1021
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100190
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100191#define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \
192 "\\\"painit\\\" to preboot command"
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100193
194#undef CONFIG_BOOTARGS
195
196/* Setup some board specific values for the default environment variables */
197#define CONFIG_HOSTNAME pmc440
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100198#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
199#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100200
201#define CONFIG_EXTRA_ENV_SETTINGS \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100202 CONFIG_SYS_BOOTFILE \
203 CONFIG_SYS_ROOTPATH \
204 "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100205 "netdev=eth0\0" \
Matthias Fuchsff41ffc2008-01-11 14:55:16 +0100206 "ethrotate=no\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100207 "nfsargs=setenv bootargs root=/dev/nfs rw " \
208 "nfsroot=${serverip}:${rootpath}\0" \
209 "ramargs=setenv bootargs root=/dev/ram rw\0" \
210 "addip=setenv bootargs ${bootargs} " \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100211 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
212 ":${hostname}:${netdev}:off panic=1\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100213 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100214 "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
215 "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100216 "nand_boot_fdt=run nandargs addip addtty addmisc;" \
217 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100218 "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \
219 "tftp ${fdt_addr_r} ${fdt_file};" \
220 "run nfsargs addip addtty addmisc;" \
221 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
222 "kernel_addr=ffc00000\0" \
223 "kernel_addr_r=200000\0" \
224 "fpga_addr=fff00000\0" \
225 "fdt_addr=fff80000\0" \
226 "fdt_addr_r=800000\0" \
227 "fpga=fpga loadb 0 ${fpga_addr}\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100228 "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
Matthias Fuchs5baefbb2010-07-26 17:17:53 +0200229 "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \
230 "cp.b 200000 fff90000 70000\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100231 ""
232
233#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
234
235#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100237
Ben Warren96e21f82008-10-27 23:50:15 -0700238#define CONFIG_PPC4xx_EMAC
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100239#define CONFIG_IBM_EMAC4_V4 1
240#define CONFIG_MII 1 /* MII PHY management */
241#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
242
243#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
244
245#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100247
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100248#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
249#define CONFIG_PHY1_ADDR 1
250#define CONFIG_RESET_PHY_R 1
251
252/* USB */
253#define CONFIG_USB_OHCI_NEW
254#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
258#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
259#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
260#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
261#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100262
263/* Comment this out to enable USB 1.1 device */
264#define USB_2_0_DEVICE
265
266/* Partitions */
267#define CONFIG_MAC_PARTITION
268#define CONFIG_DOS_PARTITION
269#define CONFIG_ISO_PARTITION
270
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100271#define CONFIG_CMD_BSP
272#define CONFIG_CMD_DATE
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100273#define CONFIG_CMD_DHCP
274#define CONFIG_CMD_DTT
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100275#define CONFIG_CMD_EEPROM
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100276#define CONFIG_CMD_FAT
277#define CONFIG_CMD_I2C
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100278#define CONFIG_CMD_MII
279#define CONFIG_CMD_NAND
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100280#define CONFIG_CMD_PCI
281#define CONFIG_CMD_PING
282#define CONFIG_CMD_USB
283#define CONFIG_CMD_REGINFO
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100284
285/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
287 CONFIG_SYS_POST_CPU | \
288 CONFIG_SYS_POST_UART | \
289 CONFIG_SYS_POST_I2C | \
290 CONFIG_SYS_POST_CACHE | \
291 CONFIG_SYS_POST_FPU | \
292 CONFIG_SYS_POST_ETHER | \
293 CONFIG_SYS_POST_SPR)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100294
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100295#define CONFIG_LOGBUFFER
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100296#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100299
300#define CONFIG_SUPPORT_VFAT
301
302/*-----------------------------------------------------------------------
303 * Miscellaneous configurable options
304 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_LONGHELP /* undef to save memory */
Stefan Roesebe88b162008-01-17 07:50:17 +0100306#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100308#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100310#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
312#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
313#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
316#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
319#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100320
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100321#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
322#define CONFIG_LOOPW 1 /* enable loopw command */
323#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
324#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
325#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
326
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100327/*-----------------------------------------------------------------------
328 * PCI stuff
329 *----------------------------------------------------------------------*/
330/* General PCI */
331#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000332#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100333#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100335#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100337
338/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_PCI_TARGET_INIT
340#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roesea760b022009-11-12 16:41:09 +0100341#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100342
Matthias Fuchs2fe6b7f2011-10-13 15:12:22 +0200343#define CONFIG_PCI_BOOTDELAY 0
344
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100345/* PCI identification */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
347#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
348#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
Stefan Roese10954932009-11-12 12:00:49 +0100349/* for weak __pci_target_init() */
350#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
352#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100353
354/*
355 * For booting Linux, the board info and command line data
356 * have to be in the first 8 MB of memory, since this is
357 * the maximum mapped by the Linux kernel during initialization.
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100360
361/*-----------------------------------------------------------------------
362 * FPGA stuff
363 *----------------------------------------------------------------------*/
364#define CONFIG_FPGA
365#define CONFIG_FPGA_XILINX
366#define CONFIG_FPGA_SPARTAN2
367#define CONFIG_FPGA_SPARTAN3
368
369#define CONFIG_FPGA_COUNT 2
370/*-----------------------------------------------------------------------
371 * External Bus Controller (EBC) Setup
372 *----------------------------------------------------------------------*/
373
374/*
375 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
376 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100378
379/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_EBC_PB0AP 0x03017200
381#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100382
383/* Memory Bank 2 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_EBC_PB2AP 0x018003c0
385#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100386
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100387/* Memory Bank 1 (RESET) initialization */
Wolfgang Denk455ae7e2008-12-16 01:02:17 +0100388#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
Jean-Christophe PLAGNIOL-VILLARD3aed3aa2008-12-14 10:29:39 +0100389#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100390
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100391/* Memory Bank 4 (FPGA / 32Bit) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
393#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100394
395/* Memory Bank 5 (FPGA / 16Bit) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
397#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100398
399/*-----------------------------------------------------------------------
400 * NAND FLASH
401 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
404#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100405
Stefan Roesebe88b162008-01-17 07:50:17 +0100406#if defined(CONFIG_CMD_KGDB)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100407#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100408#endif
409
410/* pass open firmware flat tree */
411#define CONFIG_OF_LIBFDT 1
412#define CONFIG_OF_BOARD_SETUP 1
413
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100414#define CONFIG_API 1
415
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100416#endif /* __CONFIG_H */