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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
6 * Add support the Sharp chips on the mpc8260ads.
7 * I started with board/ip860/flash.c and made changes I found in
8 * the MTD project by David Schleef.
9 *
wdenk8564acf2003-07-14 22:13:32 +000010 * (C) Copyright 2003 Arabella Software Ltd.
11 * Yuli Barcohen <yuli@arabellasw.com>
12 * Re-written to support multi-bank flash SIMMs.
13 * Added support for real protection and JFFS2.
14 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020015 * SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +000016 */
17
18#include <common.h>
19
wdenk8564acf2003-07-14 22:13:32 +000020/* Intel-compatible flash ID */
21#define INTEL_COMPAT 0x89898989
22#define INTEL_ALT 0xB0B0B0B0
wdenkaffae2b2002-08-17 09:36:01 +000023
wdenk8564acf2003-07-14 22:13:32 +000024/* Intel-compatible flash commands */
25#define INTEL_PROGRAM 0x10101010
26#define INTEL_ERASE 0x20202020
27#define INTEL_CLEAR 0x50505050
28#define INTEL_LOCKBIT 0x60606060
29#define INTEL_PROTECT 0x01010101
30#define INTEL_STATUS 0x70707070
31#define INTEL_READID 0x90909090
32#define INTEL_CONFIRM 0xD0D0D0D0
33#define INTEL_RESET 0xFFFFFFFF
wdenkaffae2b2002-08-17 09:36:01 +000034
wdenk8564acf2003-07-14 22:13:32 +000035/* Intel-compatible flash status bits */
36#define INTEL_FINISHED 0x80808080
37#define INTEL_OK 0x80808080
38
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
wdenkaffae2b2002-08-17 09:36:01 +000040
41/*-----------------------------------------------------------------------
wdenk8564acf2003-07-14 22:13:32 +000042 * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
43 * Up to 32MB of flash supported (up to 4 banks.)
44 * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
45 *
46 * The following code can not run from flash!
wdenkaffae2b2002-08-17 09:36:01 +000047 */
wdenkaffae2b2002-08-17 09:36:01 +000048unsigned long flash_init (void)
49{
wdenk8564acf2003-07-14 22:13:32 +000050 ulong size = 0, sect_start, sect_size = 0, bank_size;
51 ushort sect_count = 0;
52 int i, j, nbanks;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
54 vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
wdenkaffae2b2002-08-17 09:36:01 +000055
wdenk8564acf2003-07-14 22:13:32 +000056 switch (bcsr[2] & 0xF) {
57 case 0:
58 nbanks = 4;
59 break;
60 case 1:
61 nbanks = 2;
62 break;
63 case 2:
64 nbanks = 1;
65 break;
66 default: /* Unsupported configurations */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067 nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
wdenkaffae2b2002-08-17 09:36:01 +000068 }
69
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070 if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
71 nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
wdenkaffae2b2002-08-17 09:36:01 +000072
wdenk8564acf2003-07-14 22:13:32 +000073 for (i = 0; i < nbanks; i++) {
74 *addr = INTEL_READID; /* Read Intelligent Identifier */
75 if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
76 switch (addr[1]) {
77 case SHARP_ID_28F016SCL:
78 case SHARP_ID_28F016SCZ:
79 flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
80 sect_count = 32;
81 sect_size = 0x40000;
82 break;
83 default:
84 flash_info[i].flash_id = FLASH_UNKNOWN;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085 sect_count = CONFIG_SYS_MAX_FLASH_SECT;
wdenk8564acf2003-07-14 22:13:32 +000086 sect_size =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
wdenk8564acf2003-07-14 22:13:32 +000088 }
89 }
90 else
91 flash_info[i].flash_id = FLASH_UNKNOWN;
92 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
93 printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
94 addr[0], addr[1], (ulong)addr);
95 size = 0;
96 *addr = INTEL_RESET; /* Reset bank to Read Array mode */
97 break;
98 }
99 flash_info[i].sector_count = sect_count;
100 flash_info[i].size = bank_size = sect_size * sect_count;
101 size += bank_size;
102 sect_start = (ulong)addr;
103 for (j = 0; j < sect_count; j++) {
104 addr = (vu_long *)sect_start;
105 flash_info[i].start[j] = sect_start;
106 flash_info[i].protect[j] = (addr[2] == 0x01010101);
107 sect_start += sect_size;
108 }
109 *addr = INTEL_RESET; /* Reset bank to Read Array mode */
110 addr = (vu_long *)sect_start;
wdenkaffae2b2002-08-17 09:36:01 +0000111 }
wdenkaffae2b2002-08-17 09:36:01 +0000112
wdenk8564acf2003-07-14 22:13:32 +0000113 if (size == 0) { /* Unknown flash, fill with hard-coded values */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 sect_start = CONFIG_SYS_FLASH_BASE;
115 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
wdenk8564acf2003-07-14 22:13:32 +0000116 flash_info[i].flash_id = FLASH_UNKNOWN;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117 flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
wdenk8564acf2003-07-14 22:13:32 +0000118 flash_info[i].sector_count = sect_count;
119 for (j = 0; j < sect_count; j++) {
120 flash_info[i].start[j] = sect_start;
121 flash_info[i].protect[j] = 0;
122 sect_start += sect_size;
123 }
124 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 size = CONFIG_SYS_FLASH_SIZE;
wdenk8564acf2003-07-14 22:13:32 +0000126 }
127 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
wdenk8564acf2003-07-14 22:13:32 +0000129 flash_info[i].flash_id = FLASH_UNKNOWN;
130 flash_info[i].size = 0;
131 flash_info[i].sector_count = 0;
132 }
wdenkaffae2b2002-08-17 09:36:01 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
wdenkaffae2b2002-08-17 09:36:01 +0000135 /* monitor protection ON by default */
136 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 CONFIG_SYS_MONITOR_BASE,
138 CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
wdenkaffae2b2002-08-17 09:36:01 +0000139 &flash_info[0]);
140#endif
141
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200142#ifdef CONFIG_ENV_IS_IN_FLASH
wdenkaffae2b2002-08-17 09:36:01 +0000143 /* ENV protection ON by default */
144 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200145 CONFIG_ENV_ADDR,
146 CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
wdenkaffae2b2002-08-17 09:36:01 +0000147 &flash_info[0]);
148#endif
149 return (size);
150}
151
152/*-----------------------------------------------------------------------
153 */
154void flash_print_info (flash_info_t *info)
155{
156 int i;
157
158 if (info->flash_id == FLASH_UNKNOWN) {
159 printf ("missing or unknown FLASH type\n");
160 return;
161 }
162
163 switch (info->flash_id & FLASH_VENDMASK) {
164 case FLASH_MAN_INTEL: printf ("Intel "); break;
165 case FLASH_MAN_SHARP: printf ("Sharp "); break;
166 default: printf ("Unknown Vendor "); break;
167 }
168
169 switch (info->flash_id & FLASH_TYPEMASK) {
170 case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
171 break;
172 case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
173 break;
174 case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
175 break;
176 case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
177 break;
178 default: printf ("Unknown Chip Type\n");
179 break;
180 }
181
182 printf (" Size: %ld MB in %d Sectors\n",
183 info->size >> 20, info->sector_count);
184
185 printf (" Sector Start Addresses:");
186 for (i=0; i<info->sector_count; ++i) {
187 if ((i % 5) == 0)
188 printf ("\n ");
189 printf (" %08lX%s",
190 info->start[i],
191 info->protect[i] ? " (RO)" : " "
192 );
193 }
194 printf ("\n");
195}
196
197/*-----------------------------------------------------------------------
198 */
wdenkaffae2b2002-08-17 09:36:01 +0000199int flash_erase (flash_info_t *info, int s_first, int s_last)
200{
201 int flag, prot, sect;
202 ulong start, now, last;
203
204 if ((s_first < 0) || (s_first > s_last)) {
205 if (info->flash_id == FLASH_UNKNOWN) {
206 printf ("- missing\n");
207 } else {
208 printf ("- no sectors to erase\n");
209 }
210 return 1;
211 }
212
213 if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
214 && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
215 printf ("Can't erase unknown flash type %08lx - aborted\n",
216 info->flash_id);
217 return 1;
218 }
219
220 prot = 0;
221 for (sect=s_first; sect<=s_last; ++sect) {
222 if (info->protect[sect]) {
223 prot++;
224 }
225 }
226
227 if (prot) {
228 printf ("- Warning: %d protected sectors will not be erased!\n",
229 prot);
230 } else {
231 printf ("\n");
232 }
233
wdenkaffae2b2002-08-17 09:36:01 +0000234 /* Start erase on unprotected sectors */
235 for (sect = s_first; sect<=s_last; sect++) {
236 if (info->protect[sect] == 0) { /* not protected */
237 vu_long *addr = (vu_long *)(info->start[sect]);
238
239 last = start = get_timer (0);
240
241 /* Disable interrupts which might cause a timeout here */
242 flag = disable_interrupts();
243
wdenkaffae2b2002-08-17 09:36:01 +0000244 /* Clear Status Register */
wdenk8564acf2003-07-14 22:13:32 +0000245 *addr = INTEL_CLEAR;
wdenkaffae2b2002-08-17 09:36:01 +0000246 /* Single Block Erase Command */
wdenk8564acf2003-07-14 22:13:32 +0000247 *addr = INTEL_ERASE;
wdenkaffae2b2002-08-17 09:36:01 +0000248 /* Confirm */
wdenk8564acf2003-07-14 22:13:32 +0000249 *addr = INTEL_CONFIRM;
wdenkaffae2b2002-08-17 09:36:01 +0000250
251 if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
252 /* Resume Command, as per errata update */
wdenk8564acf2003-07-14 22:13:32 +0000253 *addr = INTEL_CONFIRM;
wdenkaffae2b2002-08-17 09:36:01 +0000254 }
255
256 /* re-enable interrupts if necessary */
257 if (flag)
258 enable_interrupts();
259
wdenk8564acf2003-07-14 22:13:32 +0000260 while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261 if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
wdenkaffae2b2002-08-17 09:36:01 +0000262 printf ("Timeout\n");
wdenk8564acf2003-07-14 22:13:32 +0000263 *addr = INTEL_RESET; /* reset bank */
wdenkaffae2b2002-08-17 09:36:01 +0000264 return 1;
265 }
266 /* show that we're waiting */
267 if ((now - last) > 1000) { /* every second */
268 putc ('.');
269 last = now;
270 }
271 }
272
wdenk8564acf2003-07-14 22:13:32 +0000273 if (*addr != INTEL_OK) {
274 printf("Block erase failed at %08X, CSR=%08X\n",
275 (uint)addr, (uint)*addr);
276 *addr = INTEL_RESET; /* reset bank */
277 return 1;
278 }
279
wdenkaffae2b2002-08-17 09:36:01 +0000280 /* reset to read mode */
wdenk8564acf2003-07-14 22:13:32 +0000281 *addr = INTEL_RESET;
wdenkaffae2b2002-08-17 09:36:01 +0000282 }
283 }
284
285 printf (" done\n");
286 return 0;
287}
288
289/*-----------------------------------------------------------------------
wdenk8564acf2003-07-14 22:13:32 +0000290 * Write a word to Flash, returns:
291 * 0 - OK
292 * 1 - write timeout
293 * 2 - Flash not erased
294 */
295static int write_word (flash_info_t *info, ulong dest, ulong data)
296{
297 ulong start;
298 int rc = 0;
299 int flag;
300 vu_long *addr = (vu_long *)dest;
301
302 /* Check if Flash is (sufficiently) erased */
303 if ((*addr & data) != data) {
304 return (2);
305 }
306
307 *addr = INTEL_CLEAR; /* Clear status register */
308
309 /* Disable interrupts which might cause a timeout here */
310 flag = disable_interrupts();
311
312 /* Write Command */
313 *addr = INTEL_PROGRAM;
314
315 /* Write Data */
316 *addr = data;
317
318 /* re-enable interrupts if necessary */
319 if (flag)
320 enable_interrupts();
321
322 /* data polling for D7 */
323 start = get_timer (0);
324 while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325 if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
wdenk8564acf2003-07-14 22:13:32 +0000326 printf("Write timed out\n");
327 rc = 1;
328 break;
329 }
330 }
331 if (*addr != INTEL_OK) {
332 printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
333 rc = 1;
334 }
335
336 *addr = INTEL_RESET; /* Reset to read array mode */
337
338 return rc;
339}
340
341/*-----------------------------------------------------------------------
wdenkaffae2b2002-08-17 09:36:01 +0000342 * Copy memory to flash, returns:
343 * 0 - OK
344 * 1 - write timeout
345 * 2 - Flash not erased
346 */
347
348int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
349{
350 ulong cp, wp, data;
351 int i, l, rc;
352
353 wp = (addr & ~3); /* get lower word aligned address */
354
wdenk8564acf2003-07-14 22:13:32 +0000355 *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
356
wdenkaffae2b2002-08-17 09:36:01 +0000357 /*
358 * handle unaligned start bytes
359 */
360 if ((l = addr - wp) != 0) {
361 data = 0;
362 for (i=0, cp=wp; i<l; ++i, ++cp) {
363 data = (data << 8) | (*(uchar *)cp);
364 }
365 for (; i<4 && cnt>0; ++i) {
366 data = (data << 8) | *src++;
367 --cnt;
368 ++cp;
369 }
370 for (; cnt==0 && i<4; ++i, ++cp) {
371 data = (data << 8) | (*(uchar *)cp);
372 }
373
374 if ((rc = write_word(info, wp, data)) != 0) {
375 return (rc);
376 }
377 wp += 4;
378 }
379
380 /*
381 * handle word aligned part
382 */
383 while (cnt >= 4) {
384 data = 0;
385 for (i=0; i<4; ++i) {
386 data = (data << 8) | *src++;
387 }
388 if ((rc = write_word(info, wp, data)) != 0) {
389 return (rc);
390 }
391 wp += 4;
392 cnt -= 4;
393 }
394
395 if (cnt == 0) {
396 return (0);
397 }
398
399 /*
400 * handle unaligned tail bytes
401 */
402 data = 0;
403 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
404 data = (data << 8) | *src++;
405 --cnt;
406 }
407 for (; i<4; ++i, ++cp) {
408 data = (data << 8) | (*(uchar *)cp);
409 }
410
wdenk8564acf2003-07-14 22:13:32 +0000411 rc = write_word(info, wp, data);
412
413 return rc;
wdenkaffae2b2002-08-17 09:36:01 +0000414}
415
416/*-----------------------------------------------------------------------
wdenk8564acf2003-07-14 22:13:32 +0000417 * Set/Clear sector's lock bit, returns:
wdenkaffae2b2002-08-17 09:36:01 +0000418 * 0 - OK
wdenk8564acf2003-07-14 22:13:32 +0000419 * 1 - Error (timeout, voltage problems, etc.)
wdenkaffae2b2002-08-17 09:36:01 +0000420 */
wdenk8564acf2003-07-14 22:13:32 +0000421int flash_real_protect(flash_info_t *info, long sector, int prot)
wdenkaffae2b2002-08-17 09:36:01 +0000422{
wdenk8564acf2003-07-14 22:13:32 +0000423 ulong start;
424 int i;
425 int rc = 0;
426 vu_long *addr = (vu_long *)(info->start[sector]);
427 int flag = disable_interrupts();
wdenkaffae2b2002-08-17 09:36:01 +0000428
wdenk8564acf2003-07-14 22:13:32 +0000429 *addr = INTEL_CLEAR; /* Clear status register */
430 if (prot) { /* Set sector lock bit */
431 *addr = INTEL_LOCKBIT; /* Sector lock bit */
432 *addr = INTEL_PROTECT; /* set */
wdenkaffae2b2002-08-17 09:36:01 +0000433 }
wdenk8564acf2003-07-14 22:13:32 +0000434 else { /* Clear sector lock bit */
435 *addr = INTEL_LOCKBIT; /* All sectors lock bits */
436 *addr = INTEL_CONFIRM; /* clear */
437 }
wdenkaffae2b2002-08-17 09:36:01 +0000438
wdenk8564acf2003-07-14 22:13:32 +0000439 start = get_timer(0);
440 while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441 if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
wdenk8564acf2003-07-14 22:13:32 +0000442 printf("Flash lock bit operation timed out\n");
443 rc = 1;
wdenkaffae2b2002-08-17 09:36:01 +0000444 break;
445 }
446 }
wdenk8564acf2003-07-14 22:13:32 +0000447
448 if (*addr != INTEL_OK) {
449 printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
450 (uint)addr, (uint)*addr);
451 rc = 1;
wdenkaffae2b2002-08-17 09:36:01 +0000452 }
453
wdenk8564acf2003-07-14 22:13:32 +0000454 if (!rc)
455 info->protect[sector] = prot;
wdenkaffae2b2002-08-17 09:36:01 +0000456
wdenk8564acf2003-07-14 22:13:32 +0000457 /*
458 * Clear lock bit command clears all sectors lock bits, so
459 * we have to restore lock bits of protected sectors.
460 */
461 if (!prot)
462 for (i = 0; i < info->sector_count; i++)
463 if (info->protect[i]) {
464 addr = (vu_long *)(info->start[i]);
465 *addr = INTEL_LOCKBIT; /* Sector lock bit */
466 *addr = INTEL_PROTECT; /* set */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467 udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
wdenk8564acf2003-07-14 22:13:32 +0000468 }
469
470 if (flag)
471 enable_interrupts();
472
473 *addr = INTEL_RESET; /* Reset to read array mode */
474
475 return rc;
wdenkaffae2b2002-08-17 09:36:01 +0000476}