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wdenkbb0f96b2002-02-17 23:48:45 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * 74xx_7xx.h
26 *
27 * 74xx/7xx specific definitions
28 */
29
30#ifndef __MPC74XX_H__
31#define __MPC74XX_H__
32
33/*----------------------------------------------------------------
34 * Exception offsets (PowerPC standard)
35 */
36#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
37
38/*----------------------------------------------------------------
39 * l2cr values
40 */
41#define l2cr 1017
42
43#define L2CR_L2E 0x80000000 /* bit 0 - enable */
44#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
45#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
46#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
47#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
48#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
49#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
50#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
51#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
52#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
53#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
54#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
55#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
56#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
57#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
58#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
59#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
60#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
61#define L2CR_TS 0x00040000 /* bit 13 - test support on */
62#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
63#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
64#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
65#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
66#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
67
68/*----------------------------------------------------------------
69 * BAT settings. Look in config_<BOARD>.h for the actual setup
70 */
71
72#define BATU_BL_128K 0x00000000
73#define BATU_BL_256K 0x00000004
74#define BATU_BL_512K 0x0000000c
75#define BATU_BL_1M 0x0000001c
76#define BATU_BL_2M 0x0000003c
77#define BATU_BL_4M 0x0000007c
78#define BATU_BL_8M 0x000000fc
79#define BATU_BL_16M 0x000001fc
80#define BATU_BL_32M 0x000003fc
81#define BATU_BL_64M 0x000007fc
82#define BATU_BL_128M 0x00000ffc
83#define BATU_BL_256M 0x00001ffc
84
85#define BATU_VS 0x00000002
86#define BATU_VP 0x00000001
87#define BATU_INVALID 0x00000000
88
89#define BATL_WRITETHROUGH 0x00000040
90#define BATL_CACHEINHIBIT 0x00000020
91#define BATL_MEMCOHERENCE 0x00000010
92#define BATL_GUARDEDSTORAGE 0x00000008
93#define BATL_NO_ACCESS 0x00000000
94
95#define BATL_PP_MSK 0x00000003
96#define BATL_PP_00 0x00000000 /* No access */
97#define BATL_PP_01 0x00000001 /* Read-only */
98#define BATL_PP_10 0x00000002 /* Read-write */
99#define BATL_PP_11 0x00000003
100
101#define BATL_PP_NO_ACCESS BATL_PP_00
102#define BATL_PP_RO BATL_PP_01
103#define BATL_PP_RW BATL_PP_10
104
105#ifndef __ASSEMBLY__
106/* cpu ids we detect */
107typedef enum __cpu_t {
108 CPU_740, CPU_750,
109 CPU_740P, CPU_750P,
110 CPU_745, CPU_755,
wdenk3a473b22004-01-03 00:43:19 +0000111 CPU_750CX, CPU_750FX, CPU_750GX,
wdenkbb0f96b2002-02-17 23:48:45 +0000112 CPU_7400,
113 CPU_7410,
Stefan Roese1eac2a72006-11-29 15:42:37 +0100114 CPU_7448,
wdenk3a473b22004-01-03 00:43:19 +0000115 CPU_7450, CPU_7455, CPU_7457,
wdenkbb0f96b2002-02-17 23:48:45 +0000116 CPU_UNKNOWN} cpu_t;
117
118extern cpu_t get_cpu_type(void);
119
120#define l1icache_enable icache_enable
121
122void l2cache_enable(void);
123void l1dcache_enable(void);
124
125static __inline__ unsigned long get_msr (void)
126{
127 unsigned long msr;
128 asm volatile("mfmsr %0" : "=r" (msr) :);
129 return msr;
130}
131
132static __inline__ void set_msr (unsigned long msr)
133{
134 asm volatile("mtmsr %0" : : "r" (msr));
135}
136
137static __inline__ unsigned long get_hid0 (void)
138{
139 unsigned long hid0;
140 asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
141 return hid0;
142}
143
144static __inline__ unsigned long get_hid1 (void)
145{
146 unsigned long hid1;
147 asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
148 return hid1;
149}
150
151static __inline__ void set_hid0 (unsigned long hid0)
152{
153 asm volatile("mtspr 1008, %0" : : "r" (hid0));
154}
155
156static __inline__ void set_hid1 (unsigned long hid1)
157{
158 asm volatile("mtspr 1009, %0" : : "r" (hid1));
159}
160
161#endif /* __ASSEMBLY__ */
162#endif /* __MPC74XX_H__ */