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David Brownell28b00322009-05-15 23:48:37 +02001/*
2 * Copyright (C) 2009 David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#include <common.h>
20#include <nand.h>
21#include <asm/io.h>
22#include <asm/arch/hardware.h>
23#include <asm/arch/emif_defs.h>
24#include <asm/arch/nand_defs.h>
Sughosh Ganud7f9b502010-11-28 20:21:27 -050025#include <asm/arch/davinci_misc.h>
Sandeep Paulrajb3af1d62009-08-10 12:24:40 -040026#include <net.h>
27#include <netdev.h>
Sandeep Paulraj073eacf2010-12-18 18:14:49 -050028#ifdef CONFIG_DAVINCI_MMC
29#include <mmc.h>
30#include <asm/arch/sdmmc_defs.h>
31#endif
David Brownell28b00322009-05-15 23:48:37 +020032
33DECLARE_GLOBAL_DATA_PTR;
34
35/*
36 * With the DM355 EVM, u-boot is *always* a third stage loader,
37 * unless a JTAG debugger handles the first two stages:
38 *
39 * - 1st stage is ROM Boot Loader (RBL), which searches for a
40 * second stage loader in one of three places based on SW7:
41 * NAND (with MMC/SD fallback), MMC/SD, or UART.
42 *
43 * - 2nd stage is User Boot Loader (UBL), using at most 30KB
44 * of on-chip SRAM, responsible for lowlevel init, and for
45 * loading the third stage loader into DRAM.
46 *
47 * - 3rd stage, that's us!
48 */
49
50int board_init(void)
51{
52 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
53 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
54
55 /* We expect the UBL to have handled "lowlevel init", which
56 * involves setting up at least:
57 * - clocks
58 * + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
59 * + clock divisors for those PLLs
60 * + LPSC_DDR module enabled
61 * + LPSC_TIMER0 module (still) enabled
62 * - EMIF
63 * + DDR init and timings
64 * + AEMIF timings (for NAND and DM9000)
65 * - pinmux
66 *
67 * Some of that is repeated here, mostly as a precaution.
68 */
69
70 /* AEMIF: Some "address" lines are available as GPIOs. A3..A13
71 * could be too if we used A12 as a GPIO during NAND chipselect
72 * (and Linux did too), letting us control the LED on A7/GPIO61.
73 */
74 REG(PINMUX2) = 0x0c08;
75
76 /* UART0 may still be in SyncReset if we didn't boot from UART */
77 davinci_enable_uart0();
78
79 /* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
80 lpsc_on(DAVINCI_LPSC_TPCC);
81 lpsc_on(DAVINCI_LPSC_TPTC0);
82 lpsc_on(DAVINCI_LPSC_TPTC1);
83
84 return 0;
85}
86
Sandeep Paulrajb3af1d62009-08-10 12:24:40 -040087#ifdef CONFIG_DRIVER_DM9000
88int board_eth_init(bd_t *bis)
89{
90 return dm9000_initialize(bis);
91}
92#endif
93
David Brownell28b00322009-05-15 23:48:37 +020094#ifdef CONFIG_NAND_DAVINCI
95
96static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
97{
98 struct nand_chip *this = mtd->priv;
Sandeep Paulraj6fe5e872009-10-01 20:21:13 -040099 unsigned long wbase = (unsigned long) this->IO_ADDR_W;
100 unsigned long rbase = (unsigned long) this->IO_ADDR_R;
David Brownell28b00322009-05-15 23:48:37 +0200101
102 if (chip == 1) {
103 __set_bit(14, &wbase);
104 __set_bit(14, &rbase);
105 } else {
106 __clear_bit(14, &wbase);
107 __clear_bit(14, &rbase);
108 }
109 this->IO_ADDR_W = (void *)wbase;
110 this->IO_ADDR_R = (void *)rbase;
111}
112
113int board_nand_init(struct nand_chip *nand)
114{
115 davinci_nand_init(nand);
116 nand->select_chip = nand_dm355evm_select_chip;
117 return 0;
118}
119
120#endif
Sandeep Paulraj073eacf2010-12-18 18:14:49 -0500121
122#ifdef CONFIG_DAVINCI_MMC
123static struct davinci_mmc mmc_sd0 = {
124 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
125 .input_clk = 108000000,
126 .host_caps = MMC_MODE_4BIT,
127 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
128 .version = MMC_CTLR_VERSION_1,
129};
130
131#ifdef CONFIG_DAVINCI_MMC_SD1
132static struct davinci_mmc mmc_sd1 = {
133 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
134 .input_clk = 108000000,
135 .host_caps = MMC_MODE_4BIT,
136 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
137 .version = MMC_CTLR_VERSION_1,
138};
139#endif
140
141int board_mmc_init(bd_t *bis)
142{
143 int err;
144
145 /* Add slot-0 to mmc subsystem */
146 err = davinci_mmc_init(bis, &mmc_sd0);
147 if (err)
148 return err;
149
150#ifdef CONFIG_DAVINCI_MMC_SD1
151 /* Add slot-1 to mmc subsystem */
152 err = davinci_mmc_init(bis, &mmc_sd1);
153#endif
154
155 return err;
156}
157#endif