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wdenk16f21702002-08-26 21:58:50 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <config.h>
26#include <mpc8xx.h>
27
28/*
29 * Memory Controller Using
30 *
31 * CS0 - Flash memory (0x40000000)
32 * CS1 - SDRAM (0x00000000}
33 * CS2 - S/UNI Ultra ATM155
34 * CS3 - IDT 77106 ATM25
35 * CS4 - DSP HPI
36 * CS5 - E1/T1 Interface device
37 * CS6 - PCMCIA device
38 * CS7 - PCMCIA device
39 */
40
41/* ------------------------------------------------------------------------- */
42
43#define _not_used_ 0xffffffff
44
45const uint sdram_table[] = {
46 /* single read. (offset 0 in upm RAM) */
47 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
48 0x1ff77c47,
49
50 /* MRS initialization (offset 5) */
51
52 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
53
54 /* burst read. (offset 8 in upm RAM) */
55 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
56 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
57 _not_used_, _not_used_, _not_used_, _not_used_,
58 _not_used_, _not_used_, _not_used_, _not_used_,
59
60 /* single write. (offset 18 in upm RAM) */
61 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
62 _not_used_, _not_used_, _not_used_, _not_used_,
63
64 /* burst write. (offset 20 in upm RAM) */
65 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
66 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
67 _not_used_, _not_used_, _not_used_, _not_used_,
68 _not_used_, _not_used_, _not_used_, _not_used_,
69
70 /* refresh. (offset 30 in upm RAM) */
71 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
72 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
73 _not_used_, _not_used_, _not_used_, _not_used_,
74
75 /* exception. (offset 3c in upm RAM) */
76 0x7ffffc07, _not_used_, _not_used_, _not_used_
77};
78
79/* ------------------------------------------------------------------------- */
80
81/*
82 * Check Board Identity:
83 */
84
85int checkboard (void)
86{
87 puts ("Board: ICU862 Board\n");
88 return 0;
89}
90
91/* ------------------------------------------------------------------------- */
92
93static long int dram_size (long int, long int *, long int);
94
95/* ------------------------------------------------------------------------- */
96
97long int initdram (int board_type)
98{
99 volatile immap_t *immap = (immap_t *) CFG_IMMR;
100 volatile memctl8xx_t *memctl = &immap->im_memctl;
101 long int size8, size9;
102 long int size_b0 = 0;
103 unsigned long reg;
104
105 upmconfig (UPMA, (uint *) sdram_table,
106 sizeof (sdram_table) / sizeof (uint));
107
108 /*
109 * Preliminary prescaler for refresh (depends on number of
110 * banks): This value is selected for four cycles every 62.4 us
111 * with two SDRAM banks or four cycles every 31.2 us with one
112 * bank. It will be adjusted after memory sizing.
113 */
114 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
115
116 memctl->memc_mar = 0x00000088;
117
118 /*
119 * Map controller bank 1 to the SDRAM bank at
120 * preliminary address - these have to be modified after the
121 * SDRAM size has been determined.
122 */
123 memctl->memc_or1 = CFG_OR1_PRELIM;
124 memctl->memc_br1 = CFG_BR1_PRELIM;
125
126 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
127
128 udelay (200);
129
130 /* perform SDRAM initializsation sequence */
131
132 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
133 udelay (200);
134 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
135 udelay (200);
136
137 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
138
139 udelay (1000);
140
141 /*
142 * Check Bank 0 Memory Size for re-configuration
143 *
144 * try 8 column mode
145 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200146 size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM,
wdenk16f21702002-08-26 21:58:50 +0000147 SDRAM_MAX_SIZE);
148
149 udelay (1000);
150
151 /*
152 * try 9 column mode
153 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200154 size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM,
wdenk16f21702002-08-26 21:58:50 +0000155 SDRAM_MAX_SIZE);
156
157 if (size8 < size9) { /* leave configuration at 9 columns */
158 size_b0 = size9;
159/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
160 } else { /* back to 8 columns */
161 size_b0 = size8;
162 memctl->memc_mamr = CFG_MAMR_8COL;
163 udelay (500);
164/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
165 }
166
167 udelay (1000);
168
169 /*
170 * Adjust refresh rate depending on SDRAM type, both banks
171 * For types > 128 MBit leave it at the current (fast) rate
172 */
173 if ((size_b0 < 0x02000000)) {
174 /* reduce to 15.6 us (62.4 us / quad) */
175 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
176 udelay (1000);
177 }
178
179 /*
180 * Final mapping
181 */
182
183 memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
184 memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
185
186 /* adjust refresh rate depending on SDRAM type, one bank */
187 reg = memctl->memc_mptpr;
188 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
189 memctl->memc_mptpr = reg;
190
191 udelay (10000);
192
193 return (size_b0);
194}
195
196/* ------------------------------------------------------------------------- */
197
198/*
199 * Check memory range for valid RAM. A simple memory test determines
200 * the actually available RAM size between addresses `base' and
201 * `base + maxsize'. Some (not all) hardware errors are detected:
202 * - short between address lines
203 * - short between data lines
204 */
205
206static long int dram_size (long int mamr_value, long int *base,
207 long int maxsize)
208{
209 volatile immap_t *immap = (immap_t *) CFG_IMMR;
210 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk16f21702002-08-26 21:58:50 +0000211
212 memctl->memc_mamr = mamr_value;
213
wdenkc83bf6a2004-01-06 22:38:14 +0000214 return (get_ram_size(base, maxsize));
wdenk16f21702002-08-26 21:58:50 +0000215}