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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +01002/*
3 * Copyright (C) STMicroelectronics SA 2017
4 * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +01005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010010#define CONFIG_MISC_INIT_R
11
12#define CONFIG_SYS_FLASH_BASE 0x08000000
13
14#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010015
16#define CONFIG_SYS_ICACHE_OFF
17#define CONFIG_SYS_DCACHE_OFF
18
19/*
20 * Configuration of the external SDRAM memory
21 */
22#define CONFIG_NR_DRAM_BANKS 1
23#define CONFIG_SYS_RAM_FREQ_DIV 2
24#define CONFIG_SYS_RAM_BASE 0x00000000
25#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
26#define CONFIG_SYS_LOAD_ADDR 0x00400000
27#define CONFIG_LOADADDR 0x00400000
28
29#define CONFIG_SYS_MAX_FLASH_SECT 12
30#define CONFIG_SYS_MAX_FLASH_BANKS 2
31
32#define CONFIG_ENV_OFFSET (256 << 10)
33#define CONFIG_ENV_SECT_SIZE (128 << 10)
34#define CONFIG_ENV_SIZE (8 << 10)
35
36#define CONFIG_STM32_FLASH
37
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010038#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
39#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
40
41#define CONFIG_CMDLINE_TAG
42#define CONFIG_SETUP_MEMORY_TAGS
43#define CONFIG_INITRD_TAG
44#define CONFIG_REVISION_TAG
45
46#define CONFIG_SYS_CBSIZE 1024
47
48#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
49
50#define CONFIG_BOOTCOMMAND \
51 "run boot_sd"
52
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010053#define CONFIG_EXTRA_ENV_SETTINGS \
54 "boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32f469-disco.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
55
56/*
57 * Command line configuration.
58 */
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010059
60#endif /* __CONFIG_H */