blob: e4b83d11dc262ea0c34feb252b0c8c3ab207b94d [file] [log] [blame]
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01001/*
Aubrey.Li3f0606a2007-03-09 13:38:44 +08002 * U-boot - u-boot.lds.S
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01003 *
Mike Frysinger9171fc82008-03-30 15:46:13 -04004 * Copyright (c) 2005-2008 Analog Device Inc.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Aubrey.Li3f0606a2007-03-09 13:38:44 +080028#include <config.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -040029#include <asm/blackfin.h>
30#undef ALIGN
31
32/* If we don't actually load anything into L1 data, this will avoid
33 * a syntax error. If we do actually load something into L1 data,
34 * we'll get a linker memory load error (which is what we'd want).
35 * This is here in the first place so we can quickly test building
36 * for different CPU's which may lack non-cache L1 data.
37 */
38#ifndef L1_DATA_B_SRAM
39# define L1_DATA_B_SRAM CFG_MONITOR_BASE
40# define L1_DATA_B_SRAM_SIZE 0
41#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +080042
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010043OUTPUT_ARCH(bfin)
Mike Frysinger9171fc82008-03-30 15:46:13 -040044
45/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
46MEMORY
47{
48 ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
49 l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
50 l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
51}
52
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010053SECTIONS
54{
Mike Frysinger9171fc82008-03-30 15:46:13 -040055 .text :
56 {
57#ifdef ENV_IS_EMBEDDED
58 /* WARNING - the following is hand-optimized to fit within
59 * the sector before the environment sector. If it throws
60 * an error during compilation remove an object here to get
61 * it linked after the configuration sector.
62 */
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010063
Mike Frysinger9171fc82008-03-30 15:46:13 -040064 cpu/blackfin/start.o (.text)
65 cpu/blackfin/traps.o (.text)
66 cpu/blackfin/interrupt.o (.text)
67 cpu/blackfin/serial.o (.text)
68 common/dlmalloc.o (.text)
69 lib_generic/crc32.o (.text)
70 lib_generic/zlib.o (.text)
71 board/bf533-ezkit/bf533-ezkit.o (.text)
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010072
Mike Frysinger9171fc82008-03-30 15:46:13 -040073 . = DEFINED(env_offset) ? env_offset : .;
74 common/environment.o (.text)
75#endif
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010076
Mike Frysinger9171fc82008-03-30 15:46:13 -040077 *(.text .text.*)
78 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010079
Mike Frysinger9171fc82008-03-30 15:46:13 -040080 .rodata :
81 {
82 . = ALIGN(4);
83 *(.rodata .rodata.*)
84 *(.rodata1)
85 *(.eh_frame)
86 . = ALIGN(4);
87 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010088
Mike Frysinger9171fc82008-03-30 15:46:13 -040089 .data :
90 {
91 . = ALIGN(256);
92 *(.data .data.*)
93 *(.data1)
94 *(.sdata)
95 *(.sdata2)
96 *(.dynamic)
97 CONSTRUCTORS
98 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010099
Mike Frysinger9171fc82008-03-30 15:46:13 -0400100 .u_boot_cmd :
101 {
102 ___u_boot_cmd_start = .;
103 *(.u_boot_cmd)
104 ___u_boot_cmd_end = .;
105 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100106
Mike Frysinger9171fc82008-03-30 15:46:13 -0400107 .text_l1 :
108 {
109 . = ALIGN(4);
110 __stext_l1 = .;
111 *(.l1.text)
112 . = ALIGN(4);
113 __etext_l1 = .;
114 } >l1_code AT>ram
115 __stext_l1_lma = LOADADDR(.text_l1);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100116
Mike Frysinger9171fc82008-03-30 15:46:13 -0400117 .data_l1 :
118 {
119 . = ALIGN(4);
120 __sdata_l1 = .;
121 *(.l1.data)
122 *(.l1.bss)
123 . = ALIGN(4);
124 __edata_l1 = .;
125 } >l1_data AT>ram
126 __sdata_l1_lma = LOADADDR(.data_l1);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100127
Mike Frysinger9171fc82008-03-30 15:46:13 -0400128 .bss :
129 {
130 . = ALIGN(4);
131 __bss_start = .;
132 *(.sbss) *(.scommon)
133 *(.dynbss)
134 *(.bss .bss.*)
135 *(COMMON)
136 __bss_end = .;
137 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100138}