blob: 80dad07d84eed751905341cf6a2833b215b288c8 [file] [log] [blame]
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +01001/*
2 * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
3 *
4 * Watchdog driver for Atmel AT91SAM9x processors.
5 *
6 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15/*
16 * The Watchdog Timer Mode Register can be only written to once. If the
17 * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
18 * write to this register. Inform Linux to it too
19 */
20
21#include <common.h>
22#include <watchdog.h>
23#include <asm/arch/hardware.h>
Reinhard Meyer7f6ed7f2011-02-04 20:17:33 +010024#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010025#include <asm/arch/at91_wdt.h>
26
27/*
28 * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
29 * use this to convert a watchdog
30 * value from/to milliseconds.
31 */
32#define ms_to_ticks(t) (((t << 8) / 1000) - 1)
33#define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
34
35/* Hardware timeout in seconds */
36#define WDT_HW_TIMEOUT 2
37
38/*
39 * Set the watchdog time interval in 1/256Hz (write-once)
40 * Counter is 12 bit.
41 */
42static int at91_wdt_settimeout(unsigned int timeout)
43{
44 unsigned int reg;
Reinhard Meyer372f2782010-11-03 15:47:20 +010045 at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010046
47 /* Check if disabled */
Achim Ehrlichf936aa02010-03-17 14:50:29 +010048 if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) {
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010049 printf("sorry, watchdog is disabled\n");
50 return -1;
51 }
52
53 /*
54 * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
55 *
56 * Since WDV is a 12-bit counter, the maximum period is
57 * 4096 / 256 = 16 seconds.
58 */
Achim Ehrlichf936aa02010-03-17 14:50:29 +010059
60 reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
61 | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
62 | AT91_WDT_MR_WDD(0xfff) /* restart at any time */
63 | AT91_WDT_MR_WDV(timeout); /* timer value */
64
65 writel(reg, &wd->mr);
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010066
67 return 0;
68}
69
70void hw_watchdog_reset(void)
71{
Reinhard Meyer372f2782010-11-03 15:47:20 +010072 at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
Achim Ehrlichf936aa02010-03-17 14:50:29 +010073 writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr);
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010074}
75
76void hw_watchdog_init(void)
77{
78 /* 16 seconds timer, resets enabled */
79 at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
80}