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Aubrey Li26bf7de2007-03-19 01:24:52 +08001/*
2 * U-boot - Configuration file for BF537 STAMP board
3 */
4
5#ifndef __CONFIG_BF537_H__
6#define __CONFIG_BF537_H__
7
8#define CFG_LONGHELP 1
9#define CONFIG_CMDLINE_EDITING 1
10#define CONFIG_BAUDRATE 57600
11/* Set default serial console for bf537 */
12#define CONFIG_UART_CONSOLE 0
13#define CONFIG_BF537 1
14#define CONFIG_BOOTDELAY 5
15/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
16/*#define CONFIG_BF537_STAMP_LEDCMD 1*/
17
18/*
19 * Boot Mode Set
20 * Blackfin can support several boot modes
21 */
22#define BF537_BYPASS_BOOT 0x0011 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
23#define BF537_PARA_BOOT 0x0012 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
24#define BF537_SPI_MASTER_BOOT 0x0014 /* Bootmode 3: SPI master mode boot from SPI flash */
25#define BF537_SPI_SLAVE_BOOT 0x0015 /* Bootmode 4: SPI slave mode boot from SPI flash */
26#define BF537_TWI_MASTER_BOOT 0x0016 /* Bootmode 5: TWI master mode boot from EEPROM */
27#define BF537_TWI_SLAVE_BOOT 0x0017 /* Bootmode 6: TWI slave mode boot from EEPROM */
28#define BF537_UART_BOOT 0x0018 /* Bootmode 7: UART slave mdoe boot via UART host */
29/* Define the boot mode */
30#define BFIN_BOOT_MODE BF537_BYPASS_BOOT
31
32#define CONFIG_PANIC_HANG 1
33
34#define ADSP_BF534 0x34
35#define ADSP_BF536 0x36
36#define ADSP_BF537 0x37
37#define BFIN_CPU ADSP_BF537
38
39/* This sets the default state of the cache on U-Boot's boot */
40#define CONFIG_ICACHE_ON
41#define CONFIG_DCACHE_ON
42
43/* Define if want to do post memory test */
44#undef CONFIG_POST_TEST
45
46/* Define where the uboot will be loaded by on-chip boot rom */
47#define APP_ENTRY 0x00001000
48
49#define CONFIG_RTC_BFIN 1
50#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
51
52/* CONFIG_CLKIN_HZ is any value in Hz */
53#define CONFIG_CLKIN_HZ 25000000
54/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
55/* 1=CLKIN/2 */
56#define CONFIG_CLKIN_HALF 0
57/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
58/* 1=bypass PLL*/
59#define CONFIG_PLL_BYPASS 0
60/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
61/* Values can range from 1-64 */
62#define CONFIG_VCO_MULT 20
63/* CONFIG_CCLK_DIV controls what the core clock divider is */
64/* Values can be 1, 2, 4, or 8 ONLY */
65#define CONFIG_CCLK_DIV 1
66/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
67/* Values can range from 1-15 */
68#define CONFIG_SCLK_DIV 5
69/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
70/* Values can range from 2-65535 */
71/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
72#define CONFIG_SPI_BAUD 2
73#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
74#define CONFIG_SPI_BAUD_INITBLOCK 4
75#endif
76
77#if ( CONFIG_CLKIN_HALF == 0 )
78#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
79#else
80#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
81#endif
82
83#if (CONFIG_PLL_BYPASS == 0)
84#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
85#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
86#else
87#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
88#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
89#endif
90
91#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
92#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
93#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
94#else
95#undef CONFIG_SPI_FLASH_FAST_READ
96#endif
97#endif
98
99#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
100#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
101#define CONFIG_MEM_MT48LC32M8A2_75 1
102
103#define CONFIG_LOADS_ECHO 1
104
105/*
106 * rarpb, bootp or dhcp commands will perform only a
107 * configuration lookup from the BOOTP/DHCP server
108 * but not try to load any image using TFTP
109 */
110#define CFG_AUTOLOAD "no"
111
112/*
113 * Network Settings
114 */
115/* network support */
116#if (BFIN_CPU != ADSP_BF534)
117#define CONFIG_IPADDR 192.168.0.15
118#define CONFIG_NETMASK 255.255.255.0
119#define CONFIG_GATEWAYIP 192.168.0.1
120#define CONFIG_SERVERIP 192.168.0.2
121#define CONFIG_HOSTNAME BF537
122#endif
123
124#define CONFIG_ROOTPATH /romfs
125/* Uncomment next line to use fixed MAC address */
126/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
127/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
128
129#define CFG_LONGHELP 1
130#define CONFIG_BOOTDELAY 5
131#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
132#define CONFIG_BOOTCOMMAND "run ramboot"
133
134#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
135/* POST support */
136#define CONFIG_POST ( CFG_POST_MEMORY | \
137 CFG_POST_UART | \
138 CFG_POST_FLASH | \
139 CFG_POST_ETHER | \
140 CFG_POST_LED | \
141 CFG_POST_BUTTON)
142#else
143#undef CONFIG_POST
144#endif
145
146#ifdef CONFIG_POST
Aubrey Li26bf7de2007-03-19 01:24:52 +0800147#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
148#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800149#endif
150
151/* CF-CARD IDE-HDD Support */
152
153/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
154/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
155/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
156
157#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
158# define CONFIG_BFIN_IDE 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800159#endif
160
161/*#define CONFIG_BF537_NAND */ /* Add nand flash support */
162
Aubrey Li26bf7de2007-03-19 01:24:52 +0800163#define CONFIG_NETCONSOLE 1
164#define CONFIG_NET_MULTI 1
165
Jon Loeligerba2351f2007-07-04 22:31:49 -0500166/*
167 * Command line configuration.
168 */
169#include <config_cmd_default.h>
170
171#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
172
173#define CONFIG_CMD_ELF
174#define CONFIG_CMD_I2C
175#define CONFIG_CMD_CACHE
176#define CONFIG_CMD_JFFS2
177#define CONFIG_CMD_EEPROM
178#define CONFIG_CMD_DATE
179
Aubrey Li26bf7de2007-03-19 01:24:52 +0800180#if (BFIN_CPU == ADSP_BF534)
Jon Loeligerba2351f2007-07-04 22:31:49 -0500181#undef CONFIG_CMD_NET
Aubrey Li26bf7de2007-03-19 01:24:52 +0800182#else
Jon Loeligerba2351f2007-07-04 22:31:49 -0500183#define CONFIG_CMD_PING
Aubrey Li26bf7de2007-03-19 01:24:52 +0800184#endif
185
Jon Loeligerba2351f2007-07-04 22:31:49 -0500186#if defined(CONFIG_BFIN_CF_IDE) \
187 || defined(CONFIG_BFIN_HDD_IDE) \
188 || defined(CONFIG_BFIN_TRUE_IDE)
189#define CONFIG_CMD_IDE
Aubrey Li26bf7de2007-03-19 01:24:52 +0800190#endif
191
Jon Loeligerba2351f2007-07-04 22:31:49 -0500192#endif
193
Jon Loeligerba2351f2007-07-04 22:31:49 -0500194#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
195
196#define CONFIG_CMD_DHCP
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500197
198#if defined(CONFIG_POST)
199#define CONFIG_CMD_DIAG
200#endif
Jon Loeligerba2351f2007-07-04 22:31:49 -0500201
202#ifdef CONFIG_BF537_NAND
203#define CONFIG_CMD_NAND
204#endif
205
206#endif
207
208
Aubrey Li26bf7de2007-03-19 01:24:52 +0800209#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
210#define CONFIG_LOADADDR 0x1000000
211
212#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
213#if (BFIN_CPU != ADSP_BF534)
214#define CONFIG_EXTRA_ENV_SETTINGS \
215 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
216 "nfsargs=setenv bootargs root=/dev/nfs rw " \
217 "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
218 "addip=setenv bootargs $(bootargs) " \
219 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
220 ":$(hostname):eth0:off\0" \
221 "ramboot=tftpboot $(loadaddr) linux;" \
222 "run ramargs;run addip;bootelf\0" \
223 "nfsboot=tftpboot $(loadaddr) linux;" \
224 "run nfsargs;run addip;bootelf\0" \
225 "flashboot=bootm 0x20100000\0" \
226 "update=tftpboot $(loadaddr) u-boot.bin;" \
227 "protect off 0x20000000 0x2007FFFF;" \
228 "erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
229 ""
230#else
231#define CONFIG_EXTRA_ENV_SETTINGS \
232 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
233 "flashboot=bootm 0x20100000\0" \
234 ""
235#endif
236#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
237#if (BFIN_CPU != ADSP_BF534)
238#define CONFIG_EXTRA_ENV_SETTINGS \
239 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
240 "nfsargs=setenv bootargs root=/dev/nfs rw " \
241 "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
242 "addip=setenv bootargs $(bootargs) " \
243 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
244 ":$(hostname):eth0:off\0" \
245 "ramboot=tftpboot $(loadaddr) linux;" \
246 "run ramargs;run addip;bootelf\0" \
247 "nfsboot=tftpboot $(loadaddr) linux;" \
248 "run nfsargs;run addip;bootelf\0" \
249 "flashboot=bootm 0x20100000\0" \
250 "update=tftpboot $(loadaddr) u-boot.ldr;" \
251 "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
252 ""
253#else
254#define CONFIG_EXTRA_ENV_SETTINGS \
255 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
256 "flashboot=bootm 0x20100000\0" \
257 ""
258#endif
259#endif
260
Aubrey Li26bf7de2007-03-19 01:24:52 +0800261#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
262#if (BFIN_CPU == ADSP_BF534)
263#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */
264#elif (BFIN_CPU == ADSP_BF536)
265#define CFG_PROMPT "serial_bf536> " /* Monitor Command Prompt */
266#else
267#define CFG_PROMPT "serial_bf537> " /* Monitor Command Prompt */
268#endif
269#else
270#if (BFIN_CPU == ADSP_BF534)
271#define CFG_PROMPT "bf534> " /* Monitor Command Prompt */
272#elif (BFIN_CPU == ADSP_BF536)
273#define CFG_PROMPT "bf536> " /* Monitor Command Prompt */
274#else
275#define CFG_PROMPT "bf537> " /* Monitor Command Prompt */
276#endif
277#endif
278
Jon Loeligerba2351f2007-07-04 22:31:49 -0500279#if defined(CONFIG_CMD_KGDB)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800280#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
281#else
282#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
283#endif
284#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
285#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
286#define CFG_MAXARGS 16 /* max number of command args */
287#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
288#define CFG_MEMTEST_START 0x0 /* memtest works on */
289#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
290#define CFG_LOAD_ADDR CONFIG_LOADADDR /* default load address */
291#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
292#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
293#define CFG_SDRAM_BASE 0x00000000
294
295#define CFG_FLASH_BASE 0x20000000
296
297#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
298#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
299#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
300#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
301#define CFG_GBL_DATA_SIZE 0x4000
302#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
303#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
304
305#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
306#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
307#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
308
309#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
310/* for bf537-stamp, usrt boot mode still store env in flash */
311#define CFG_ENV_IS_IN_FLASH 1
312#define CFG_ENV_ADDR 0x20004000
313#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
314#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
315#define CFG_ENV_IS_IN_EEPROM 1
316#define CFG_ENV_OFFSET 0x4000
317#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
318#endif
319#define CFG_ENV_SIZE 0x2000
320#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
321/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
322#define ENV_IS_EMBEDDED
323/* #endif */
324
325/* JFFS Partition offset set */
326#define CFG_JFFS2_FIRST_BANK 0
327#define CFG_JFFS2_NUM_BANKS 1
328/* 512k reserved for u-boot */
329#define CFG_JFFS2_FIRST_SECTOR 15
330
331#define CONFIG_SPI
332
333/*
334 * Stack sizes
335 */
336#define CONFIG_STACKSIZE (128*1024) /* regular stack */
337
338#define POLL_MODE 1
339#define FLASH_TOT_SECT 71
340#define FLASH_SIZE 0x400000
341#define CFG_FLASH_SIZE 0x400000
342
343/*
344 * Board NAND Infomation
345 */
346
347#define CFG_NAND_ADDR 0x20212000
348#define CFG_NAND_BASE CFG_NAND_ADDR
349#define CFG_MAX_NAND_DEVICE 1
350#define SECTORSIZE 512
351#define ADDR_COLUMN 1
352#define ADDR_PAGE 2
353#define ADDR_COLUMN_PAGE 3
354#define NAND_ChipID_UNKNOWN 0x00
355#define NAND_MAX_FLOORS 1
356#define NAND_MAX_CHIPS 1
357#define BFIN_NAND_READY PF3
358
359#define NAND_WAIT_READY(nand) \
360 do { \
361 int timeout = 0; \
362 while(!(*pPORTFIO & PF3)) \
363 if (timeout++ > 100000) \
364 break; \
365 } while (0)
366
367#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
368#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
369
370#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
371#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
372#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
373#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
374
375/*
376 * Initialize PSD4256 registers for using I2C
377 */
378#define CONFIG_MISC_INIT_R
379
380#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
381
382/*
383 * I2C settings
384 * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
385 */
386/* #define CONFIG_SOFT_I2C 1*/ /* I2C bit-banged */
387#define CONFIG_HARD_I2C 1 /* I2C TWI */
388#if defined CONFIG_HARD_I2C
389#define CONFIG_TWICLK_KHZ 50
390#endif
391
392#if defined CONFIG_SOFT_I2C
393/*
394 * Software (bit-bang) I2C driver configuration
395 */
396#define PF_SCL PF0
397#define PF_SDA PF1
398
399#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
400#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
401#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
402#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
403#define I2C_SDA(bit) if(bit) { \
404 *pFIO_FLAG_S = PF_SDA; \
405 asm("ssync;"); \
406 } \
407 else { \
408 *pFIO_FLAG_C = PF_SDA; \
409 asm("ssync;"); \
410 }
411#define I2C_SCL(bit) if(bit) { \
412 *pFIO_FLAG_S = PF_SCL; \
413 asm("ssync;"); \
414 } \
415 else { \
416 *pFIO_FLAG_C = PF_SCL; \
417 asm("ssync;"); \
418 }
419#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
420#endif
421
422#define CFG_I2C_SPEED 50000
423#define CFG_I2C_SLAVE 0xFE
424
425/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
426/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
427#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
428 ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
429#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
430 B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
431*/
432
433#define AMGCTLVAL 0xFF
434#define AMBCTL0VAL 0x7BB07BB0
435#define AMBCTL1VAL 0xFFC27BB0
436
437#define CONFIG_VDSP 1
438
439#ifdef CONFIG_VDSP
440#define ET_EXEC_VDSP 0x8
441#define SHT_STRTAB_VDSP 0x1
442#define ELFSHDRSIZE_VDSP 0x2C
443#define VDSP_ENTRY_ADDR 0xFFA00000
444#endif
445
446#if defined(CONFIG_BFIN_IDE)
447
448#define CONFIG_DOS_PARTITION 1
449/*
450 * IDE/ATA stuff
451 */
452#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
453#undef CONFIG_IDE_LED /* no led for ide supported */
454#undef CONFIG_IDE_RESET /* no reset for ide supported */
455
456#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
457#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
458
459#undef AMBCTL1VAL
460#define AMBCTL1VAL 0xFFC3FFC3
461
462#define CONFIG_CF_ATASEL_DIS 0x20311800
463#define CONFIG_CF_ATASEL_ENA 0x20311802
464
465#if defined(CONFIG_BFIN_TRUE_IDE)
466/*
467 * Note that these settings aren't for the most part used in include/ata.h
468 * when all of the ATA registers are setup
469 */
470#define CFG_ATA_BASE_ADDR 0x2031C000
471#define CFG_ATA_IDE0_OFFSET 0x0000
472#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
473#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
474#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
475#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
476#endif /* CONFIG_BFIN_TRUE_IDE */
477
478#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
479#define CFG_ATA_BASE_ADDR 0x20211800
480#define CFG_ATA_IDE0_OFFSET 0x0000
481#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
482#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
483#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
484#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
485#endif /* CONFIG_BFIN_CF_IDE */
486
487#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
488#define CFG_ATA_BASE_ADDR 0x20314000
489#define CFG_ATA_IDE0_OFFSET 0x0000
490#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
491#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
492#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
493#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
494
495#undef CONFIG_SCLK_DIV
496#define CONFIG_SCLK_DIV 8
497#endif /* CONFIG_BFIN_HDD_IDE */
498
499#endif /*CONFIG_BFIN_IDE */
500
501#endif