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Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR X11
Shaohui Xie126fe702016-09-07 17:56:14 +08002/*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright (C) 2016, Freescale Semiconductor
6 *
7 * Mingkai Hu <Mingkai.hu@nxp.com>
Shaohui Xie126fe702016-09-07 17:56:14 +08008 */
9
10/include/ "fsl-ls1046a.dtsi"
11
12/ {
13 model = "LS1046A QDS Board";
14 aliases {
15 spi0 = &qspi;
16 spi1 = &dspi0;
17 };
18};
19
20&dspi0 {
21 bus-num = <0>;
22 status = "okay";
23
24 dflash0: n25q128a {
25 #address-cells = <1>;
26 #size-cells = <1>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +000027 compatible = "jedec,spi-nor";
Shaohui Xie126fe702016-09-07 17:56:14 +080028 spi-max-frequency = <1000000>; /* input clock */
29 spi-cpol;
30 spi-cpha;
31 reg = <0>;
32 };
33
34 dflash1: sst25wf040b {
35 #address-cells = <1>;
36 #size-cells = <1>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +000037 compatible = "jedec,spi-nor";
Shaohui Xie126fe702016-09-07 17:56:14 +080038 spi-max-frequency = <3500000>;
39 spi-cpol;
40 spi-cpha;
41 reg = <1>;
42 };
43
44 dflash2: en25s64 {
45 #address-cells = <1>;
46 #size-cells = <1>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +000047 compatible = "jedec,spi-nor";
Shaohui Xie126fe702016-09-07 17:56:14 +080048 spi-max-frequency = <3500000>;
49 spi-cpol;
50 spi-cpha;
51 reg = <2>;
52 };
53};
54
55&qspi {
56 bus-num = <0>;
57 status = "okay";
58
59 qflash0: s25fl128s@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +000062 compatible = "jedec,spi-nor";
Shaohui Xie126fe702016-09-07 17:56:14 +080063 spi-max-frequency = <20000000>;
64 reg = <0>;
65 };
66};
67
68&duart0 {
69 status = "okay";
70};
71
72&duart1 {
73 status = "okay";
74};
Shaohui Xiefdc2b542016-10-28 14:24:02 +080075
76&lpuart0 {
77 status = "okay";
78};
Peng Ma539e0cb2018-10-11 10:34:20 +000079
80&sata {
81 status = "okay";
82};