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Jon Smirlc9969942009-06-14 18:21:28 -04001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Jon Smirlc9969942009-06-14 18:21:28 -040012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
18
19/*-----------------------------------------------------------------------------
20High Level Configuration Options
21(easy to change)
22-----------------------------------------------------------------------------*/
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090023#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Jon Smirlc9969942009-06-14 18:21:28 -040024#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
25#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
26 /* FEC configuration and IDE */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027
28/*
29 * Valid values for CONFIG_SYS_TEXT_BASE are:
30 * 0xFFF00000 boot high (standard configuration)
31 * 0xFF000000 boot low
32 * 0x00100000 boot from RAM (for testing only)
33 */
34#ifndef CONFIG_SYS_TEXT_BASE
35#define CONFIG_SYS_TEXT_BASE 0xFFF00000
36#endif
37
Jon Smirlc9969942009-06-14 18:21:28 -040038#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jon Smirlc9969942009-06-14 18:21:28 -040039
40/*-----------------------------------------------------------------------------
41Serial console configuration
42-----------------------------------------------------------------------------*/
43#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
44 /*define gps port conf. */
45 /* register later on to */
46 /*enable UART function! */
Jon Smirlc9969942009-06-14 18:21:28 -040047#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
48
49/*
50 * Command line configuration.
51 */
Jon Smirlc9969942009-06-14 18:21:28 -040052#define CONFIG_CMD_JFFS2
Jon Smirlc9969942009-06-14 18:21:28 -040053#define CONFIG_CMD_PCI
54
55#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
56
Wolfgang Denk14d0a022010-10-07 21:51:12 +020057#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
Jon Smirlc9969942009-06-14 18:21:28 -040058#define CONFIG_SYS_LOWBOOT 1
59#endif
60/* RAMBOOT will be defined automatically in memory section */
61
62#define CONFIG_JFFS2_CMDLINE
63#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
64#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
65 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
66
Jon Smirlc9969942009-06-14 18:21:28 -040067#undef CONFIG_BOOTARGS
68
Jon Smirlc9969942009-06-14 18:21:28 -040069#define CONFIG_PREBOOT "echo;" \
70 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
71 "mount root filesystem over NFS;" \
72 "echo"
73
74#define CONFIG_EXTRA_ENV_SETTINGS \
75 "netdev=eth0\0" \
76 "uimage=uImage-pcm030\0" \
77 "oftree=oftree-pcm030.dtb\0" \
78 "jffs2=root-pcm030.jffs2\0" \
79 "uboot=u-boot-pcm030.bin\0" \
80 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
81 " $(mtdparts) rw\0" \
82 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
83 " rootfstype=jffs2\0" \
84 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
85 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
86 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
87 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
88 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
89 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
90 "0xfff40000\0" \
91 " cp.b 0x400000 0xff040000 $(filesize)\0" \
92 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
93 "cp.b 0x400000 0xff200000 $(filesize)\0" \
94 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
95 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
96 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
97 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
98 "unlock=yes\0" \
99 ""
100
101#define CONFIG_BOOTCOMMAND "run bcmd_flash"
102
103/*--------------------------------------------------------------------------
104IPB Bus clocking configuration.
105 ---------------------------------------------------------------------------*/
106#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
107
108/*-------------------------------------------------------------------------
109 * PCI Mapping:
110 * 0x40000000 - 0x4fffffff - PCI Memory
111 * 0x50000000 - 0x50ffffff - PCI IO Space
112 * -----------------------------------------------------------------------*/
Jon Smirlc9969942009-06-14 18:21:28 -0400113#define CONFIG_PCI_SCAN_SHOW 1
114#define CONFIG_PCI_MEM_BUS 0x40000000
115#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
116#define CONFIG_PCI_MEM_SIZE 0x10000000
117#define CONFIG_PCI_IO_BUS 0x50000000
118#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
119#define CONFIG_PCI_IO_SIZE 0x01000000
120#define CONFIG_SYS_XLB_PIPELINING 1
121
122/*---------------------------------------------------------------------------
Jon Smirlc9969942009-06-14 18:21:28 -0400123 Flash configuration
124---------------------------------------------------------------------------*/
125
126#define CONFIG_SYS_FLASH_BASE 0xff000000
127#define CONFIG_SYS_FLASH_SIZE 0x01000000
128#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
129
130#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
131#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
132#define CONFIG_SYS_FLASH_EMPTY_INFO
133#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
134#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
135 /* (= chip selects) */
136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
137
138/*
139 * Use also hardware protection. This seems required, as the BDI uses
140 * hardware protection. Without this, U-Boot can't work with this sectors,
141 * as its protection is software only by default
142 */
143#define CONFIG_SYS_FLASH_PROTECTION 1
144
145/*---------------------------------------------------------------------------
146 Environment settings
147---------------------------------------------------------------------------*/
148
Simon Glasseb5ba3a2017-05-12 21:09:49 -0600149#define CONFIG_ENV_IS_NOWHERE
Jon Smirlc9969942009-06-14 18:21:28 -0400150#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
151 /*beginning of the EEPROM */
Simon Glasseb5ba3a2017-05-12 21:09:49 -0600152#define CONFIG_ENV_SIZE 2048
Jon Smirlc9969942009-06-14 18:21:28 -0400153
154#define CONFIG_ENV_OVERWRITE 1
155
156/*-----------------------------------------------------------------------------
157 Memory map
158-----------------------------------------------------------------------------*/
159#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
160 /* bootloader or debugger config */
161#define CONFIG_SYS_SDRAM_BASE 0x00000000
162#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
163/* Use SRAM until RAM will be available */
164#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200165#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
Jon Smirlc9969942009-06-14 18:21:28 -0400166 /* area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200167#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200168 GENERATED_GBL_DATA_SIZE)
Jon Smirlc9969942009-06-14 18:21:28 -0400169#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
170
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jon Smirlc9969942009-06-14 18:21:28 -0400172#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
173# define CONFIG_SYS_RAMBOOT 1
174#endif
175
176#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
177#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
178#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
179
180/*-----------------------------------------------------------------------------
181 Ethernet configuration
182-----------------------------------------------------------------------------*/
183#define CONFIG_MPC5xxx_FEC 1
184#define CONFIG_MPC5xxx_FEC_MII100
185#define CONFIG_PHY_ADDR 0x01
186
187/*---------------------------------------------------------------------------
188 GPIO configuration
189 ---------------------------------------------------------------------------*/
190
191/* GPIO port configuration
192 *
193 * Pin mapping:
194 *
195 * [29:31] = 01x
196 * PSC1_0 -> AC97 SDATA out
197 * PSC1_1 -> AC97 SDTA in
198 * PSC1_2 -> AC97 SYNC out
199 * PSC1_3 -> AC97 bitclock out
200 * PSC1_4 -> AC97 reset out
201 *
202 * [25:27] = 001
203 * PSC2_0 -> CAN 1 Tx out
204 * PSC2_1 -> CAN 1 Rx in
205 * PSC2_2 -> CAN 2 Tx out
206 * PSC2_3 -> CAN 2 Rx in
207 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
208 *
209 *
210 * [20:23] = 1100
211 * PSC3_0 -> UART Tx out
212 * PSC3_1 -> UART Rx in
213 * PSC3_2 -> UART RTS (in/out FIXME)
214 * PSC3_3 -> UART CTS (in/out FIXME)
215 * PSC3_4 -> LocalPlus Bus CS6 \
216 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
217 * PSC3_6 -> dedicated SPI MOSI out (master case)
218 * PSC3_7 -> dedicated SPI MISO in (master case)
219 * PSC3_8 -> dedicated SPI SS out (master case)
220 * PSC3_9 -> dedicated SPI CLK out (master case)
221 *
222 * [18:19] = 01
223 * USB_0 -> USB OE out
224 * USB_1 -> USB Tx- out
225 * USB_2 -> USB Tx+ out
226 * USB_3 -> USB RxD (in/out FIXME)
227 * USB_4 -> USB Rx+ in
228 * USB_5 -> USB Rx- in
229 * USB_6 -> USB PortPower out
230 * USB_7 -> USB speed out
231 * USB_8 -> USB suspend (in/out FIXME)
232 * USB_9 -> USB overcurrent in
233 *
234 * [17] = 0
235 * USB differential mode
236 *
237 * [16] = 0
238 * PCI enabled
239 *
240 * [12:15] = 0101
241 * ETH_0 -> ETH Txen
242 * ETH_1 -> ETH TxD0
243 * ETH_2 -> ETH TxD1
244 * ETH_3 -> ETH TxD2
245 * ETH_4 -> ETH TxD3
246 * ETH_5 -> ETH Txerr
247 * ETH_6 -> ETH MDC
248 * ETH_7 -> ETH MDIO
249 * ETH_8 -> ETH RxDv
250 * ETH_9 -> ETH RxCLK
251 * ETH_10 -> ETH Collision
252 * ETH_11 -> ETH TxD
253 * ETH_12 -> ETH RxD0
254 * ETH_13 -> ETH RxD1
255 * ETH_14 -> ETH RxD2
256 * ETH_15 -> ETH RxD3
257 * ETH_16 -> ETH Rxerr
258 * ETH_17 -> ETH CRS
259 *
260 * [9:11] = 101
261 * PSC6_0 -> UART RxD in
262 * PSC6_1 -> UART CTS (in/out FIXME)
263 * PSC6_2 -> UART TxD out
264 * PSC6_3 -> UART RTS (in/out FIXME)
265 *
266 * [2:3/6:7] = 00/11
267 * TMR_0 -> ATA_CS0 out
268 * TMR_1 -> ATA_CS1 out
269 * TMR_2 -> GPIO
270 * TMR_3 -> GPIO
271 * TMR_4 -> GPIO
272 * TMR_5 -> GPIO
273 * TMR_6 -> GPIO
274 * TMR_7 -> GPIO
275 * I2C_0 -> I2C 1 Clock out
276 * I2C_1 -> I2C 1 IO in/out
277 * I2C_2 -> I2C 2 Clock out
278 * I2C_3 -> I2C 2 IO in/out
279 *
280 * [4] = 1
281 * PSC3_5 is used as CS7
282 *
283 * [5] = 1
284 * PSC3_4 is used as CS6
285 *
286 * [1] = 0
287 * gpio_wkup_7 is GPIO
288 *
289 * [0] = 0
290 * gpio_wkup_6 is GPIO
291 *
292 */
293#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
294
295/*-----------------------------------------------------------------------------
296 Miscellaneous configurable options
297-------------------------------------------------------------------------------*/
298#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Smirlc9969942009-06-14 18:21:28 -0400299
300#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
301
302#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
303#if defined(CONFIG_CMD_KGDB)
304#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
305#endif
306
307#if defined(CONFIG_CMD_KGDB)
308#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
309#else
310#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
311#endif
312#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
313 /* Print Buffer Size */
314#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
315#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
316
317#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
318#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
319
320#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
Jon Smirlc9969942009-06-14 18:21:28 -0400321
Jon Smirlc9969942009-06-14 18:21:28 -0400322/*-----------------------------------------------------------------------------
323 Various low-level settings
324-----------------------------------------------------------------------------*/
325#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
326#define CONFIG_SYS_HID0_FINAL HID0_ICE
327
328/* no burst access on the LPB */
329#define CONFIG_SYS_CS_BURST 0x00000000
330/* one deadcycle for the 33MHz statemachine */
331#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
332/* one additional waitstate for the 33MHz statemachine */
333#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
334#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
335#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
336
337#define CONFIG_SYS_RESET_ADDRESS 0xff000000
338
339/*-----------------------------------------------------------------------
340 * USB stuff
341 *-----------------------------------------------------------------------
342 */
343#define CONFIG_USB_CLOCK 0x0001BBBB
344#define CONFIG_USB_CONFIG 0x00001000
345
346/*---------------------------------------------------------------------------
347 IDE/ATA stuff Supports IDE harddisk
348----------------------------------------------------------------------------*/
349
350#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
351#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
352#undef CONFIG_IDE_LED /* LED for ide not supported */
353#define CONFIG_SYS_ATA_CS_ON_TIMER01
354#define CONFIG_IDE_RESET 1 /* reset for ide supported */
355#define CONFIG_IDE_PREINIT
356#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
357#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
358#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
359#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
360/* Offset for data I/O */
361#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
362/* Offset for normal register accesses */
363#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
364/* Offset for alternate registers */
365#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
366/* Interval between registers */
367#define CONFIG_SYS_ATA_STRIDE 4
368#define CONFIG_ATAPI 1
369
Jon Smirlc9969942009-06-14 18:21:28 -0400370/* USB */
371#define CONFIG_USB_OHCI
Jon Smirlc9969942009-06-14 18:21:28 -0400372
373/* pass open firmware flat tree */
Jon Smirlc9969942009-06-14 18:21:28 -0400374#define OF_CPU "PowerPC,5200@0"
375#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
376#define OF_SOC "soc5200@f0000000"
377#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
378
379#endif /* __CONFIG_H */