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wdenkd1cbe852003-06-28 17:24:46 +00001/*----------------------------------------------------------------------+
Josh Boyer31773492009-08-07 13:53:20 -04002 * This source code is dual-licensed. You may use it under the terms of
3 * the GNU General Public License version 2, or under the license below.
wdenkd1cbe852003-06-28 17:24:46 +00004 *
5 * This source code has been made available to you by IBM on an AS-IS
6 * basis. Anyone receiving this source is licensed under IBM
7 * copyrights to use it in any way he or she deems fit, including
8 * copying it, modifying it, compiling it, and redistributing it either
9 * with or without modifications. No license under IBM patents or
10 * patent applications is to be implied by the copyright license.
11 *
12 * Any user of this software should understand that IBM cannot provide
13 * technical support for this software and will not be responsible for
14 * any consequences resulting from the use of this software.
15 *
16 * Any person who transfers this source code or any derivative work
17 * must include the IBM copyright notice, this paragraph, and the
18 * preceding two paragraphs in the transferred software.
19 *
20 * COPYRIGHT I B M CORPORATION 1995
21 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 *-----------------------------------------------------------------------
23 */
24
25#include <config.h>
26#include <ppc4xx.h>
27#include "config.h"
28
29#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
30#define FPGA_BRDC 0xF0300004
31
32#include <ppc_asm.tmpl>
33#include <ppc_defs.h>
34
35#include <asm/cache.h>
36#include <asm/mmu.h>
37
38#include "exbitgen.h"
wdenk945af8d2003-07-16 21:53:01 +000039
wdenkd1cbe852003-06-28 17:24:46 +000040/* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
41/* c-code declarations and consequently can't be included here). */
42/* (Possibly to be solved somehow else). */
43/*--------------------------------------------------------------------- */
44#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500
45#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
46#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
47#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
48#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
49#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
50#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
51#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
52#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
53#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
54#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
55#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
56#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
57#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
58#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
59#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
60
61/* MDCNTL Register Bit definition */
62#define IIC_MDCNTL_HSCL 0x01
63#define IIC_MDCNTL_EUBS 0x02
64#define IIC_MDCNTL_FMDB 0x40
65#define IIC_MDCNTL_FSDB 0x80
66
67/* CNTL Register Bit definition */
68#define IIC_CNTL_PT 0x01
69#define IIC_CNTL_READ 0x02
70#define IIC_CNTL_CHT 0x04
71
72/* STS Register Bit definition */
73#define IIC_STS_PT 0X01
74#define IIC_STS_ERR 0X04
75#define IIC_STS_MDBS 0X20
76
77/* EXTSTS Register Bit definition */
78#define IIC_EXTSTS_XFRA 0X01
79#define IIC_EXTSTS_ICT 0X02
80#define IIC_EXTSTS_LA 0X04
81
82/* LED codes used for inditing progress and errors during read of DIMM SPD. */
83/*--------------------------------------------------------------------- */
84#define LED_SDRAM_CODE_1 0xef
85#define LED_SDRAM_CODE_2 0xee
86#define LED_SDRAM_CODE_3 0xed
87#define LED_SDRAM_CODE_4 0xec
88#define LED_SDRAM_CODE_5 0xeb
89#define LED_SDRAM_CODE_6 0xea
90#define LED_SDRAM_CODE_7 0xe9
91#define LED_SDRAM_CODE_8 0xe8
92#define LED_SDRAM_CODE_9 0xe7
93#define LED_SDRAM_CODE_10 0xe6
94#define LED_SDRAM_CODE_11 0xe5
95#define LED_SDRAM_CODE_12 0xe4
96#define LED_SDRAM_CODE_13 0xe3
97#define LED_SDRAM_CODE_14 0xe2
98#define LED_SDRAM_CODE_15 0xe1
99#define LED_SDRAM_CODE_16 0xe0
100
101
102#define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100
103
104#define FLASH_8bit_AP 0x9B015480
wdenk945af8d2003-07-16 21:53:01 +0000105#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */
wdenkd1cbe852003-06-28 17:24:46 +0000106
107#define FLASH_32bit_AP 0x9B015480
108#define FLASH_32bit_CR 0xFFE3C000 /* 2MB, 32bit, R/W */
109
110
111#define WDCR_EBC(reg,val) addi r4,0,reg;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200112 mtdcr EBC0_CFGADDR,r4;\
wdenk945af8d2003-07-16 21:53:01 +0000113 addis r4,0,val@h;\
114 ori r4,r4,val@l;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200115 mtdcr EBC0_CFGDATA,r4
wdenkd1cbe852003-06-28 17:24:46 +0000116
117/*---------------------------------------------------------------------
118 * Function: ext_bus_cntlr_init
wdenk945af8d2003-07-16 21:53:01 +0000119 * Description: Initializes the External Bus Controller for the external
120 * peripherals. IMPORTANT: For pass1 this code must run from
wdenkd1cbe852003-06-28 17:24:46 +0000121 * cache since you can not reliably change a peripheral banks
122 * timing register (pbxap) while running code from that bank.
wdenk945af8d2003-07-16 21:53:01 +0000123 * For ex., since we are running from ROM on bank 0, we can NOT
wdenkd1cbe852003-06-28 17:24:46 +0000124 * execute the code that modifies bank 0 timings from ROM, so
125 * we run it from cache.
126 * Bank 0 - Boot flash
127 * Bank 1-4 - application flash
128 * Bank 5 - CPLD
129 * Bank 6 - not used
130 * Bank 7 - Heathrow chip
wdenk945af8d2003-07-16 21:53:01 +0000131 *---------------------------------------------------------------------
wdenkd1cbe852003-06-28 17:24:46 +0000132 */
wdenk945af8d2003-07-16 21:53:01 +0000133 .globl ext_bus_cntlr_init
wdenkd1cbe852003-06-28 17:24:46 +0000134ext_bus_cntlr_init:
wdenk945af8d2003-07-16 21:53:01 +0000135 mflr r4 /* save link register */
136 bl ..getAddr
wdenkd1cbe852003-06-28 17:24:46 +0000137..getAddr:
wdenk945af8d2003-07-16 21:53:01 +0000138 mflr r3 /* get address of ..getAddr */
139 mtlr r4 /* restore link register */
140 addi r4,0,14 /* set ctr to 10; used to prefetch */
141 mtctr r4 /* 10 cache lines to fit this function */
142 /* in cache (gives us 8x10=80 instrctns) */
wdenkd1cbe852003-06-28 17:24:46 +0000143..ebcloop:
wdenk945af8d2003-07-16 21:53:01 +0000144 icbt r0,r3 /* prefetch cache line for addr in r3 */
145 addi r3,r3,32 /* move to next cache line */
146 bdnz ..ebcloop /* continue for 10 cache lines */
wdenkd1cbe852003-06-28 17:24:46 +0000147
148 mflr r31 /* save link register */
wdenk945af8d2003-07-16 21:53:01 +0000149
150 /*-----------------------------------------------------------
151 * Delay to ensure all accesses to ROM are complete before changing
wdenkd1cbe852003-06-28 17:24:46 +0000152 * bank 0 timings. 200usec should be enough.
wdenk945af8d2003-07-16 21:53:01 +0000153 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
154 *-----------------------------------------------------------
wdenkd1cbe852003-06-28 17:24:46 +0000155 */
156
157 addis r3,0,0x0
wdenk945af8d2003-07-16 21:53:01 +0000158 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
159 mtctr r3
wdenkd1cbe852003-06-28 17:24:46 +0000160..spinlp:
wdenk945af8d2003-07-16 21:53:01 +0000161 bdnz ..spinlp /* spin loop */
wdenkd1cbe852003-06-28 17:24:46 +0000162
wdenk945af8d2003-07-16 21:53:01 +0000163 /*---------------------------------------------------------------
164 * Memory Bank 0 (Boot Flash) initialization
165 *---------------------------------------------------------------
wdenkd1cbe852003-06-28 17:24:46 +0000166 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200167 WDCR_EBC(PB1AP, FLASH_32bit_AP)
168 WDCR_EBC(PB0CR, 0xffe38000)
169/*pnc WDCR_EBC(PB0CR, FLASH_32bit_CR) */
wdenk945af8d2003-07-16 21:53:01 +0000170
171 /*---------------------------------------------------------------
172 * Memory Bank 5 (CPLD) initialization
173 *---------------------------------------------------------------
wdenkd1cbe852003-06-28 17:24:46 +0000174 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200175 WDCR_EBC(PB5AP, 0x01010040)
176/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */
177 WDCR_EBC(PB5CR, 0x10038000)
wdenkd1cbe852003-06-28 17:24:46 +0000178
wdenk945af8d2003-07-16 21:53:01 +0000179 /*--------------------------------------------------------------- */
180 /* Memory Bank 6 (not used) initialization */
181 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200182 WDCR_EBC(PB6CR, 0x00000000)
wdenkd1cbe852003-06-28 17:24:46 +0000183
184 /* Read HW ID to determine whether old H2 board or new generic CPU board */
185 addis r3, 0, HW_ID_ADDR@h
186 ori r3, r3, HW_ID_ADDR@l
wdenk945af8d2003-07-16 21:53:01 +0000187 lbz r3,0x0000(r3)
wdenkd1cbe852003-06-28 17:24:46 +0000188 cmpi 0, r3, 1 /* if (HW_ID==1) */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200189 beq setup_h2evalboard /* then jump */
wdenkd1cbe852003-06-28 17:24:46 +0000190 cmpi 0, r3, 2 /* if (HW_ID==2) */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200191 beq setup_genieboard /* then jump */
wdenkd1cbe852003-06-28 17:24:46 +0000192 cmpi 0, r3, 3 /* if (HW_ID==3) */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200193 beq setup_genieboard /* then jump */
wdenkd1cbe852003-06-28 17:24:46 +0000194
195setup_genieboard:
wdenk945af8d2003-07-16 21:53:01 +0000196 /*--------------------------------------------------------------- */
197 /* Memory Bank 1 (Application Flash) initialization for generic CPU board */
198 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200199/* WDCR_EBC(PB1AP, 0x7b015480) /###* T.B.M. */
200/* WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */
201 WDCR_EBC(PB1AP, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */
wdenkd1cbe852003-06-28 17:24:46 +0000202
Stefan Roesed1c3b272009-09-09 16:25:29 +0200203/* WDCR_EBC(PB1CR, 0x20098000) /###* 16 MB */
204 WDCR_EBC(PB1CR, 0x200B8000) /* 32 MB */
wdenkd1cbe852003-06-28 17:24:46 +0000205
wdenk945af8d2003-07-16 21:53:01 +0000206 /*--------------------------------------------------------------- */
207 /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
208 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200209 WDCR_EBC(PB4AP, 0x01010000) /* */
210 WDCR_EBC(PB4CR, 0x1021c000) /* */
wdenkd1cbe852003-06-28 17:24:46 +0000211
wdenk945af8d2003-07-16 21:53:01 +0000212 /*--------------------------------------------------------------- */
213 /* Memory Bank 7 (Heathrow chip on Reference board) initialization */
214 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200215 WDCR_EBC(PB7AP, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */
216 WDCR_EBC(PB7CR, 0X4001A000)
wdenkd1cbe852003-06-28 17:24:46 +0000217
218 bl setup_continue
219
wdenk945af8d2003-07-16 21:53:01 +0000220
wdenkd1cbe852003-06-28 17:24:46 +0000221setup_h2evalboard:
wdenk945af8d2003-07-16 21:53:01 +0000222 /*--------------------------------------------------------------- */
223 /* Memory Bank 1 (Application Flash) initialization */
224 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200225 WDCR_EBC(PB1AP, 0x7b015480) /* T.B.M. */
226/*3010 WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */
227 WDCR_EBC(PB1CR, 0x20058000)
wdenkd1cbe852003-06-28 17:24:46 +0000228
229 /*--------------------------------------------------------------- */
wdenk945af8d2003-07-16 21:53:01 +0000230 /* Memory Bank 2 (Application Flash) initialization */
231 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200232 WDCR_EBC(PB2AP, 0x7b015480) /* T.B.M. */
233/*3010 WDCR_EBC(PB2AP, 0x7F8FFE80) /###* T.B.M. */
234 WDCR_EBC(PB2CR, 0x20458000)
wdenk945af8d2003-07-16 21:53:01 +0000235
236 /*--------------------------------------------------------------- */
237 /* Memory Bank 3 (Application Flash) initialization */
238 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200239 WDCR_EBC(PB3AP, 0x7b015480) /* T.B.M. */
240/*3010 WDCR_EBC(PB3AP, 0x7F8FFE80) /###* T.B.M. */
241 WDCR_EBC(PB3CR, 0x20858000)
wdenkd1cbe852003-06-28 17:24:46 +0000242
wdenk945af8d2003-07-16 21:53:01 +0000243 /*--------------------------------------------------------------- */
244 /* Memory Bank 4 (Application Flash) initialization */
245 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200246 WDCR_EBC(PB4AP, 0x7b015480) /* T.B.M. */
247/*3010 WDCR_EBC(PB4AP, 0x7F8FFE80) /###* T.B.M. */
248 WDCR_EBC(PB4CR, 0x20C58000)
wdenkd1cbe852003-06-28 17:24:46 +0000249
wdenk945af8d2003-07-16 21:53:01 +0000250 /*--------------------------------------------------------------- */
251 /* Memory Bank 7 (Heathrow chip) initialization */
252 /*--------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200253 WDCR_EBC(PB7AP, 0x02000280) /* No Ready, 4 wait states */
254 WDCR_EBC(PB7CR, 0X4001A000)
wdenkd1cbe852003-06-28 17:24:46 +0000255
256setup_continue:
257
wdenk945af8d2003-07-16 21:53:01 +0000258
259 mtlr r31 /* restore lr */
wdenkd1cbe852003-06-28 17:24:46 +0000260 nop /* pass2 DCR errata #8 */
wdenk945af8d2003-07-16 21:53:01 +0000261 blr
wdenkd1cbe852003-06-28 17:24:46 +0000262
263/*--------------------------------------------------------------------- */
264/* Function: sdram_init */
265/* Description: Configures SDRAM memory banks. */
266/*--------------------------------------------------------------------- */
wdenk945af8d2003-07-16 21:53:01 +0000267 .globl sdram_init
wdenkd1cbe852003-06-28 17:24:46 +0000268
269sdram_init:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
wdenkd1cbe852003-06-28 17:24:46 +0000271 blr
272#else
273 mflr r31
274
275 /* output SDRAM code on LEDs */
276 addi r4, 0, LED_SDRAM_CODE_1
277 addis r5, 0, 0x1000
278 ori r5, r5, 0x0001
279 stb r4,0(r5)
280 eieio
281
282 /* Read contents of spd */
283 /*--------------------- */
284 bl read_spd
285
286 /*----------------------------------------------------------- */
287 /* */
288 /* */
289 /* Update SDRAM timing register */
290 /* */
291 /* */
292 /*----------------------------------------------------------- */
293
294 /* Read PLL feedback divider and calculate clock period of local bus in */
295 /* granularity of 10 ps. Save clock period in r30 */
296 /*-------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200297 mfdcr r4, CPC0_PLLMR
wdenkd1cbe852003-06-28 17:24:46 +0000298 addi r9, 0, 25
299 srw r4, r4, r9
300 andi. r4, r4, 0x07
301 addis r5, 0, TIMEBASE_10PS@h
302 ori r5, r5, TIMEBASE_10PS@l
303 divwu r30, r5, r4
304
305 /* Determine CASL */
306 /*--------------- */
307 bl find_casl /* Returns CASL in r3 */
308
309 /* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */
310 /* (trp read from byte 27 in granularity of 1 ns) */
311 /*------------------------------------------------ */
312 mulli r16, r16, 100
313 add r16, r16, r30
314 addi r6, 0, 1
315 subf r16, r6, r16
316 divwu r16, r16, r30
317
318 /* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */
319 /* (trcd read from byte 29 in granularity of 1 ns) */
320 /*--------------------------------------------------- */
321 mulli r17, r17, 100
322 add r17, r17, r30
323 addi r6, 0, 1
324 subf r17, r6, r17
325 divwu r17, r17, r30
326
327 /* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */
328 /* (tras read from byte 30 in granularity of 1 ns) */
329 /*--------------------------------------------------- */
330 mulli r18, r18, 100
331 add r18, r18, r30
332 addi r6, 0, 1
333 subf r18, r6, r18
334 divwu r18, r18, r30
335
336 /* Calc trc_clocks = trp_clocks + tras_clocks */
337 /*------------------------------------------- */
338 add r18, r18, r16
339
340 /* CASL value */
341 /*----------- */
342 addi r9, 0, 23
343 slw r4, r3, r9
344
345 /* PTA = trp_clocks - 1 */
346 /*--------------------- */
347 addi r6, 0, 1
348 subf r5, r6, r16
349 addi r9, 0, 18
350 slw r5, r5, r9
351 or r4, r4, r5
352
353 /* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */
354 /*------------------------------------------------ */
355 addi r5, r18, 0
356 subf r5, r16, r5
357 subf r5, r17, r5
358 addi r6, 0, 1
359 subf r5, r6, r5
360 addi r9, 0, 16
361 slw r5, r5, r9
362 or r4, r4, r5
363
364 /* LDF = 1 */
365 /*-------- */
366 ori r4, r4, 0x4000
367
368 /* RFTA = trc_clocks - 4 */
369 /*---------------------- */
370 addi r6, 0, 4
371 subf r5, r6, r18
372 addi r9, 0, 2
373 slw r5, r5, r9
374 or r4, r4, r5
375
376 /* RCD = trcd_clocks - 1 */
377 /*---------------------- */
378 addi r6, 0, 1
379 subf r5, r6, r17
380 or r4, r4, r5
381
wdenk945af8d2003-07-16 21:53:01 +0000382 /*----------------------------------------------------------- */
383 /* Set SDTR1 */
384 /*----------------------------------------------------------- */
Stefan Roese95b602b2009-09-24 13:59:57 +0200385 addi r5,0,SDRAM0_TR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200386 mtdcr SDRAM0_CFGADDR,r5
387 mtdcr SDRAM0_CFGDATA,r4
wdenkd1cbe852003-06-28 17:24:46 +0000388
389 /*----------------------------------------------------------- */
390 /* */
391 /* */
392 /* Update memory bank 0-3 configuration registers */
393 /* */
394 /* */
395 /*----------------------------------------------------------- */
396
397 /* Build contents of configuration register for bank 0 into r6 */
398 /*------------------------------------------------------------ */
399 bl find_mode /* returns addressing mode in r3 */
400 addi r29, r3, 0 /* save mode temporarily in r29 */
401 bl find_size_code /* returns size code in r3 */
402 addi r9, 0, 17 /* bit offset of size code in configuration register */
403 slw r3, r3, r9 /* */
404 addi r9, 0, 13 /* bit offset of addressing mode in configuration register */
405 slw r29, r29, r9 /* */
406 or r3, r29, r3 /* merge size code and addressing mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407 ori r6, r3, CONFIG_SYS_SDRAM_BASE + 1 /* insert base address and enable bank */
wdenkd1cbe852003-06-28 17:24:46 +0000408
409 /* Calculate banksize r15 = (density << 22) / 2 */
410 /*--------------------------------------------- */
411 addi r9, 0, 21
412 slw r15, r15, r9
413
414 /* Set SDRAM bank 0 register and adjust r6 for next bank */
415 /*------------------------------------------------------ */
Stefan Roese95b602b2009-09-24 13:59:57 +0200416 addi r7,0,SDRAM0_B0CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200417 mtdcr SDRAM0_CFGADDR,r7
418 mtdcr SDRAM0_CFGDATA,r6
wdenkd1cbe852003-06-28 17:24:46 +0000419
420 add r6, r6, r15 /* add bank size to base address for next bank */
421
422 /* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */
423 /*---------------------------------------------------------------------------- */
424 cmpi 0, r12, 2
425 bne b1skip
426
Stefan Roese95b602b2009-09-24 13:59:57 +0200427 addi r7,0,SDRAM0_B1CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200428 mtdcr SDRAM0_CFGADDR,r7
429 mtdcr SDRAM0_CFGDATA,r6
wdenkd1cbe852003-06-28 17:24:46 +0000430
431 add r6, r6, r15 /* add bank size to base address for next bank */
432
433 /* Set SDRAM bank 2 register and adjust r6 for next bank */
434 /*------------------------------------------------------ */
Stefan Roese95b602b2009-09-24 13:59:57 +0200435b1skip: addi r7,0,SDRAM0_B2CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200436 mtdcr SDRAM0_CFGADDR,r7
437 mtdcr SDRAM0_CFGDATA,r6
wdenkd1cbe852003-06-28 17:24:46 +0000438
439 add r6, r6, r15 /* add bank size to base address for next bank */
440
441 /* If two rows/banks then set SDRAM bank 3 register */
442 /*------------------------------------------------ */
443 cmpi 0, r12, 2
444 bne b3skip
445
Stefan Roese95b602b2009-09-24 13:59:57 +0200446 addi r7,0,SDRAM0_B3CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200447 mtdcr SDRAM0_CFGADDR,r7
448 mtdcr SDRAM0_CFGDATA,r6
wdenk945af8d2003-07-16 21:53:01 +0000449b3skip:
wdenkd1cbe852003-06-28 17:24:46 +0000450
wdenk945af8d2003-07-16 21:53:01 +0000451 /*----------------------------------------------------------- */
452 /* Set RTR */
453 /*----------------------------------------------------------- */
wdenkd1cbe852003-06-28 17:24:46 +0000454 cmpi 0, r30, 1600
455 bge rtr_1
wdenk945af8d2003-07-16 21:53:01 +0000456 addis r7, 0, 0x05F0 /* RTR value for 100Mhz */
wdenkd1cbe852003-06-28 17:24:46 +0000457 bl rtr_2
458rtr_1: addis r7, 0, 0x03F8
Stefan Roese95b602b2009-09-24 13:59:57 +0200459rtr_2: addi r4,0,SDRAM0_RTR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200460 mtdcr SDRAM0_CFGADDR,r4
461 mtdcr SDRAM0_CFGDATA,r7
wdenkd1cbe852003-06-28 17:24:46 +0000462
wdenk945af8d2003-07-16 21:53:01 +0000463 /*----------------------------------------------------------- */
464 /* Delay to ensure 200usec have elapsed since reset. Assume worst */
465 /* case that the core is running 200Mhz: */
466 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
467 /*----------------------------------------------------------- */
468 addis r3,0,0x0000
469 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
470 mtctr r3
wdenkd1cbe852003-06-28 17:24:46 +0000471..spinlp2:
wdenk945af8d2003-07-16 21:53:01 +0000472 bdnz ..spinlp2 /* spin loop */
wdenkd1cbe852003-06-28 17:24:46 +0000473
wdenk945af8d2003-07-16 21:53:01 +0000474 /*----------------------------------------------------------- */
475 /* Set memory controller options reg, MCOPT1. */
wdenkd1cbe852003-06-28 17:24:46 +0000476 /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
477 /* read/prefetch. */
wdenk945af8d2003-07-16 21:53:01 +0000478 /*----------------------------------------------------------- */
Stefan Roese95b602b2009-09-24 13:59:57 +0200479 addi r4,0,SDRAM0_CFG
Stefan Roesed1c3b272009-09-09 16:25:29 +0200480 mtdcr SDRAM0_CFGADDR,r4
wdenkd1cbe852003-06-28 17:24:46 +0000481 addis r4,0,0x80C0 /* set DC_EN=1 */
482 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200483 mtdcr SDRAM0_CFGDATA,r4
wdenkd1cbe852003-06-28 17:24:46 +0000484
485
wdenk945af8d2003-07-16 21:53:01 +0000486 /*----------------------------------------------------------- */
487 /* Delay to ensure 10msec have elapsed since reset. This is */
488 /* required for the MPC952 to stabalize. Assume worst */
489 /* case that the core is running 200Mhz: */
490 /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
491 /* This delay should occur before accessing SDRAM. */
492 /*----------------------------------------------------------- */
wdenkd1cbe852003-06-28 17:24:46 +0000493 addis r3,0,0x001E
494 ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
495 mtctr r3
496..spinlp3:
497 bdnz ..spinlp3 /* spin loop */
498
499 /* output SDRAM code on LEDs */
500 addi r4, 0, LED_SDRAM_CODE_16
501 addis r5, 0, 0x1000
502 ori r5, r5, 0x0001
503 stb r4,0(r5)
504 eieio
505
wdenk945af8d2003-07-16 21:53:01 +0000506 mtlr r31 /* restore lr */
507 blr
wdenkd1cbe852003-06-28 17:24:46 +0000508
509/*--------------------------------------------------------------------- */
510/* Function: read_spd */
511/* Description: Reads contents of SPD and saves parameters to be used for */
512/* configuration in dedicated registers (see code below). */
513/*--------------------------------------------------------------------- */
514
515#define WRITE_I2C(reg,val) \
516 addi r3,0,val;\
wdenk945af8d2003-07-16 21:53:01 +0000517 addis r4, 0, 0xef60;\
518 ori r4, r4, 0x0500 + reg;\
519 stb r3, 0(r4);\
520 eieio
wdenkd1cbe852003-06-28 17:24:46 +0000521
522#define READ_I2C(reg) \
wdenk945af8d2003-07-16 21:53:01 +0000523 addis r3, 0, 0xef60;\
524 ori r3, r3, 0x0500 + reg;\
525 lbz r3, 0x0000(r3);\
526 eieio
wdenkd1cbe852003-06-28 17:24:46 +0000527
528read_spd:
529
530 mflr r5
wdenk945af8d2003-07-16 21:53:01 +0000531
wdenkd1cbe852003-06-28 17:24:46 +0000532 /* Initialize i2c */
533 /*--------------- */
534 WRITE_I2C(IICLMADR, 0x00) /* clear lo master address */
535 WRITE_I2C(IICHMADR, 0x00) /* clear hi master address */
536 WRITE_I2C(IICLSADR, 0x00) /* clear lo slave address */
537 WRITE_I2C(IICHSADR, 0x00) /* clear hi slave address */
538 WRITE_I2C(IICSTS, 0x08) /* update status register */
539 WRITE_I2C(IICEXTSTS, 0x8f)
540 WRITE_I2C(IICCLKDIV, 0x05)
541 WRITE_I2C(IICINTRMSK, 0x00) /* no interrupts */
542 WRITE_I2C(IICXFRCNT, 0x00) /* clear transfer count */
543 WRITE_I2C(IICXTCNTLSS, 0xf0) /* clear extended control & stat */
544 WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB) /* mode control */
545 READ_I2C(IICMDCNTL)
546 ori r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL
547 WRITE_I2C(IICMDCNTL, r3) /* mode control */
548 WRITE_I2C(IICCNTL, 0x00) /* clear control reg */
549
550 /* Wait until initialization completed */
551 /*------------------------------------ */
552 bl wait_i2c_transfer_done
553
554 WRITE_I2C(IICHMADR, 0x00) /* 7-bit addressing */
555 WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS)
556
557 /* Write 0 into buffer(start address) */
558 /*----------------------------------- */
559 WRITE_I2C(IICMDBUF, 0x00);
560
561 /* Wait a little */
562 /*-------------- */
wdenk945af8d2003-07-16 21:53:01 +0000563 addis r3,0,0x0000
564 ori r3,r3,0xA000
565 mtctr r3
wdenkd1cbe852003-06-28 17:24:46 +0000566in02: bdnz in02
567
568 /* Issue write command */
569 /*-------------------- */
570 WRITE_I2C(IICCNTL, IIC_CNTL_PT)
571 bl wait_i2c_transfer_done
572
573 /* Read 128 bytes */
574 /*--------------- */
575 addi r7, 0, 0 /* byte counter in r7 */
576 addi r8, 0, 0 /* checksum in r8 */
wdenk945af8d2003-07-16 21:53:01 +0000577rdlp:
wdenkd1cbe852003-06-28 17:24:46 +0000578 /* issue read command */
579 /*------------------- */
580 cmpi 0, r7, 127
581 blt rd01
wdenk945af8d2003-07-16 21:53:01 +0000582 WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
wdenkd1cbe852003-06-28 17:24:46 +0000583 bl rd02
584rd01: WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
585rd02: bl wait_i2c_transfer_done
586
587 /* Fetch byte from buffer */
588 /*----------------------- */
589 READ_I2C(IICMDBUF)
wdenk945af8d2003-07-16 21:53:01 +0000590
wdenkd1cbe852003-06-28 17:24:46 +0000591 /* Retrieve parameters that are going to be used during configuration. */
592 /* Save them in dedicated registers. */
593 /*------------------------------------------------------------ */
594 cmpi 0, r7, 3 /* Save byte 3 in r10 */
595 bne rd10
wdenk945af8d2003-07-16 21:53:01 +0000596 addi r10, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000597rd10: cmpi 0, r7, 4 /* Save byte 4 in r11 */
598 bne rd11
wdenk945af8d2003-07-16 21:53:01 +0000599 addi r11, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000600rd11: cmpi 0, r7, 5 /* Save byte 5 in r12 */
601 bne rd12
wdenk945af8d2003-07-16 21:53:01 +0000602 addi r12, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000603rd12: cmpi 0, r7, 17 /* Save byte 17 in r13 */
604 bne rd13
wdenk945af8d2003-07-16 21:53:01 +0000605 addi r13, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000606rd13: cmpi 0, r7, 18 /* Save byte 18 in r14 */
607 bne rd14
wdenk945af8d2003-07-16 21:53:01 +0000608 addi r14, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000609rd14: cmpi 0, r7, 31 /* Save byte 31 in r15 */
610 bne rd15
wdenk945af8d2003-07-16 21:53:01 +0000611 addi r15, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000612rd15: cmpi 0, r7, 27 /* Save byte 27 in r16 */
613 bne rd16
wdenk945af8d2003-07-16 21:53:01 +0000614 addi r16, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000615rd16: cmpi 0, r7, 29 /* Save byte 29 in r17 */
616 bne rd17
wdenk945af8d2003-07-16 21:53:01 +0000617 addi r17, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000618rd17: cmpi 0, r7, 30 /* Save byte 30 in r18 */
619 bne rd18
wdenk945af8d2003-07-16 21:53:01 +0000620 addi r18, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000621rd18: cmpi 0, r7, 9 /* Save byte 9 in r19 */
622 bne rd19
wdenk945af8d2003-07-16 21:53:01 +0000623 addi r19, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000624rd19: cmpi 0, r7, 23 /* Save byte 23 in r20 */
625 bne rd20
wdenk945af8d2003-07-16 21:53:01 +0000626 addi r20, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000627rd20: cmpi 0, r7, 25 /* Save byte 25 in r21 */
628 bne rd21
wdenk945af8d2003-07-16 21:53:01 +0000629 addi r21, r3, 0
wdenkd1cbe852003-06-28 17:24:46 +0000630rd21:
631
632 /* Calculate checksum of the first 63 bytes */
633 /*----------------------------------------- */
634 cmpi 0, r7, 63
635 bgt rd31
636 beq rd30
637 add r8, r8, r3
638 bl rd31
639
640 /* Verify checksum at byte 63 */
641 /*--------------------------- */
642rd30: andi. r8, r8, 0xff /* use only 8 bits */
643 cmp 0, r8, r3
644 beq rd31
645 addi r4, 0, LED_SDRAM_CODE_8
646 addis r5, 0, 0x1000
647 ori r5, r5, 0x0001
648 stb r4,0(r5)
649 eieio
650rderr: bl rderr
651
wdenk945af8d2003-07-16 21:53:01 +0000652rd31:
653
wdenkd1cbe852003-06-28 17:24:46 +0000654 /* Increment byte counter and check whether all bytes have been read. */
655 /*------------------------------------------------------------------- */
656 addi r7, r7, 1
657 cmpi 0, r7, 127
658 bgt rd05
659 bl rdlp
wdenk945af8d2003-07-16 21:53:01 +0000660rd05:
661 mtlr r5 /* restore lr */
wdenkd1cbe852003-06-28 17:24:46 +0000662 blr
663
664wait_i2c_transfer_done:
665 mflr r6
666wt01: READ_I2C(IICSTS)
667 andi. r4, r3, IIC_STS_PT
668 cmpi 0, r4, IIC_STS_PT
wdenk945af8d2003-07-16 21:53:01 +0000669 beq wt01
670 mtlr r6 /* restore lr */
wdenkd1cbe852003-06-28 17:24:46 +0000671 blr
672
673/*--------------------------------------------------------------------- */
674/* Function: find_mode */
675/* Description: Determines addressing mode to be used dependent on */
676/* number of rows (r10 = byte 3 from SPD), number of columns (r11 = */
677/* byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */
678/* mode is returned in r3. */
679/* (It would be nicer having a table, pnc). */
680/*--------------------------------------------------------------------- */
681find_mode:
682
683 mflr r5
684
685 cmpi 0, r10, 11
686 bne fm01
687 cmpi 0, r11, 9
688 bne fm01
689 cmpi 0, r13, 2
690 bne fm01
691 addi r3, 0, 1
692 bl fmfound
693
694fm01: cmpi 0, r10, 11
695 bne fm02
696 cmpi 0, r11, 10
697 bne fm02
698 cmpi 0, r13, 2
699 bne fm02
700 addi r3, 0, 1
wdenk945af8d2003-07-16 21:53:01 +0000701 bl fmfound
wdenkd1cbe852003-06-28 17:24:46 +0000702
703fm02: cmpi 0, r10, 12
704 bne fm03
705 cmpi 0, r11, 9
706 bne fm03
707 cmpi 0, r13, 4
708 bne fm03
709 addi r3, 0, 2
710 bl fmfound
711
712fm03: cmpi 0, r10, 12
713 bne fm04
714 cmpi 0, r11, 10
715 bne fm04
716 cmpi 0, r13, 4
717 bne fm04
718 addi r3, 0, 2
719 bl fmfound
720
721fm04: cmpi 0, r10, 13
722 bne fm05
723 cmpi 0, r11, 9
724 bne fm05
725 cmpi 0, r13, 4
726 bne fm05
727 addi r3, 0, 3
728 bl fmfound
729
730fm05: cmpi 0, r10, 13
731 bne fm06
732 cmpi 0, r11, 10
733 bne fm06
734 cmpi 0, r13, 4
735 bne fm06
736 addi r3, 0, 3
737 bl fmfound
738
739fm06: cmpi 0, r10, 13
740 bne fm07
741 cmpi 0, r11, 11
742 bne fm07
743 cmpi 0, r13, 4
744 bne fm07
745 addi r3, 0, 3
746 bl fmfound
747
748fm07: cmpi 0, r10, 12
749 bne fm08
750 cmpi 0, r11, 8
751 bne fm08
752 cmpi 0, r13, 2
753 bne fm08
754 addi r3, 0, 4
755 bl fmfound
756
757fm08: cmpi 0, r10, 12
758 bne fm09
759 cmpi 0, r11, 8
760 bne fm09
761 cmpi 0, r13, 4
762 bne fm09
763 addi r3, 0, 4
764 bl fmfound
765
766fm09: cmpi 0, r10, 11
767 bne fm10
768 cmpi 0, r11, 8
769 bne fm10
770 cmpi 0, r13, 2
771 bne fm10
772 addi r3, 0, 5
773 bl fmfound
774
775fm10: cmpi 0, r10, 11
776 bne fm11
777 cmpi 0, r11, 8
778 bne fm11
779 cmpi 0, r13, 4
780 bne fm11
781 addi r3, 0, 5
782 bl fmfound
783
784fm11: cmpi 0, r10, 13
785 bne fm12
786 cmpi 0, r11, 8
787 bne fm12
788 cmpi 0, r13, 2
789 bne fm12
790 addi r3, 0, 6
791 bl fmfound
792
793fm12: cmpi 0, r10, 13
794 bne fm13
795 cmpi 0, r11, 8
796 bne fm13
797 cmpi 0, r13, 4
798 bne fm13
799 addi r3, 0, 6
800 bl fmfound
801
802fm13: cmpi 0, r10, 13
803 bne fm14
804 cmpi 0, r11, 9
805 bne fm14
806 cmpi 0, r13, 2
807 bne fm14
808 addi r3, 0, 7
809 bl fmfound
810
811fm14: cmpi 0, r10, 13
812 bne fm15
813 cmpi 0, r11, 10
814 bne fm15
815 cmpi 0, r13, 2
816 bne fm15
817 addi r3, 0, 7
818 bl fmfound
819
wdenk945af8d2003-07-16 21:53:01 +0000820fm15:
wdenkd1cbe852003-06-28 17:24:46 +0000821 /* not found, error code to be issued on LEDs */
822 addi r7, 0, LED_SDRAM_CODE_2
823 addis r6, 0, 0x1000
824 ori r6, r6, 0x0001
825 stb r7,0(r6)
826 eieio
827fmerr: bl fmerr
828
829fmfound:addi r6, 0, 1
830 subf r3, r6, r3
831
wdenk945af8d2003-07-16 21:53:01 +0000832 mtlr r5 /* restore lr */
wdenkd1cbe852003-06-28 17:24:46 +0000833 blr
834
835/*--------------------------------------------------------------------- */
836/* Function: find_size_code */
837/* Description: Determines size code to be used in configuring SDRAM controller */
838/* dependent on density (r15 = byte 31 from SPD) */
839/*--------------------------------------------------------------------- */
840find_size_code:
841
842 mflr r5
wdenk945af8d2003-07-16 21:53:01 +0000843
wdenkd1cbe852003-06-28 17:24:46 +0000844 addi r3, r15, 0 /* density */
845 addi r7, 0, 0
846fs01: andi. r6, r3, 0x01
847 cmpi 0, r6, 1
848 beq fs04
wdenk945af8d2003-07-16 21:53:01 +0000849
wdenkd1cbe852003-06-28 17:24:46 +0000850 addi r7, r7, 1
851 cmpi 0, r7, 7
852 bge fs02
853 addi r9, 0, 1
854 srw r3, r3, r9
855 bl fs01
856
857 /* not found, error code to be issued on LEDs */
858fs02: addi r4, 0, LED_SDRAM_CODE_3
859 addis r8, 0, 0x1000
860 ori r8, r8, 0x0001
861 stb r4,0(r8)
862 eieio
863fs03: bl fs03
864
865fs04: addi r3, r7, 0
866 cmpi 0, r3, 0
867 beq fs05
868 addi r6, 0, 1
869 subf r3, r6, r3
870fs05:
wdenk945af8d2003-07-16 21:53:01 +0000871 mtlr r5 /* restore lr */
wdenkd1cbe852003-06-28 17:24:46 +0000872 blr
873
874/*--------------------------------------------------------------------- */
875/* Function: find_casl */
876/* Description: Determines CAS latency */
877/*--------------------------------------------------------------------- */
878find_casl:
879
880 mflr r5
881
882 andi. r14, r14, 0x7f /* r14 holds supported CAS latencies */
883 addi r3, 0, 0xff /* preset determined CASL */
884 addi r4, 0, 6 /* Start at bit 6 of supported CAS latencies */
885 addi r2, 0, 0 /* Start finding highest CAS latency */
886
887fc01: srw r6, r14, r4 /* */
888 andi. r6, r6, 0x01 /* */
889 cmpi 0, r6, 1 /* Check bit for current latency */
890 bne fc06 /* If not supported, go to next */
891
892 cmpi 0, r2, 2 /* Check if third-highest latency */
893 bge fc04 /* If so, go calculate with another format */
894
895 cmpi 0, r2, 0 /* Check if highest latency */
896 bgt fc02 /* */
897 addi r7, r19, 0 /* SDRAM cycle time for highest CAS latenty */
898
899 bl fc03
wdenk945af8d2003-07-16 21:53:01 +0000900fc02:
wdenkd1cbe852003-06-28 17:24:46 +0000901 addi r7, r20, 0 /* SDRAM cycle time for next-highest CAS latenty */
wdenk945af8d2003-07-16 21:53:01 +0000902fc03:
wdenkd1cbe852003-06-28 17:24:46 +0000903 addi r8, r7, 0
904 addi r9, 0, 4
905 srw r7, r7, r9
906 andi. r7, r7, 0x0f
907 mulli r7, r7, 100
908 andi. r8, r8, 0x0f
909 mulli r8, r8, 10
910 add r7, r7, r8
911 cmp 0, r7, r30
912 bgt fc05
913 addi r3, r2, 0
914 bl fc05
wdenk945af8d2003-07-16 21:53:01 +0000915fc04:
wdenkd1cbe852003-06-28 17:24:46 +0000916 addi r7, r21, 0 /* SDRAM cycle time for third-highest CAS latenty */
917 addi r8, r7, 0
918 addi r9, 0, 2
919 srw r7, r7, r9
920 andi. r7, r7, 0x3f
921 mulli r7, r7, 100
922 andi. r8, r8, 0x03
923 mulli r8, r8, 25
924 add r7, r7, r8
925
926 cmp 0, r7, r30
927 bgt fc05
928 addi r3, r2, 0
929
930fc05: addi r2, r2, 1 /* next latency */
931 cmpi 0, r2, 3
932 bge fc07
933fc06: addi r6, 0, 1
934 subf r4, r6, r4
935 cmpi 0, r4, 0
936 bne fc01
937
wdenk945af8d2003-07-16 21:53:01 +0000938fc07:
wdenkd1cbe852003-06-28 17:24:46 +0000939
wdenk945af8d2003-07-16 21:53:01 +0000940 mtlr r5 /* restore lr */
wdenkd1cbe852003-06-28 17:24:46 +0000941 blr
942#endif
943
944
945/* Peripheral Bank 1 Access Parameters */
946/* 0 BME = 1 ; burstmode enabled */
947/* " 1:8" TWT=00110110 ;Transfer wait (details below) */
948/* 1:5 FWT=00110 ; first wait = 6 cycles */
949/* 6:8 BWT=110 ; burst wait = 6 cycles */
950/* 9:11 000 ; reserved */
951/* 12:13 CSN=00 ; chip select on timing = 0 */
952/* 14:15 OEN=01 ; output enable */
953/* 16:17 WBN=01 ; write byte enable on timing 1 cycle */
954/* 18:19 WBF=01 ; write byte enable off timing 1 cycle */
955/* 20:22 TH=010 ; transfer hold = 2 cycles */
956/* 23 RE=0 ; ready enable = disabled */
957/* 24 SOR=1 ; sample on ready = same PerClk */
958/* 25 BEM=0 ; byte enable mode = only for write cycles */
959/* 26 PEN=0 ; parity enable = disable */
960/* 27:31 00000 ;reserved */
961/* */
962/* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */
963/* */
964/* */
965/* Code for BDI probe: */
966/* */
967/* WDCR 18 0x00000011 ;Select PB1AP */
968/* WDCR 19 0x1b015480 ;PB1AP: Flash */
969/* */
970/* Peripheral Bank 0 Access Parameters */
971/* 0:11 BAS=0x200 ; base address select = 0x200 * 0x100000 (1MB) = */
972/* 12:14 BS=100 ; bank size = 16MB (100) / 32MB (101) */
973/* 15:16 BU=11 ; bank usage = read/write */
974/* 17:18 BW=00 ; bus width = 8-bit */
975/* 19:31 ; reserved */
976/* */
977/* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */
978/* WDCR 18 0x00000001 ;Select PB1CR */
979/* WDCR 19 0x20098000 ;PB1CR: 1MB at 0x00100000, r/w, 8bit */
980
981/* For CPLD */
982/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200983/* WDCR_EBC(PB5AP, 0x01010040) */
984/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */
985/* WDCR_EBC(PB5CR, 0X10018000) */
wdenkd1cbe852003-06-28 17:24:46 +0000986/* Access parms */
987/* 100 3 8 0 0 0 */
988/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */
989/* Address : 0x10000000 */
990/* Size: 2 MB */
991/* Usage: read/write */
992/* Width: 32 bit */
993
994/* For Genie onboard fpga 32 bit interface */
995/* 0 1 0 1 0 0 0 0 */
996/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */
997/* 0x01010000 */
998/* Access parms */
999/* 102 1 c 0 0 0 */
1000/* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */
1001/* Address : 0x10200000 */
1002/* Size: 2 MB */
1003/* Usage: read/write */
1004/* Width: 32 bit */
wdenk945af8d2003-07-16 21:53:01 +00001005
Stefan Roesed1c3b272009-09-09 16:25:29 +02001006/* Walnut fpga PB7AP */
wdenkd1cbe852003-06-28 17:24:46 +00001007/* 0 1 8 1 5 2 8 0 */
1008/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001009/* Walnut fpga PB7CR */
wdenkd1cbe852003-06-28 17:24:46 +00001010/* 0xF0318000 */
1011/* */