| Dzmitry Sankouski | 4cbc16c | 2021-10-17 13:44:31 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Qualcomm SDM845 chip device tree source |
| 4 | * |
| 5 | * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | /dts-v1/; |
| 10 | |
| 11 | #include "skeleton64.dtsi" |
| 12 | |
| 13 | / { |
| 14 | soc: soc { |
| 15 | #address-cells = <1>; |
| 16 | #size-cells = <1>; |
| 17 | ranges = <0 0 0 0xffffffff>; |
| 18 | compatible = "simple-bus"; |
| 19 | |
| 20 | gcc: clock-controller@100000 { |
| 21 | u-boot,dm-pre-reloc; |
| 22 | compatible = "qcom,gcc-sdm845"; |
| 23 | reg = <0x100000 0x1f0000>; |
| 24 | #clock-cells = <1>; |
| 25 | #reset-cells = <1>; |
| 26 | #power-domain-cells = <1>; |
| 27 | }; |
| 28 | |
| 29 | gpio_north: gpio_north@3900000 { |
| 30 | u-boot,dm-pre-reloc; |
| 31 | #gpio-cells = <2>; |
| 32 | compatible = "qcom,sdm845-pinctrl"; |
| 33 | reg = <0x3900000 0x400000>; |
| 34 | gpio-count = <150>; |
| 35 | gpio-controller; |
| 36 | gpio-ranges = <&gpio_north 0 0 150>; |
| 37 | gpio-bank-name = "soc_north."; |
| 38 | }; |
| 39 | |
| 40 | tlmm_north: pinctrl_north@3900000 { |
| 41 | u-boot,dm-pre-reloc; |
| 42 | compatible = "qcom,tlmm-sdm845"; |
| 43 | reg = <0x3900000 0x400000>; |
| 44 | gpio-count = <150>; |
| 45 | gpio-controller; |
| 46 | #gpio-cells = <2>; |
| 47 | gpio-ranges = <&tlmm_north 0 0 150>; |
| 48 | |
| 49 | /* DEBUG UART */ |
| 50 | qup_uart9: qup-uart9-default { |
| Dzmitry Sankouski | f8a1b33 | 2022-02-22 21:49:53 +0300 | [diff] [blame^] | 51 | pins = "GPIO_4", "GPIO_5"; |
| 52 | function = "gpio"; |
| Dzmitry Sankouski | 4cbc16c | 2021-10-17 13:44:31 +0300 | [diff] [blame] | 53 | }; |
| 54 | }; |
| 55 | |
| 56 | debug_uart: serial@a84000 { |
| 57 | compatible = "qcom,msm-geni-uart"; |
| 58 | reg = <0xa84000 0x4000>; |
| 59 | reg-names = "se_phys"; |
| 60 | clock-names = "se-clk"; |
| 61 | clocks = <&gcc 0x58>; |
| 62 | pinctrl-names = "default"; |
| 63 | pinctrl-0 = <&qup_uart9>; |
| 64 | qcom,wrapper-core = <0x8a>; |
| 65 | status = "disabled"; |
| 66 | }; |
| 67 | |
| 68 | spmi@c440000 { |
| 69 | compatible = "qcom,spmi-pmic-arb"; |
| 70 | reg = <0xc440000 0x1100>, |
| 71 | <0xc600000 0x2000000>, |
| 72 | <0xe600000 0x100000>; |
| 73 | reg-names = "cnfg", "core", "obsrvr"; |
| 74 | #address-cells = <0x1>; |
| 75 | #size-cells = <0x1>; |
| 76 | |
| 77 | qcom,revid@100 { |
| 78 | compatible = "qcom,qpnp-revid"; |
| 79 | reg = <0x100 0x100>; |
| 80 | }; |
| 81 | |
| 82 | pmic0: pm8998@0 { |
| 83 | compatible = "qcom,spmi-pmic"; |
| 84 | reg = <0x0 0x1>; |
| 85 | #address-cells = <0x1>; |
| 86 | #size-cells = <0x1>; |
| 87 | |
| 88 | pm8998_pon: pm8998_pon@800 { |
| 89 | compatible = "qcom,pm8998-pwrkey"; |
| 90 | reg = <0x800 0x100>; |
| 91 | #gpio-cells = <2>; |
| 92 | gpio-controller; |
| 93 | gpio-bank-name = "pm8998_key."; |
| 94 | }; |
| 95 | |
| 96 | pm8998_gpios: pm8998_gpios@c000 { |
| 97 | compatible = "qcom,pm8998-gpio"; |
| 98 | reg = <0xc000 0x1a00>; |
| 99 | gpio-controller; |
| 100 | gpio-count = <21>; |
| 101 | #gpio-cells = <2>; |
| 102 | gpio-bank-name = "pm8998."; |
| 103 | }; |
| 104 | }; |
| 105 | |
| 106 | pmic1: pm8998@1 { |
| 107 | compatible = "qcom,spmi-pmic"; |
| 108 | reg = <0x1 0x0>; |
| 109 | #address-cells = <0x2>; |
| 110 | #size-cells = <0x0>; |
| 111 | }; |
| 112 | }; |
| 113 | }; |
| 114 | }; |