blob: 9af8bd5b57af25b9d0db89f11e1b43671c5e740a [file] [log] [blame]
Valentin Longchamp877bfe32013-10-18 11:47:24 +02001#
2# Copyright 2012 Freescale Semiconductor, Inc.
3#
4# SPDX-License-Identifier: GPL-2.0+
5#
6# Refer docs/README.pblimage for more details about how-to configure
7# and create PBL boot image
8#
9
10#PBI commands
Valentin Longchampfabb9292014-01-27 11:49:07 +010011#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
12#Freescale's errarta sheet suggests it may be done with PBI
1309000010 00000000
1409000014 00000000
1509000018 81d00000
1609021008 0000f000
1709021028 0000f000
1809021048 0000f000
1909021068 0000f000
2009000018 00000000
Valentin Longchamp877bfe32013-10-18 11:47:24 +020021#Initialize CPC1 as 1MB SRAM
2209010000 00200400
2309138000 00000000
24091380c0 00000100
2509010100 00000000
2609010104 fff0000b
2709010f00 08000000
2809010000 80000000
29#Configure LAW for CPC1
3009000d00 00000000
3109000d04 fff00000
3209000d08 81000013
3309000010 00000000
3409000014 ff000000
3509000018 81000000
36#Initialize eSPI controller, default configuration is slow for eSPI to
37#load data, this configuration comes from u-boot eSPI driver.
3809110000 80000403
3909110020 27170008
4009110024 00100008
4109110028 00100008
420911002c 00100008
43#Flush PBL data
4409138000 00000000
45091380c0 00000000