blob: 22324f97b3d9412c82224a7aa9208af03bed0868 [file] [log] [blame]
Kever Yangb6474422017-06-23 17:17:51 +08001/*
2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/clock/rk3228-cru.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 interrupt-parent = <&gic>;
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
Kever Yanga2a1bfe2017-07-21 18:21:09 +080024 mmc0 = &emmc;
25 mmc1 = &sdmmc;
Kever Yangb6474422017-06-23 17:17:51 +080026 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu0: cpu@f00 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a7";
35 reg = <0xf00>;
36 resets = <&cru SRST_CORE0>;
37 operating-points = <
38 /* KHz uV */
39 816000 1000000
40 >;
41 #cooling-cells = <2>; /* min followed by max */
42 clock-latency = <40000>;
43 clocks = <&cru ARMCLK>;
44 };
45
46 cpu1: cpu@f01 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a7";
49 reg = <0xf01>;
50 resets = <&cru SRST_CORE1>;
51 };
52
53 cpu2: cpu@f02 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0xf02>;
57 resets = <&cru SRST_CORE2>;
58 };
59
60 cpu3: cpu@f03 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a7";
63 reg = <0xf03>;
64 resets = <&cru SRST_CORE3>;
65 };
66 };
67
68 amba {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges;
73
74 pdma: pdma@110f0000 {
75 compatible = "arm,pl330", "arm,primecell";
76 reg = <0x110f0000 0x4000>;
77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
79 #dma-cells = <1>;
80 clocks = <&cru ACLK_DMAC>;
81 clock-names = "apb_pclk";
82 };
83 };
84
85 arm-pmu {
86 compatible = "arm,cortex-a7-pmu";
87 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
91 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
92 };
93
94 timer {
95 compatible = "arm,armv7-timer";
96 arm,cpu-registers-not-fw-configured;
97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
98 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
99 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
100 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
101 clock-frequency = <24000000>;
102 };
103
104 xin24m: oscillator {
105 compatible = "fixed-clock";
106 clock-frequency = <24000000>;
107 clock-output-names = "xin24m";
108 #clock-cells = <0>;
109 };
110
111 bus_intmem@10080000 {
112 compatible = "mmio-sram";
113 reg = <0x10080000 0x9000>;
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges = <0 0x10080000 0x9000>;
117 smp-sram@0 {
118 compatible = "rockchip,rk322x-smp-sram";
119 reg = <0x00 0x10>;
120 };
121 ddr_sram: ddr-sram@1000 {
122 compatible = "rockchip,rk322x-ddr-sram";
123 reg = <0x1000 0x8000>;
124 };
125 };
126
127 i2s1: i2s1@100b0000 {
128 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
129 reg = <0x100b0000 0x4000>;
130 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
131 #address-cells = <1>;
132 #size-cells = <0>;
133 clock-names = "i2s_clk", "i2s_hclk";
134 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
135 dmas = <&pdma 14>, <&pdma 15>;
136 dma-names = "tx", "rx";
137 pinctrl-names = "default";
138 pinctrl-0 = <&i2s1_bus>;
139 status = "disabled";
140 };
141
142 i2s0: i2s0@100c0000 {
143 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
144 reg = <0x100c0000 0x4000>;
145 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 clock-names = "i2s_clk", "i2s_hclk";
149 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
150 dmas = <&pdma 11>, <&pdma 12>;
151 dma-names = "tx", "rx";
152 status = "disabled";
153 };
154
155 i2s2: i2s2@100e0000 {
156 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
157 reg = <0x100e0000 0x4000>;
158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 clock-names = "i2s_clk", "i2s_hclk";
162 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
163 dmas = <&pdma 0>, <&pdma 1>;
164 dma-names = "tx", "rx";
165 status = "disabled";
166 };
167
168 grf: syscon@11000000 {
169 u-boot,dm-pre-reloc;
170 compatible = "rockchip,rk3228-grf", "syscon";
171 reg = <0x11000000 0x1000>;
172 };
173
174 uart0: serial@11010000 {
175 compatible = "snps,dw-apb-uart";
176 reg = <0x11010000 0x100>;
177 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
178 clock-frequency = <24000000>;
179 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
180 clock-names = "baudclk", "apb_pclk";
181 pinctrl-names = "default";
182 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
183 reg-shift = <2>;
184 reg-io-width = <4>;
185 status = "disabled";
186 };
187
188 uart1: serial@11020000 {
189 compatible = "snps,dw-apb-uart";
190 reg = <0x11020000 0x100>;
191 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
192 clock-frequency = <24000000>;
193 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
194 clock-names = "baudclk", "apb_pclk";
195 pinctrl-names = "default";
196 pinctrl-0 = <&uart1_xfer>;
197 reg-shift = <2>;
198 reg-io-width = <4>;
199 status = "disabled";
200 };
201
202 uart2: serial@11030000 {
203 compatible = "snps,dw-apb-uart";
204 reg = <0x11030000 0x100>;
205 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
206 clock-frequency = <24000000>;
207 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
208 clock-names = "baudclk", "apb_pclk";
209 pinctrl-names = "default";
210 pinctrl-0 = <&uart2_xfer>;
211 reg-shift = <2>;
212 reg-io-width = <4>;
213 status = "disabled";
214 };
215
216 i2c0: i2c@11050000 {
217 compatible = "rockchip,rk3228-i2c";
218 reg = <0x11050000 0x1000>;
219 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
220 #address-cells = <1>;
221 #size-cells = <0>;
222 clock-names = "i2c";
223 clocks = <&cru PCLK_I2C0>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&i2c0_xfer>;
226 status = "disabled";
227 };
228
229 i2c1: i2c@11060000 {
230 compatible = "rockchip,rk3228-i2c";
231 reg = <0x11060000 0x1000>;
232 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 clock-names = "i2c";
236 clocks = <&cru PCLK_I2C1>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&i2c1_xfer>;
239 status = "disabled";
240 };
241
242 i2c2: i2c@11070000 {
243 compatible = "rockchip,rk3228-i2c";
244 reg = <0x11070000 0x1000>;
245 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 clock-names = "i2c";
249 clocks = <&cru PCLK_I2C2>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&i2c2_xfer>;
252 status = "disabled";
253 };
254
255 i2c3: i2c@11080000 {
256 compatible = "rockchip,rk3228-i2c";
257 reg = <0x11080000 0x1000>;
258 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 clock-names = "i2c";
262 clocks = <&cru PCLK_I2C3>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&i2c3_xfer>;
265 status = "disabled";
266 };
267
268 pwm0: pwm@110b0000 {
269 compatible = "rockchip,rk3288-pwm";
270 reg = <0x110b0000 0x10>;
271 #pwm-cells = <3>;
272 clocks = <&cru PCLK_PWM>;
273 clock-names = "pwm";
274 pinctrl-names = "default";
275 pinctrl-0 = <&pwm0_pin>;
276 status = "disabled";
277 };
278
279 pwm1: pwm@110b0010 {
280 compatible = "rockchip,rk3288-pwm";
281 reg = <0x110b0010 0x10>;
282 #pwm-cells = <3>;
283 clocks = <&cru PCLK_PWM>;
284 clock-names = "pwm";
285 pinctrl-names = "default";
286 pinctrl-0 = <&pwm1_pin>;
287 status = "disabled";
288 };
289
290 pwm2: pwm@110b0020 {
291 compatible = "rockchip,rk3288-pwm";
292 reg = <0x110b0020 0x10>;
293 #pwm-cells = <3>;
294 clocks = <&cru PCLK_PWM>;
295 clock-names = "pwm";
296 pinctrl-names = "default";
297 pinctrl-0 = <&pwm2_pin>;
298 status = "disabled";
299 };
300
301 pwm3: pwm@110b0030 {
302 compatible = "rockchip,rk3288-pwm";
303 reg = <0x110b0030 0x10>;
304 #pwm-cells = <2>;
305 clocks = <&cru PCLK_PWM>;
306 clock-names = "pwm";
307 pinctrl-names = "default";
308 pinctrl-0 = <&pwm3_pin>;
309 status = "disabled";
310 };
311
312 timer: timer@110c0000 {
313 compatible = "rockchip,rk3288-timer";
314 reg = <0x110c0000 0x20>;
315 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&xin24m>, <&cru PCLK_TIMER>;
317 clock-names = "timer", "pclk";
318 };
319
320 cru: clock-controller@110e0000 {
321 u-boot,dm-pre-reloc;
322 compatible = "rockchip,rk3228-cru";
323 reg = <0x110e0000 0x1000>;
324 rockchip,grf = <&grf>;
325 #clock-cells = <1>;
326 #reset-cells = <1>;
327 assigned-clocks = <&cru PLL_GPLL>;
328 assigned-clock-rates = <594000000>;
329 };
330
331 thermal-zones {
332 cpu_thermal: cpu-thermal {
333 polling-delay-passive = <100>; /* milliseconds */
334 polling-delay = <5000>; /* milliseconds */
335
336 thermal-sensors = <&tsadc 0>;
337
338 trips {
339 cpu_alert0: cpu_alert0 {
340 temperature = <70000>; /* millicelsius */
341 hysteresis = <2000>; /* millicelsius */
342 type = "passive";
343 };
344 cpu_alert1: cpu_alert1 {
345 temperature = <75000>; /* millicelsius */
346 hysteresis = <2000>; /* millicelsius */
347 type = "passive";
348 };
349 cpu_crit: cpu_crit {
350 temperature = <90000>; /* millicelsius */
351 hysteresis = <2000>; /* millicelsius */
352 type = "critical";
353 };
354 };
355
356 cooling-maps {
357 map0 {
358 trip = <&cpu_alert0>;
359 cooling-device =
360 <&cpu0 THERMAL_NO_LIMIT 6>;
361 };
362 map1 {
363 trip = <&cpu_alert1>;
364 cooling-device =
365 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
366 };
367 };
368 };
369 };
370
371 tsadc: tsadc@11150000 {
372 compatible = "rockchip,rk3228-tsadc";
373 reg = <0x11150000 0x100>;
374 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
376 clock-names = "tsadc", "apb_pclk";
377 resets = <&cru SRST_TSADC>;
378 reset-names = "tsadc-apb";
379 pinctrl-names = "init", "default", "sleep";
380 pinctrl-0 = <&otp_gpio>;
381 pinctrl-1 = <&otp_out>;
382 pinctrl-2 = <&otp_gpio>;
383 #thermal-sensor-cells = <0>;
384 rockchip,hw-tshut-temp = <95000>;
385 status = "disabled";
386 };
387
Kever Yanga2a1bfe2017-07-21 18:21:09 +0800388 sdmmc: dwmmc@30000000 {
389 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
390 reg = <0x30000000 0x4000>;
Kever Yang95ca1002017-07-27 12:54:00 +0800391 max-frequency = <150000000>;
Kever Yanga2a1bfe2017-07-21 18:21:09 +0800392 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
394 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
395 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
396 fifo-depth = <0x100>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
399 status = "disabled";
400 };
401
402 sdio: dwmmc@30010000 {
403 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
404 reg = <0x30010000 0x4000>;
405 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
407 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
408 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
409 fifo-depth = <0x100>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
412 status = "disabled";
413 };
414
Kever Yangb6474422017-06-23 17:17:51 +0800415 emmc: dwmmc@30020000 {
416 compatible = "rockchip,rk3288-dw-mshc";
417 reg = <0x30020000 0x4000>;
Kever Yang95ca1002017-07-27 12:54:00 +0800418 max-frequency = <150000000>;
Kever Yangb6474422017-06-23 17:17:51 +0800419 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
Kever Yangb6474422017-06-23 17:17:51 +0800420 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
421 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
422 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
423 bus-width = <8>;
424 default-sample-phase = <158>;
425 num-slots = <1>;
426 fifo-depth = <0x100>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
429 resets = <&cru SRST_EMMC>;
430 reset-names = "reset";
431 status = "disabled";
432 };
433
Meng Dongyang01240622017-07-13 10:59:54 +0800434 usb20_otg: usb@30040000 {
435 compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
436 "snps,dwc2";
437 reg = <0x30040000 0x40000>;
438 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
439 hnp-srp-disable;
440 dr_mode = "otg";
441 status = "disabled";
442 };
443
Kever Yangb6474422017-06-23 17:17:51 +0800444 gmac: ethernet@30200000 {
445 compatible = "rockchip,rk3228-gmac";
446 reg = <0x30200000 0x10000>;
447 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-names = "macirq";
449 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
450 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
451 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
452 <&cru PCLK_GMAC>;
453 clock-names = "stmmaceth", "mac_clk_rx",
454 "mac_clk_tx", "clk_mac_ref",
455 "clk_mac_refout", "aclk_mac",
456 "pclk_mac";
457 resets = <&cru SRST_GMAC>;
458 reset-names = "stmmaceth";
459 rockchip,grf = <&grf>;
460 status = "disabled";
461 };
462
463 gic: interrupt-controller@32010000 {
464 compatible = "arm,gic-400";
465 interrupt-controller;
466 #interrupt-cells = <3>;
467 #address-cells = <0>;
468
469 reg = <0x32011000 0x1000>,
470 <0x32012000 0x2000>,
471 <0x32014000 0x2000>,
472 <0x32016000 0x2000>;
473 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
474 };
475
476 pinctrl: pinctrl {
477 compatible = "rockchip,rk3228-pinctrl";
478 rockchip,grf = <&grf>;
479 #address-cells = <1>;
480 #size-cells = <1>;
481 ranges;
482
483 gpio0: gpio0@11110000 {
484 compatible = "rockchip,gpio-bank";
485 reg = <0x11110000 0x100>;
486 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru PCLK_GPIO0>;
488
489 gpio-controller;
490 #gpio-cells = <2>;
491
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 };
495
496 gpio1: gpio1@11120000 {
497 compatible = "rockchip,gpio-bank";
498 reg = <0x11120000 0x100>;
499 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cru PCLK_GPIO1>;
501
502 gpio-controller;
503 #gpio-cells = <2>;
504
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 };
508
509 gpio2: gpio2@11130000 {
510 compatible = "rockchip,gpio-bank";
511 reg = <0x11130000 0x100>;
512 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cru PCLK_GPIO2>;
514
515 gpio-controller;
516 #gpio-cells = <2>;
517
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 };
521
522 gpio3: gpio3@11140000 {
523 compatible = "rockchip,gpio-bank";
524 reg = <0x11140000 0x100>;
525 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cru PCLK_GPIO3>;
527
528 gpio-controller;
529 #gpio-cells = <2>;
530
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 };
534
535 pcfg_pull_up: pcfg-pull-up {
536 bias-pull-up;
537 };
538
539 pcfg_pull_down: pcfg-pull-down {
540 bias-pull-down;
541 };
542
543 pcfg_pull_none: pcfg-pull-none {
544 bias-disable;
545 };
546
547 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
548 drive-strength = <12>;
549 };
550
Kever Yanga2a1bfe2017-07-21 18:21:09 +0800551 sdmmc {
552 sdmmc_clk: sdmmc-clk {
553 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
554 };
555
556 sdmmc_cmd: sdmmc-cmd {
557 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
558 };
559
560 sdmmc_bus4: sdmmc-bus4 {
561 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
562 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
563 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
564 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
565 };
566 };
567
568 sdio {
569 sdio_clk: sdio-clk {
570 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
571 };
572
573 sdio_cmd: sdio-cmd {
574 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
575 };
576
577 sdio_bus4: sdio-bus4 {
578 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
579 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
580 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
581 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
582 };
583 };
584
Kever Yangb6474422017-06-23 17:17:51 +0800585 emmc {
586 emmc_clk: emmc-clk {
587 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
588 };
589
590 emmc_cmd: emmc-cmd {
591 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
592 };
593
594 emmc_bus8: emmc-bus8 {
595 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,
596 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,
597 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,
598 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,
599 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,
600 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
601 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,
602 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
603 };
604 };
605
606 gmac {
607 rgmii_pins: rgmii-pins {
608 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
609 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
610 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
611 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
612 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
613 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
614 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
615 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
616 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
617 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
618 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
619 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
620 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
621 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
622 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
623 };
624
625 rmii_pins: rmii-pins {
626 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
627 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
628 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
629 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
630 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
631 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
632 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
633 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
634 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
635 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
636 };
637
638 phy_pins: phy-pins {
639 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,
640 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
641 };
642 };
643
644 i2c0 {
645 i2c0_xfer: i2c0-xfer {
646 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
647 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
648 };
649 };
650
651 i2c1 {
652 i2c1_xfer: i2c1-xfer {
653 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
654 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
655 };
656 };
657
658 i2c2 {
659 i2c2_xfer: i2c2-xfer {
660 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
661 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
662 };
663 };
664
665 i2c3 {
666 i2c3_xfer: i2c3-xfer {
667 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
668 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
669 };
670 };
671
672 i2s1 {
673 i2s1_bus: i2s1-bus {
674 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
675 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
676 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
677 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
678 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
679 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
680 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
681 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
682 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
683 };
684 };
685
686 pwm0 {
687 pwm0_pin: pwm0-pin {
688 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
689 };
690 };
691
692 pwm1 {
693 pwm1_pin: pwm1-pin {
694 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
695 };
696 };
697
698 pwm2 {
699 pwm2_pin: pwm2-pin {
700 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
701 };
702 };
703
704 pwm3 {
705 pwm3_pin: pwm3-pin {
706 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
707 };
708 };
709
710 tsadc {
711 otp_gpio: otp-gpio {
712 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
713 };
714
715 otp_out: otp-out {
716 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
717 };
718 };
719
720 uart0 {
721 uart0_xfer: uart0-xfer {
722 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
723 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
724 };
725
726 uart0_cts: uart0-cts {
727 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
728 };
729
730 uart0_rts: uart0-rts {
731 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
732 };
733 };
734
735 uart1 {
736 uart1_xfer: uart1-xfer {
737 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
738 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
739 };
740
741 uart1_cts: uart1-cts {
742 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
743 };
744
745 uart1_rts: uart1-rts {
746 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
747 };
748 };
749
750 uart2 {
751 uart2_xfer: uart2-xfer {
752 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
753 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
754 };
755
756 uart2_cts: uart2-cts {
757 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
758 };
759
760 uart2_rts: uart2-rts {
761 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
762 };
763 };
764 };
765
766 dmc: dmc@11200000 {
767 u-boot,dm-pre-reloc;
768 compatible = "rockchip,rk3228-dmc", "syscon";
769 rockchip,cru = <&cru>;
770 rockchip,grf = <&grf>;
771 rockchip,msch = <&service_msch>;
772 reg = <0x11200000 0x3fc
773 0x12000000 0x400>;
774 rockchip,sram = <&ddr_sram>;
775 };
776
777 service_msch: syscon@31090000 {
778 u-boot,dm-pre-reloc;
779 compatible = "rockchip,rk3228-msch", "syscon";
780 reg = <0x31090000 0x2000>;
781 };
782};