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Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +08001/*
2 * (C) Copyright 2009 Faraday Technology
3 * Po-Yu Chuang <ratbert@faraday-tech.com>
4 *
5 * Configuation settings for the Faraday A320 board.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25#include <asm/arch/a320.h>
26
Po-Yu Chuang78991472011-07-18 16:55:39 +000027/*
Po-Yu Chuangfd90b0d2011-07-18 16:56:53 +000028 * Linux kernel tagged list
29 */
30#define CONFIG_CMDLINE_TAG
31#define CONFIG_SETUP_MEMORY_TAGS
32
33/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080034 * CPU and Board Configuration Options
35 */
36#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
37
38#undef CONFIG_SKIP_LOWLEVEL_INIT
39
Po-Yu Chuang78991472011-07-18 16:55:39 +000040/*
Po-Yu Chuang8dc667c2011-02-17 19:35:23 +000041 * Power Management Unit
42 */
43#define CONFIG_FTPMU010_POWER
44
Po-Yu Chuang78991472011-07-18 16:55:39 +000045/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080046 * Timer
47 */
48#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
49
Po-Yu Chuang78991472011-07-18 16:55:39 +000050/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080051 * Real Time Clock
52 */
53#define CONFIG_RTC_FTRTC010
54
Po-Yu Chuang78991472011-07-18 16:55:39 +000055/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080056 * Serial console configuration
57 */
58
59/* FTUART is a high speed NS 16C550A compatible UART */
60#define CONFIG_BAUDRATE 38400
61#define CONFIG_CONS_INDEX 1
62#define CONFIG_SYS_NS16550
63#define CONFIG_SYS_NS16550_SERIAL
64#define CONFIG_SYS_NS16550_COM1 0x98200000
65#define CONFIG_SYS_NS16550_REG_SIZE -4
66#define CONFIG_SYS_NS16550_CLK 18432000
67
68/* valid baudrates */
69#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
70
Po-Yu Chuang78991472011-07-18 16:55:39 +000071/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080072 * Ethernet
73 */
74#define CONFIG_NET_MULTI
75#define CONFIG_FTMAC100
76
77#define CONFIG_BOOTDELAY 3
78
Po-Yu Chuang78991472011-07-18 16:55:39 +000079/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080080 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#define CONFIG_CMD_CACHE
85#define CONFIG_CMD_DATE
86#define CONFIG_CMD_PING
87
Po-Yu Chuang78991472011-07-18 16:55:39 +000088/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080089 * Miscellaneous configurable options
90 */
91#define CONFIG_SYS_LONGHELP /* undef to save memory */
92#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
93#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
94
95/* Print Buffer Size */
96#define CONFIG_SYS_PBSIZE \
97 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
98
99/* max number of command args */
100#define CONFIG_SYS_MAXARGS 16
101
102/* Boot Argument Buffer Size */
103#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
104
Po-Yu Chuang78991472011-07-18 16:55:39 +0000105/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800106 * Stack sizes
107 *
108 * The stack sizes are set up in start.S using the settings below
109 */
110#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
111#ifdef CONFIG_USE_IRQ
112#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
113#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
114#endif
115
Po-Yu Chuang78991472011-07-18 16:55:39 +0000116/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800117 * Size of malloc() pool
118 */
119#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
120
Po-Yu Chuang78991472011-07-18 16:55:39 +0000121/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800122 * SDRAM controller configuration
123 */
124#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
125 FTSDMC020_TP0_TRP(1) | \
126 FTSDMC020_TP0_TRCD(1) | \
127 FTSDMC020_TP0_TRF(3) | \
128 FTSDMC020_TP0_TWR(1) | \
129 FTSDMC020_TP0_TCL(2))
130
131#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
132 FTSDMC020_TP1_INI_REFT(8) | \
133 FTSDMC020_TP1_REF_INTV(0x180))
134
135#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
136 FTSDMC020_BANK_DDW_X16 | \
137 FTSDMC020_BANK_DSZ_256M | \
138 FTSDMC020_BANK_MBW_32 | \
139 FTSDMC020_BANK_SIZE_64M)
140
Po-Yu Chuang78991472011-07-18 16:55:39 +0000141/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800142 * Physical Memory Map
143 */
144#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
145#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
146#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
147
Po-Yu Chuang5eb522a2010-12-19 23:07:23 +0000148#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
149#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
150 GENERATED_GBL_DATA_SIZE)
151
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800152/*
153 * Load address and memory test area should agree with
154 * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
155 */
Po-Yu Chuang5eb522a2010-12-19 23:07:23 +0000156#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800157
158/* memtest works on 63 MB in DRAM */
Po-Yu Chuang5eb522a2010-12-19 23:07:23 +0000159#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
160#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
161
162#define CONFIG_SYS_TEXT_BASE 0
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800163
Po-Yu Chuang78991472011-07-18 16:55:39 +0000164/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800165 * Static memory controller configuration
166 */
167
Macpaul Lin00d10eb2011-04-15 21:37:11 +0000168#define CONFIG_FTSMC020
169#include <faraday/ftsmc020.h>
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800170
171#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
172 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
173 FTSMC020_BANK_SIZE_1M | \
174 FTSMC020_BANK_MBW_8)
175
176#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
177 FTSMC020_TPR_AST(3) | \
178 FTSMC020_TPR_CTW(3) | \
179 FTSMC020_TPR_ATI(0xf) | \
180 FTSMC020_TPR_AT2(3) | \
181 FTSMC020_TPR_WTC(3) | \
182 FTSMC020_TPR_AHT(3) | \
183 FTSMC020_TPR_TRNA(0xf))
184
185#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
186 FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
187 FTSMC020_BANK_SIZE_32M | \
188 FTSMC020_BANK_MBW_32)
189
190#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
191 FTSMC020_TPR_CTW(3) | \
192 FTSMC020_TPR_ATI(0xf) | \
193 FTSMC020_TPR_AT2(3) | \
194 FTSMC020_TPR_WTC(3) | \
195 FTSMC020_TPR_AHT(3) | \
196 FTSMC020_TPR_TRNA(0xf))
197
198#define CONFIG_SYS_FTSMC020_CONFIGS { \
199 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
200 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
201}
202
Po-Yu Chuang78991472011-07-18 16:55:39 +0000203/*
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800204 * FLASH and environment organization
205 */
206
207/* use CFI framework */
208#define CONFIG_SYS_FLASH_CFI
209#define CONFIG_FLASH_CFI_DRIVER
210
211/* support JEDEC */
212#define CONFIG_FLASH_CFI_LEGACY
213#define CONFIG_SYS_FLASH_LEGACY_512Kx8
214
215#define PHYS_FLASH_1 0x00000000
216#define PHYS_FLASH_2 0x00400000
217#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
218#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
219
220#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
221
222/* max number of memory banks */
223#define CONFIG_SYS_MAX_FLASH_BANKS 2
224
225/* max number of sectors on one chip */
226#define CONFIG_SYS_MAX_FLASH_SECT 512
227
228#undef CONFIG_SYS_FLASH_EMPTY_INFO
229
230/* environments */
231#define CONFIG_ENV_IS_IN_FLASH
Po-Yu Chuang5eb522a2010-12-19 23:07:23 +0000232#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800233#define CONFIG_ENV_SIZE 0x20000
234
235#endif /* __CONFIG_H */