blob: 2ed66261d28680cf6536ad57585201749930130a [file] [log] [blame]
Marcel Ziswiler3d603662019-05-31 19:00:20 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Toradex
4 */
5
6#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07007#include <cpu_func.h>
Simon Glass52559322019-11-14 12:57:46 -07008#include <init.h>
Marcel Ziswiler3d603662019-05-31 19:00:20 +03009
10#include <asm/arch/clock.h>
11#include <asm/arch/imx8-pins.h>
12#include <asm/arch/iomux.h>
13#include <asm/arch/sci/sci.h>
14#include <asm/arch/sys_proto.h>
15#include <asm/gpio.h>
16#include <asm/io.h>
Simon Glass9fb625c2019-08-01 09:46:51 -060017#include <env.h>
Marcel Ziswiler3d603662019-05-31 19:00:20 +030018#include <errno.h>
19#include <linux/libfdt.h>
20
21#include "../common/tdx-cfg-block.h"
22
23DECLARE_GLOBAL_DATA_PTR;
24
25#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
26 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
27 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
28 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
29
30static iomux_cfg_t uart1_pads[] = {
31 SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
32 SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
33};
34
35static void setup_iomux_uart(void)
36{
37 imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
38}
39
Igor Opaniuk90311be2020-10-22 11:21:41 +030040void board_mem_get_layout(u64 *phys_sdram_1_start,
41 u64 *phys_sdram_1_size,
42 u64 *phys_sdram_2_start,
43 u64 *phys_sdram_2_size)
44{
45 u32 is_quadplus = 0, val = 0;
46 sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
47
48 if (scierr == SC_ERR_NONE) {
49 /* QP has one A72 core disabled */
50 is_quadplus = ((val >> 4) & 0x3) != 0x0;
51 }
52
53 *phys_sdram_1_start = PHYS_SDRAM_1;
54 *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
55 *phys_sdram_2_start = PHYS_SDRAM_2;
56 if (is_quadplus)
57 /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */
58 *phys_sdram_2_size = 0x0UL;
59 else
60 *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
61}
62
Marcel Ziswiler3d603662019-05-31 19:00:20 +030063int board_early_init_f(void)
64{
Anatolij Gustschin64b5f462019-06-12 13:35:25 +020065 sc_pm_clock_rate_t rate = SC_80MHZ;
Marcel Ziswiler3d603662019-05-31 19:00:20 +030066 sc_err_t err = 0;
67
Anatolij Gustschin64b5f462019-06-12 13:35:25 +020068 /* Set UART1 clock root to 80 MHz and enable it */
69 err = sc_pm_setup_uart(SC_R_UART_1, rate);
Marcel Ziswiler3d603662019-05-31 19:00:20 +030070 if (err != SC_ERR_NONE)
71 return 0;
72
73 setup_iomux_uart();
74
75 return 0;
76}
77
Simon Glassbcee8d62019-12-06 21:41:35 -070078#if CONFIG_IS_ENABLED(DM_GPIO)
Marcel Ziswiler3d603662019-05-31 19:00:20 +030079static void board_gpio_init(void)
80{
81 /* TODO */
82}
83#else
84static inline void board_gpio_init(void) {}
85#endif
86
87#if IS_ENABLED(CONFIG_FEC_MXC)
88#include <miiphy.h>
89
90int board_phy_config(struct phy_device *phydev)
91{
92 if (phydev->drv->config)
93 phydev->drv->config(phydev);
94
95 return 0;
96}
97#endif
98
Marcel Ziswiler3d603662019-05-31 19:00:20 +030099int checkboard(void)
100{
101 puts("Model: Toradex Apalis iMX8\n");
102
103 build_info();
104 print_bootinfo();
105
106 return 0;
107}
108
109int board_init(void)
110{
111 board_gpio_init();
112
113 return 0;
114}
115
Marcel Ziswiler3d603662019-05-31 19:00:20 +0300116/*
117 * Board specific reset that is system reset.
118 */
119void reset_cpu(ulong addr)
120{
121 /* TODO */
122}
123
124#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900125int ft_board_setup(void *blob, struct bd_info *bd)
Marcel Ziswiler3d603662019-05-31 19:00:20 +0300126{
127 return ft_common_board_setup(blob, bd);
128}
129#endif
130
131int board_mmc_get_env_dev(int devno)
132{
133 return devno;
134}
135
136int board_late_init(void)
137{
138#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
139/* TODO move to common */
140 env_set("board_name", "Apalis iMX8QM");
141 env_set("board_rev", "v1.0");
142#endif
143
144 return 0;
145}