blob: 3fd334a54d35364924ff54816055099c4dc09df3 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05302/*
3 * (C) Copyright 2015 Xilinx, Inc,
Michal Simek174d72842023-07-10 14:35:49 +02004 * Michal Simek <michal.simek@amd.com>
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05305 */
6
7#ifndef _ZYNQMPPL_H_
8#define _ZYNQMPPL_H_
9
10#include <xilinx.h>
Simon Glasscd93d622020-05-10 11:40:13 -060011#include <linux/bitops.h>
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053012
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053013#define ZYNQMP_FPGA_OP_INIT (1 << 0)
14#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
15#define ZYNQMP_FPGA_OP_DONE (1 << 2)
16
Siva Durga Prasad Paladugua18d09e2018-05-31 15:10:23 +053017#define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2)
18#define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3)
19
Soren Brinkmann0cba6ab2016-09-29 11:44:41 -070020#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
21#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
22 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
23#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
Michal Simek92687042017-06-28 15:40:32 +020024#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
Soren Brinkmann0cba6ab2016-09-29 11:44:41 -070025
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053026extern struct xilinx_fpga_op zynqmp_op;
27
Oleksandr Suvorova3a1afb2022-07-22 17:16:13 +030028#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
Adrian Fiergolskib524f8f2022-07-22 17:16:14 +030029#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | \
30 FPGA_XILINX_ZYNQMP_DDRAUTH | \
31 FPGA_XILINX_ZYNQMP_ENC)
Oleksandr Suvorova3a1afb2022-07-22 17:16:13 +030032#else
Oleksandr Suvorovd7fcbfc2022-07-22 17:16:04 +030033#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY)
Oleksandr Suvorova3a1afb2022-07-22 17:16:13 +030034#endif
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053035
36#endif /* _ZYNQMPPL_H_ */