blob: e3a733f42f486acdcff1c6a97aef4e7bb348b887 [file] [log] [blame]
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
7 */
8
9#include <common.h>
10
Gabor Juhosfeaa6062013-05-22 03:57:42 +000011#include <asm/addrspace.h>
Gabor Juhos01564312013-05-22 03:57:38 +000012#include <asm/io.h>
13#include <asm/malta.h>
Gabor Juhosfeaa6062013-05-22 03:57:42 +000014#include <pci_gt64120.h>
Gabor Juhos01564312013-05-22 03:57:38 +000015
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000016phys_size_t initdram(int board_type)
17{
18 return CONFIG_SYS_MEM_SIZE;
19}
20
21int checkboard(void)
22{
23 puts("Board: MIPS Malta CoreLV (Qemu)\n");
24 return 0;
25}
Gabor Juhos01564312013-05-22 03:57:38 +000026
27void _machine_restart(void)
28{
29 void __iomem *reset_base;
30
31 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
32 __raw_writel(GORESET, reset_base);
33}
Gabor Juhosfeaa6062013-05-22 03:57:42 +000034
35void pci_init_board(void)
36{
37 set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
38
39 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
40 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
41 0x10000000, 0x10000000, 128 * 1024 * 1024,
42 0x00000000, 0x00000000, 0x20000);
43}