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Kumar Gala129ba612008-08-12 11:13:08 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
Kumar Gala129ba612008-08-12 11:13:08 -050010
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
Kumar Gala129ba612008-08-12 11:13:08 -050013
York Sun712cf7a2011-10-03 09:19:53 -070014struct board_specific_parameters {
Haiying Wang4ca06602008-10-03 12:37:41 -040015 u32 n_ranks;
York Sun712cf7a2011-10-03 09:19:53 -070016 u32 datarate_mhz_high;
Haiying Wang4ca06602008-10-03 12:37:41 -040017 u32 clk_adjust;
18 u32 cpo;
19 u32 write_data_delay;
Priyanka Jain0dd38a32013-09-25 10:41:19 +053020 u32 force_2t;
York Sun712cf7a2011-10-03 09:19:53 -070021};
Haiying Wang4ca06602008-10-03 12:37:41 -040022
York Sun634bc552011-03-17 11:18:11 -070023/*
York Sun712cf7a2011-10-03 09:19:53 -070024 * This table contains all valid speeds we want to override with board
25 * specific parameters. datarate_mhz_high values need to be in ascending order
26 * for each n_ranks group.
York Sun634bc552011-03-17 11:18:11 -070027 *
28 * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
29 * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
30 * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
31 * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
32 * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
York Sun712cf7a2011-10-03 09:19:53 -070033 *
34 * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
Haiying Wang4ca06602008-10-03 12:37:41 -040035 */
York Sun712cf7a2011-10-03 09:19:53 -070036static const struct board_specific_parameters udimm0[] = {
York Sun634bc552011-03-17 11:18:11 -070037 /*
York Sun712cf7a2011-10-03 09:19:53 -070038 * memory controller 0
39 * num| hi| clk| cpo|wrdata|2T
40 * ranks| mhz|adjst| | delay|
York Sun634bc552011-03-17 11:18:11 -070041 */
York Sun712cf7a2011-10-03 09:19:53 -070042 {2, 333, 8, 7, 5, 0},
43 {2, 400, 8, 9, 5, 0},
44 {2, 549, 8, 11, 5, 0},
45 {2, 680, 8, 10, 5, 0},
46 {2, 850, 8, 12, 5, 1},
47 {1, 333, 6, 7, 3, 0},
48 {1, 400, 6, 9, 3, 0},
49 {1, 549, 6, 11, 3, 0},
50 {1, 680, 1, 10, 5, 0},
51 {1, 850, 1, 12, 5, 0},
52 {}
Haiying Wang4ca06602008-10-03 12:37:41 -040053};
54
York Sun712cf7a2011-10-03 09:19:53 -070055static const struct board_specific_parameters udimm1[] = {
York Sun634bc552011-03-17 11:18:11 -070056 /*
York Sun712cf7a2011-10-03 09:19:53 -070057 * memory controller 1
58 * num| hi| clk| cpo|wrdata|2T
59 * ranks| mhz|adjst| | delay|
York Sun634bc552011-03-17 11:18:11 -070060 */
York Sun712cf7a2011-10-03 09:19:53 -070061 {2, 333, 8, 7, 5, 0},
62 {2, 400, 8, 9, 5, 0},
63 {2, 549, 8, 11, 5, 0},
64 {2, 680, 8, 11, 5, 0},
65 {2, 850, 8, 13, 5, 1},
66 {1, 333, 6, 7, 3, 0},
67 {1, 400, 6, 9, 3, 0},
68 {1, 549, 6, 11, 3, 0},
69 {1, 680, 1, 11, 6, 0},
70 {1, 850, 1, 13, 6, 0},
71 {}
72};
York Sun634bc552011-03-17 11:18:11 -070073
York Sun712cf7a2011-10-03 09:19:53 -070074static const struct board_specific_parameters *udimms[] = {
75 udimm0,
76 udimm1,
77};
78
79static const struct board_specific_parameters rdimm0[] = {
York Sun634bc552011-03-17 11:18:11 -070080 /*
York Sun712cf7a2011-10-03 09:19:53 -070081 * memory controller 0
82 * num| hi| clk| cpo|wrdata|2T
83 * ranks| mhz|adjst| | delay|
York Sun634bc552011-03-17 11:18:11 -070084 */
York Sun712cf7a2011-10-03 09:19:53 -070085 {2, 333, 4, 7, 3, 0},
86 {2, 400, 4, 9, 3, 0},
87 {2, 549, 4, 11, 3, 0},
88 {2, 680, 4, 10, 3, 0},
89 {2, 850, 4, 12, 3, 1},
90 {}
91};
92
93static const struct board_specific_parameters rdimm1[] = {
94 /*
95 * memory controller 1
96 * num| hi| clk| cpo|wrdata|2T
97 * ranks| mhz|adjst| | delay|
98 */
99 {2, 333, 4, 7, 3, 0},
100 {2, 400, 4, 9, 3, 0},
101 {2, 549, 4, 11, 3, 0},
102 {2, 680, 4, 11, 3, 0},
103 {2, 850, 4, 13, 3, 1},
104 {}
105};
106
107static const struct board_specific_parameters *rdimms[] = {
108 rdimm0,
109 rdimm1,
York Sun634bc552011-03-17 11:18:11 -0700110};
111
Haiying Wangdfb49102008-10-03 12:36:55 -0400112void fsl_ddr_board_options(memctl_options_t *popts,
113 dimm_params_t *pdimm,
114 unsigned int ctrl_num)
Kumar Gala129ba612008-08-12 11:13:08 -0500115{
York Sun712cf7a2011-10-03 09:19:53 -0700116 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
Haiying Wang4ca06602008-10-03 12:37:41 -0400117 ulong ddr_freq;
York Sun634bc552011-03-17 11:18:11 -0700118
York Sun712cf7a2011-10-03 09:19:53 -0700119 if (ctrl_num > 1) {
120 printf("Wrong parameter for controller number %d", ctrl_num);
121 return;
122 }
York Sun634bc552011-03-17 11:18:11 -0700123 if (!pdimm->n_ranks)
124 return;
125
York Sun712cf7a2011-10-03 09:19:53 -0700126 if (popts->registered_dimm_en)
127 pbsp = rdimms[ctrl_num];
128 else
129 pbsp = udimms[ctrl_num];
Kumar Gala129ba612008-08-12 11:13:08 -0500130
Haiying Wang4ca06602008-10-03 12:37:41 -0400131 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
132 * freqency and n_banks specified in board_specific_parameters table.
Kumar Gala129ba612008-08-12 11:13:08 -0500133 */
Haiying Wang4ca06602008-10-03 12:37:41 -0400134 ddr_freq = get_ddr_freq(0) / 1000000;
York Sun712cf7a2011-10-03 09:19:53 -0700135 while (pbsp->datarate_mhz_high) {
136 if (pbsp->n_ranks == pdimm->n_ranks) {
137 if (ddr_freq <= pbsp->datarate_mhz_high) {
138 popts->clk_adjust = pbsp->clk_adjust;
139 popts->cpo_override = pbsp->cpo;
140 popts->write_data_delay =
141 pbsp->write_data_delay;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530142 popts->twot_en = pbsp->force_2t;
York Sun712cf7a2011-10-03 09:19:53 -0700143 goto found;
144 }
145 pbsp_highest = pbsp;
Haiying Wang4ca06602008-10-03 12:37:41 -0400146 }
147 pbsp++;
148 }
Kumar Gala129ba612008-08-12 11:13:08 -0500149
York Sun712cf7a2011-10-03 09:19:53 -0700150 if (pbsp_highest) {
151 printf("Error: board specific timing not found "
152 "for data rate %lu MT/s!\n"
153 "Trying to use the highest speed (%u) parameters\n",
154 ddr_freq, pbsp_highest->datarate_mhz_high);
155 popts->clk_adjust = pbsp->clk_adjust;
156 popts->cpo_override = pbsp->cpo;
157 popts->write_data_delay = pbsp->write_data_delay;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530158 popts->twot_en = pbsp->force_2t;
York Sun712cf7a2011-10-03 09:19:53 -0700159 } else {
160 panic("DIMM is not supported by this board");
York Sun939e5bf2011-06-27 13:30:55 -0700161 }
York Sun634bc552011-03-17 11:18:11 -0700162
York Sun712cf7a2011-10-03 09:19:53 -0700163found:
Kumar Gala129ba612008-08-12 11:13:08 -0500164 /*
165 * Factors to consider for half-strength driver enable:
166 * - number of DIMMs installed
167 */
168 popts->half_strength_driver_enable = 0;
169}