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wdenk5b1d7132002-11-03 00:07:02 +00001/*
Wolfgang Denkcd0402a2010-11-20 15:07:45 +01002 * (C) Copyright 2000-2010
wdenk5b1d7132002-11-03 00:07:02 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetVia board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
38#define CONFIG_NETVIA 1 /* ...on a NetVia board */
wdenk5b1d7132002-11-03 00:07:02 +000039
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0x40000000
41
wdenk993cad92003-06-26 22:04:09 +000042#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
wdenk5b1d7132002-11-03 00:07:02 +000043#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44#undef CONFIG_8xx_CONS_SMC2
45#undef CONFIG_8xx_CONS_NONE
wdenk993cad92003-06-26 22:04:09 +000046#else
47#define CONFIG_8xx_CONS_NONE
48#define CONFIG_MAX3100_SERIAL
49#endif
50
wdenk5b1d7132002-11-03 00:07:02 +000051#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
52
wdenk04a85b32004-04-15 18:22:41 +000053#define CONFIG_XIN 10000000
54#define CONFIG_8xx_GCLK_FREQ 80000000
wdenk5b1d7132002-11-03 00:07:02 +000055
56#if 0
57#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58#else
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60#endif
61
62#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
63
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010064#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk5b1d7132002-11-03 00:07:02 +000065
66#undef CONFIG_BOOTARGS
67#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020068 "tftpboot; " \
69 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk5b1d7132002-11-03 00:07:02 +000071 "bootm"
72
73#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk5b1d7132002-11-03 00:07:02 +000075
76#undef CONFIG_WATCHDOG /* watchdog disabled */
77
78#define CONFIG_STATUS_LED 1 /* Status LED enabled */
79
wdenk993cad92003-06-26 22:04:09 +000080#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
81#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
82#endif
83
wdenk5b1d7132002-11-03 00:07:02 +000084#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
85
Jon Loeliger7be044e2007-07-09 21:24:19 -050086/*
87 * BOOTP options
88 */
89#define CONFIG_BOOTP_SUBNETMASK
90#define CONFIG_BOOTP_GATEWAY
91#define CONFIG_BOOTP_HOSTNAME
92#define CONFIG_BOOTP_BOOTPATH
93#define CONFIG_BOOTP_BOOTFILESIZE
94#define CONFIG_BOOTP_NISDOMAIN
95
wdenk5b1d7132002-11-03 00:07:02 +000096
97#undef CONFIG_MAC_PARTITION
98#undef CONFIG_DOS_PARTITION
99
100#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
101
Jon Loeligere18a1062007-07-08 14:21:43 -0500102
103/*
104 * Command line configuration.
105 */
106#include <config_cmd_default.h>
107
108#define CONFIG_CMD_DHCP
109#define CONFIG_CMD_PING
wdenk993cad92003-06-26 22:04:09 +0000110
111#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
Wolfgang Denk7640f412009-07-19 19:37:24 +0200112/* #define CONFIG_CMD_NAND */ /* disabled */
wdenk993cad92003-06-26 22:04:09 +0000113#endif
wdenk5b1d7132002-11-03 00:07:02 +0000114
Jon Loeligere18a1062007-07-08 14:21:43 -0500115
wdenkc837dcb2004-01-20 23:12:12 +0000116#define CONFIG_BOARD_EARLY_INIT_F 1
wdenk5b1d7132002-11-03 00:07:02 +0000117#define CONFIG_MISC_INIT_R
118
wdenk5b1d7132002-11-03 00:07:02 +0000119/*
120 * Miscellaneous configurable options
121 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_LONGHELP /* undef to save memory */
123#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere18a1062007-07-08 14:21:43 -0500124#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000126#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000128#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
130#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
134#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk5b1d7132002-11-03 00:07:02 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk5b1d7132002-11-03 00:07:02 +0000139
wdenk5b1d7132002-11-03 00:07:02 +0000140/*
141 * Low Level Configuration Settings
142 * (address mappings, register initial values, etc.)
143 * You should know what you are doing if you make changes here.
144 */
145/*-----------------------------------------------------------------------
146 * Internal Memory Mapped Register
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_IMMR 0xFF000000
wdenk5b1d7132002-11-03 00:07:02 +0000149
150/*-----------------------------------------------------------------------
151 * Definitions for initial stack pointer and data area (in DPRAM)
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200154#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200155#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk5b1d7132002-11-03 00:07:02 +0000157
158/*-----------------------------------------------------------------------
159 * Start addresses for the final memory configuration
160 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk5b1d7132002-11-03 00:07:02 +0000162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_SDRAM_BASE 0x00000000
164#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenk5b1d7132002-11-03 00:07:02 +0000165#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk5b1d7132002-11-03 00:07:02 +0000167#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk5b1d7132002-11-03 00:07:02 +0000169#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
171#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk5b1d7132002-11-03 00:07:02 +0000172
173/*
174 * For booting Linux, the board info and command line data
175 * have to be in the first 8 MB of memory, since this is
176 * the maximum mapped by the Linux kernel during initialization.
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk5b1d7132002-11-03 00:07:02 +0000179
180/*-----------------------------------------------------------------------
181 * FLASH organization
182 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
184#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk5b1d7132002-11-03 00:07:02 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
187#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk5b1d7132002-11-03 00:07:02 +0000188
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200189#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200190#define CONFIG_ENV_SECT_SIZE 0x10000
wdenk5b1d7132002-11-03 00:07:02 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200193#define CONFIG_ENV_SIZE 0x4000
wdenk993cad92003-06-26 22:04:09 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200196#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
wdenk993cad92003-06-26 22:04:09 +0000197
wdenk5b1d7132002-11-03 00:07:02 +0000198/*-----------------------------------------------------------------------
199 * Cache Configuration
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere18a1062007-07-08 14:21:43 -0500202#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk5b1d7132002-11-03 00:07:02 +0000204#endif
205
206/*-----------------------------------------------------------------------
207 * SYPCR - System Protection Control 11-9
208 * SYPCR can only be written once after reset!
209 *-----------------------------------------------------------------------
210 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
211 */
212#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk5b1d7132002-11-03 00:07:02 +0000214 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
215#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000217#endif
218
219/*-----------------------------------------------------------------------
220 * SIUMCR - SIU Module Configuration 11-6
221 *-----------------------------------------------------------------------
222 * PCMCIA config., multi-function pin tri-state
223 */
224#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
wdenk5b1d7132002-11-03 00:07:02 +0000226#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
wdenk5b1d7132002-11-03 00:07:02 +0000228#endif /* CONFIG_CAN_DRIVER */
229
230/*-----------------------------------------------------------------------
231 * TBSCR - Time Base Status and Control 11-26
232 *-----------------------------------------------------------------------
233 * Clear Reference Interrupt Status, Timebase freezing enabled
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk5b1d7132002-11-03 00:07:02 +0000236
237/*-----------------------------------------------------------------------
238 * RTCSC - Real-Time Clock Status and Control Register 11-27
239 *-----------------------------------------------------------------------
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk5b1d7132002-11-03 00:07:02 +0000242
243/*-----------------------------------------------------------------------
244 * PISCR - Periodic Interrupt Status and Control 11-31
245 *-----------------------------------------------------------------------
246 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk5b1d7132002-11-03 00:07:02 +0000249
250/*-----------------------------------------------------------------------
251 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
252 *-----------------------------------------------------------------------
253 * Reset PLL lock status sticky bit, timer expired status bit and timer
254 * interrupt status bit
255 *
wdenk04a85b32004-04-15 18:22:41 +0000256 *
257 *-----------------------------------------------------------------------
wdenk5b1d7132002-11-03 00:07:02 +0000258 * SCCR - System Clock and reset Control Register 15-27
259 *-----------------------------------------------------------------------
260 * Set clock output, timebase and RTC source and divider,
261 * power management and some other internal clocks
262 */
wdenk04a85b32004-04-15 18:22:41 +0000263
wdenk5b1d7132002-11-03 00:07:02 +0000264#define SCCR_MASK SCCR_EBDF11
wdenk04a85b32004-04-15 18:22:41 +0000265
266#if CONFIG_8xx_GCLK_FREQ == 50000000
267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
269#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk5b1d7132002-11-03 00:07:02 +0000270 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
271 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
272 SCCR_DFALCD00)
273
wdenk04a85b32004-04-15 18:22:41 +0000274#elif CONFIG_8xx_GCLK_FREQ == 80000000
275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
277#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk04a85b32004-04-15 18:22:41 +0000278 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
279 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
280 SCCR_DFALCD00 | SCCR_EBDF01)
281
282#endif
283
wdenk5b1d7132002-11-03 00:07:02 +0000284/*-----------------------------------------------------------------------
285 *
286 *-----------------------------------------------------------------------
287 *
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289/*#define CONFIG_SYS_DER 0x2002000F*/
290#define CONFIG_SYS_DER 0
wdenk5b1d7132002-11-03 00:07:02 +0000291
292/*
293 * Init Memory Controller:
294 *
295 * BR0/1 and OR0/1 (FLASH)
296 */
297
298#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
299
300/* used to re-map FLASH both when starting from SRAM or FLASH:
301 * restrict access enough to keep SRAM working (if any)
302 * but not too much to meddle with FLASH accesses
303 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
305#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk5b1d7132002-11-03 00:07:02 +0000306
307/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
wdenk5b1d7132002-11-03 00:07:02 +0000309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
311#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
312#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenk5b1d7132002-11-03 00:07:02 +0000313
314/*
wdenk5b1d7132002-11-03 00:07:02 +0000315 * BR3 and OR3 (SDRAM)
316 *
317 */
318#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
319#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
320
321/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
wdenk5b1d7132002-11-03 00:07:02 +0000323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
325#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
wdenk5b1d7132002-11-03 00:07:02 +0000326
327/*
wdenk5b1d7132002-11-03 00:07:02 +0000328 * Memory Periodic Timer Prescaler
329 */
330
331/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_MAMR_PTA 208
wdenk5b1d7132002-11-03 00:07:02 +0000333
334/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk5b1d7132002-11-03 00:07:02 +0000336
337/*
338 * MAMR settings for SDRAM
339 */
340
341/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk5b1d7132002-11-03 00:07:02 +0000343 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
344 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
345
wdenk5b1d7132002-11-03 00:07:02 +0000346/* Ethernet at SCC2 */
347#define CONFIG_SCC2_ENET
348
wdenk993cad92003-06-26 22:04:09 +0000349/****************************************************************/
350
351#define DSP_SIZE 0x00010000 /* 64K */
352#define FPGA_SIZE 0x00010000 /* 64K */
353
354#define DSP0_BASE 0xF1000000
355#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
356#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
357
358#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
359
360#define ER_SIZE 0x00010000 /* 64K */
361#define ER_BASE (FPGA_BASE + FPGA_SIZE)
362
363#define NAND_SIZE 0x00010000 /* 64K */
364#define NAND_BASE (ER_BASE + ER_SIZE)
365
366#endif
367
368/****************************************************************/
369
370#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
371
372#define STATUS_LED_BIT 0x00000001 /* bit 31 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
wdenk993cad92003-06-26 22:04:09 +0000374#define STATUS_LED_STATE STATUS_LED_BLINKING
375
376#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
wdenk993cad92003-06-26 22:04:09 +0000378#define STATUS_LED_STATE1 STATUS_LED_OFF
379
380#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
381#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
382
383#endif
384
wdenk993cad92003-06-26 22:04:09 +0000385
386/*****************************************************************************/
387
388#ifndef __ASSEMBLY__
389
390#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
391
392/* LEDs */
393
394/* last value written to the external register; we cannot read back */
395extern unsigned int last_er_val;
396
397/* led_id_t is unsigned long mask */
398typedef unsigned int led_id_t;
399
400static inline void __led_init(led_id_t mask, int state)
401{
402 unsigned int new_er_val;
403
404 if (state)
405 new_er_val = last_er_val & ~mask;
406 else
407 new_er_val = last_er_val | mask;
408
409 *(volatile unsigned int *)ER_BASE = new_er_val;
410 last_er_val = new_er_val;
411}
412
413static inline void __led_toggle(led_id_t mask)
414{
415 unsigned int new_er_val;
416
417 new_er_val = last_er_val ^ mask;
418 *(volatile unsigned int *)ER_BASE = new_er_val;
419 last_er_val = new_er_val;
420}
421
422static inline void __led_set(led_id_t mask, int state)
423{
424 unsigned int new_er_val;
425
426 if (state)
427 new_er_val = last_er_val & ~mask;
428 else
429 new_er_val = last_er_val | mask;
430
431 *(volatile unsigned int *)ER_BASE = new_er_val;
432 last_er_val = new_er_val;
433}
434
435/* MAX3100 console */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
wdenk993cad92003-06-26 22:04:09 +0000437#define MAX3100_SPI_RXD_BIT 0x00000008
438
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
wdenk993cad92003-06-26 22:04:09 +0000440#define MAX3100_SPI_TXD_BIT 0x00000004
441
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
wdenk993cad92003-06-26 22:04:09 +0000443#define MAX3100_SPI_CLK_BIT 0x00000002
444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
wdenk993cad92003-06-26 22:04:09 +0000446#define MAX3100_CS_BIT 0x0010
447
448#endif
449
450#endif
451
wdenk04a85b32004-04-15 18:22:41 +0000452/*************************************************************************************************/
wdenk993cad92003-06-26 22:04:09 +0000453
wdenk5b1d7132002-11-03 00:07:02 +0000454#endif /* __CONFIG_H */