Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2 | /* |
York Sun | c0c32af | 2018-01-29 09:44:35 -0800 | [diff] [blame] | 3 | * Copyright 2008-2016 Freescale Semiconductor, Inc. |
Jaiprakash Singh | 164a5af | 2020-06-02 12:44:02 +0530 | [diff] [blame] | 4 | * Copyright 2017-2020 NXP Semiconductor |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
Shengzhou Liu | 02fb276 | 2016-11-21 11:36:48 +0800 | [diff] [blame] | 8 | * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller. |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 9 | * Based on code from spd_sdram.c |
| 10 | * Author: James Yang [at freescale.com] |
| 11 | */ |
| 12 | |
| 13 | #include <common.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 14 | #include <fsl_ddr_sdram.h> |
Shengzhou Liu | 02fb276 | 2016-11-21 11:36:48 +0800 | [diff] [blame] | 15 | #include <fsl_errata.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 16 | #include <fsl_ddr.h> |
York Sun | 9a17eb5 | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 17 | #include <fsl_immap.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 18 | #include <log.h> |
Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 19 | #include <asm/bitops.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 20 | #include <asm/io.h> |
Simon Glass | 457e51c | 2017-05-17 08:23:10 -0600 | [diff] [blame] | 21 | #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ |
| 22 | defined(CONFIG_ARM) |
Simon Glass | 6e2941d | 2017-05-17 08:23:06 -0600 | [diff] [blame] | 23 | #include <asm/arch/clock.h> |
| 24 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 25 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 26 | /* |
| 27 | * Determine Rtt value. |
| 28 | * |
| 29 | * This should likely be either board or controller specific. |
| 30 | * |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 31 | * Rtt(nominal) - DDR2: |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 32 | * 0 = Rtt disabled |
| 33 | * 1 = 75 ohm |
| 34 | * 2 = 150 ohm |
| 35 | * 3 = 50 ohm |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 36 | * Rtt(nominal) - DDR3: |
| 37 | * 0 = Rtt disabled |
| 38 | * 1 = 60 ohm |
| 39 | * 2 = 120 ohm |
| 40 | * 3 = 40 ohm |
| 41 | * 4 = 20 ohm |
| 42 | * 5 = 30 ohm |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 43 | * |
| 44 | * FIXME: Apparently 8641 needs a value of 2 |
| 45 | * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 |
| 46 | * |
| 47 | * FIXME: There was some effort down this line earlier: |
| 48 | * |
| 49 | * unsigned int i; |
| 50 | * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { |
| 51 | * if (popts->dimmslot[i].num_valid_cs |
| 52 | * && (popts->cs_local_opts[2*i].odt_rd_cfg |
| 53 | * || popts->cs_local_opts[2*i].odt_wr_cfg)) { |
| 54 | * rtt = 2; |
| 55 | * break; |
| 56 | * } |
| 57 | * } |
| 58 | */ |
| 59 | static inline int fsl_ddr_get_rtt(void) |
| 60 | { |
| 61 | int rtt; |
| 62 | |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 63 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 64 | rtt = 0; |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 65 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 66 | rtt = 3; |
| 67 | #else |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 68 | rtt = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 69 | #endif |
| 70 | |
| 71 | return rtt; |
| 72 | } |
| 73 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 74 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 75 | /* |
| 76 | * compute CAS write latency according to DDR4 spec |
| 77 | * CWL = 9 for <= 1600MT/s |
| 78 | * 10 for <= 1866MT/s |
| 79 | * 11 for <= 2133MT/s |
| 80 | * 12 for <= 2400MT/s |
| 81 | * 14 for <= 2667MT/s |
| 82 | * 16 for <= 2933MT/s |
| 83 | * 18 for higher |
| 84 | */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 85 | static inline unsigned int compute_cas_write_latency( |
| 86 | const unsigned int ctrl_num) |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 87 | { |
| 88 | unsigned int cwl; |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 89 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 90 | if (mclk_ps >= 1250) |
| 91 | cwl = 9; |
| 92 | else if (mclk_ps >= 1070) |
| 93 | cwl = 10; |
| 94 | else if (mclk_ps >= 935) |
| 95 | cwl = 11; |
| 96 | else if (mclk_ps >= 833) |
| 97 | cwl = 12; |
| 98 | else if (mclk_ps >= 750) |
| 99 | cwl = 14; |
| 100 | else if (mclk_ps >= 681) |
| 101 | cwl = 16; |
| 102 | else |
| 103 | cwl = 18; |
| 104 | |
| 105 | return cwl; |
| 106 | } |
| 107 | #else |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 108 | /* |
| 109 | * compute the CAS write latency according to DDR3 spec |
| 110 | * CWL = 5 if tCK >= 2.5ns |
| 111 | * 6 if 2.5ns > tCK >= 1.875ns |
| 112 | * 7 if 1.875ns > tCK >= 1.5ns |
| 113 | * 8 if 1.5ns > tCK >= 1.25ns |
York Sun | 2bba85f | 2011-08-24 09:40:25 -0700 | [diff] [blame] | 114 | * 9 if 1.25ns > tCK >= 1.07ns |
| 115 | * 10 if 1.07ns > tCK >= 0.935ns |
| 116 | * 11 if 0.935ns > tCK >= 0.833ns |
| 117 | * 12 if 0.833ns > tCK >= 0.75ns |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 118 | */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 119 | static inline unsigned int compute_cas_write_latency( |
| 120 | const unsigned int ctrl_num) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 121 | { |
| 122 | unsigned int cwl; |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 123 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 124 | |
| 125 | if (mclk_ps >= 2500) |
| 126 | cwl = 5; |
| 127 | else if (mclk_ps >= 1875) |
| 128 | cwl = 6; |
| 129 | else if (mclk_ps >= 1500) |
| 130 | cwl = 7; |
| 131 | else if (mclk_ps >= 1250) |
| 132 | cwl = 8; |
York Sun | 2bba85f | 2011-08-24 09:40:25 -0700 | [diff] [blame] | 133 | else if (mclk_ps >= 1070) |
| 134 | cwl = 9; |
| 135 | else if (mclk_ps >= 935) |
| 136 | cwl = 10; |
| 137 | else if (mclk_ps >= 833) |
| 138 | cwl = 11; |
| 139 | else if (mclk_ps >= 750) |
| 140 | cwl = 12; |
| 141 | else { |
| 142 | cwl = 12; |
| 143 | printf("Warning: CWL is out of range\n"); |
| 144 | } |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 145 | return cwl; |
| 146 | } |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 147 | #endif |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 148 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 149 | /* Chip Select Configuration (CSn_CONFIG) */ |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 150 | static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 151 | const memctl_options_t *popts, |
| 152 | const dimm_params_t *dimm_params) |
| 153 | { |
| 154 | unsigned int cs_n_en = 0; /* Chip Select enable */ |
| 155 | unsigned int intlv_en = 0; /* Memory controller interleave enable */ |
| 156 | unsigned int intlv_ctl = 0; /* Interleaving control */ |
| 157 | unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ |
| 158 | unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ |
| 159 | unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ |
| 160 | unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ |
| 161 | unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ |
| 162 | unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 163 | int go_config = 0; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 164 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 165 | unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */ |
| 166 | #else |
| 167 | unsigned int n_banks_per_sdram_device; |
| 168 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 169 | |
| 170 | /* Compute CS_CONFIG only for existing ranks of each DIMM. */ |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 171 | switch (i) { |
| 172 | case 0: |
| 173 | if (dimm_params[dimm_number].n_ranks > 0) { |
| 174 | go_config = 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 175 | /* These fields only available in CS0_CONFIG */ |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 176 | if (!popts->memctl_interleaving) |
| 177 | break; |
| 178 | switch (popts->memctl_interleaving_mode) { |
York Sun | 6b1e125 | 2014-02-10 13:59:44 -0800 | [diff] [blame] | 179 | case FSL_DDR_256B_INTERLEAVING: |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 180 | case FSL_DDR_CACHE_LINE_INTERLEAVING: |
| 181 | case FSL_DDR_PAGE_INTERLEAVING: |
| 182 | case FSL_DDR_BANK_INTERLEAVING: |
| 183 | case FSL_DDR_SUPERBANK_INTERLEAVING: |
| 184 | intlv_en = popts->memctl_interleaving; |
| 185 | intlv_ctl = popts->memctl_interleaving_mode; |
| 186 | break; |
| 187 | default: |
| 188 | break; |
| 189 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 190 | } |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 191 | break; |
| 192 | case 1: |
| 193 | if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ |
| 194 | (dimm_number == 1 && dimm_params[1].n_ranks > 0)) |
| 195 | go_config = 1; |
| 196 | break; |
| 197 | case 2: |
| 198 | if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ |
York Sun | cae7c1b | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 199 | (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 200 | go_config = 1; |
| 201 | break; |
| 202 | case 3: |
| 203 | if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ |
| 204 | (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ |
| 205 | (dimm_number == 3 && dimm_params[3].n_ranks > 0)) |
| 206 | go_config = 1; |
| 207 | break; |
| 208 | default: |
| 209 | break; |
| 210 | } |
| 211 | if (go_config) { |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 212 | cs_n_en = 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 213 | ap_n_en = popts->cs_local_opts[i].auto_precharge; |
| 214 | odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; |
| 215 | odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 216 | #ifdef CONFIG_SYS_FSL_DDR4 |
Sean Anderson | 6f6fbb3 | 2022-08-30 17:01:07 -0400 | [diff] [blame] | 217 | ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits - 2; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 218 | bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits; |
| 219 | #else |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 220 | n_banks_per_sdram_device |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 221 | = dimm_params[dimm_number].n_banks_per_sdram_device; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 222 | ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 223 | #endif |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 224 | row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; |
| 225 | col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 226 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 227 | ddr->cs[i].config = (0 |
| 228 | | ((cs_n_en & 0x1) << 31) |
| 229 | | ((intlv_en & 0x3) << 29) |
Haiying Wang | dbbbb3a | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 230 | | ((intlv_ctl & 0xf) << 24) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 231 | | ((ap_n_en & 0x1) << 23) |
| 232 | |
| 233 | /* XXX: some implementation only have 1 bit starting at left */ |
| 234 | | ((odt_rd_cfg & 0x7) << 20) |
| 235 | |
| 236 | /* XXX: Some implementation only have 1 bit starting at left */ |
| 237 | | ((odt_wr_cfg & 0x7) << 16) |
| 238 | |
| 239 | | ((ba_bits_cs_n & 0x3) << 14) |
| 240 | | ((row_bits_cs_n & 0x7) << 8) |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 241 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 242 | | ((bg_bits_cs_n & 0x3) << 4) |
| 243 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 244 | | ((col_bits_cs_n & 0x7) << 0) |
| 245 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 246 | debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | /* Chip Select Configuration 2 (CSn_CONFIG_2) */ |
| 250 | /* FIXME: 8572 */ |
| 251 | static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) |
| 252 | { |
| 253 | unsigned int pasr_cfg = 0; /* Partial array self refresh config */ |
| 254 | |
| 255 | ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 256 | debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ |
| 260 | |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 261 | #if !defined(CONFIG_SYS_FSL_DDR1) |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 262 | /* |
| 263 | * Check DIMM configuration, return 2 if quad-rank or two dual-rank |
| 264 | * Return 1 if other two slots configuration. Return 0 if single slot. |
| 265 | */ |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 266 | static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) |
| 267 | { |
| 268 | #if CONFIG_DIMM_SLOTS_PER_CTLR == 1 |
| 269 | if (dimm_params[0].n_ranks == 4) |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 270 | return 2; |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 271 | #endif |
| 272 | |
| 273 | #if CONFIG_DIMM_SLOTS_PER_CTLR == 2 |
| 274 | if ((dimm_params[0].n_ranks == 2) && |
| 275 | (dimm_params[1].n_ranks == 2)) |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 276 | return 2; |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 277 | |
| 278 | #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE |
| 279 | if (dimm_params[0].n_ranks == 4) |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 280 | return 2; |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 281 | #endif |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 282 | |
| 283 | if ((dimm_params[0].n_ranks != 0) && |
| 284 | (dimm_params[2].n_ranks != 0)) |
| 285 | return 1; |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 286 | #endif |
| 287 | return 0; |
| 288 | } |
| 289 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 290 | /* |
| 291 | * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) |
| 292 | * |
| 293 | * Avoid writing for DDR I. The new PQ38 DDR controller |
| 294 | * dreams up non-zero default values to be backwards compatible. |
| 295 | */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 296 | static void set_timing_cfg_0(const unsigned int ctrl_num, |
| 297 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 298 | const memctl_options_t *popts, |
| 299 | const dimm_params_t *dimm_params) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 300 | { |
| 301 | unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ |
| 302 | unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ |
| 303 | /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ |
| 304 | unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ |
| 305 | unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ |
| 306 | |
| 307 | /* Active powerdown exit timing (tXARD and tXARDS). */ |
| 308 | unsigned char act_pd_exit_mclk; |
| 309 | /* Precharge powerdown exit timing (tXP). */ |
| 310 | unsigned char pre_pd_exit_mclk; |
york | 5fb8a8a | 2010-07-02 22:25:56 +0000 | [diff] [blame] | 311 | /* ODT powerdown exit timing (tAXPD). */ |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 312 | unsigned char taxpd_mclk = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 313 | /* Mode register set cycle time (tMRD). */ |
| 314 | unsigned char tmrd_mclk; |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 315 | #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 316 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 317 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 318 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 319 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 320 | /* tXP=max(4nCK, 6ns) */ |
Masahiro Yamada | b414119 | 2014-11-07 03:03:31 +0900 | [diff] [blame] | 321 | int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ |
York Sun | 66869f9 | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 322 | unsigned int data_rate = get_ddr_freq(ctrl_num); |
| 323 | |
| 324 | /* for faster clock, need more time for data setup */ |
| 325 | trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2; |
York Sun | 6c6e006 | 2015-11-04 10:03:21 -0800 | [diff] [blame] | 326 | |
| 327 | /* |
| 328 | * for single quad-rank DIMM and two-slot DIMMs |
| 329 | * to avoid ODT overlap |
| 330 | */ |
| 331 | switch (avoid_odt_overlap(dimm_params)) { |
| 332 | case 2: |
| 333 | twrt_mclk = 2; |
| 334 | twwt_mclk = 2; |
| 335 | trrt_mclk = 2; |
| 336 | break; |
| 337 | default: |
| 338 | twrt_mclk = 1; |
| 339 | twwt_mclk = 1; |
| 340 | trrt_mclk = 0; |
| 341 | break; |
| 342 | } |
| 343 | |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 344 | act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 345 | pre_pd_exit_mclk = act_pd_exit_mclk; |
| 346 | /* |
| 347 | * MRS_CYC = max(tMRD, tMOD) |
| 348 | * tMRD = 8nCK, tMOD = max(24nCK, 15ns) |
| 349 | */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 350 | tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000)); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 351 | #elif defined(CONFIG_SYS_FSL_DDR3) |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 352 | unsigned int data_rate = get_ddr_freq(ctrl_num); |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 353 | int txp; |
York Sun | 938bbb6 | 2014-12-02 11:18:09 -0800 | [diff] [blame] | 354 | unsigned int ip_rev; |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 355 | int odt_overlap; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 356 | /* |
| 357 | * (tXARD and tXARDS). Empirical? |
| 358 | * The DDR3 spec has not tXARD, |
| 359 | * we use the tXP instead of it. |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 360 | * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066 |
| 361 | * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133 |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 362 | * spec has not the tAXPD, we use |
york | 5fb8a8a | 2010-07-02 22:25:56 +0000 | [diff] [blame] | 363 | * tAXPD=1, need design to confirm. |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 364 | */ |
Masahiro Yamada | b414119 | 2014-11-07 03:03:31 +0900 | [diff] [blame] | 365 | txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 366 | |
York Sun | 66869f9 | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 367 | ip_rev = fsl_ddr_get_version(ctrl_num); |
York Sun | 938bbb6 | 2014-12-02 11:18:09 -0800 | [diff] [blame] | 368 | if (ip_rev >= 0x40700) { |
| 369 | /* |
| 370 | * MRS_CYC = max(tMRD, tMOD) |
| 371 | * tMRD = 4nCK (8nCK for RDIMM) |
| 372 | * tMOD = max(12nCK, 15ns) |
| 373 | */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 374 | tmrd_mclk = max((unsigned int)12, |
| 375 | picos_to_mclk(ctrl_num, 15000)); |
York Sun | 938bbb6 | 2014-12-02 11:18:09 -0800 | [diff] [blame] | 376 | } else { |
| 377 | /* |
| 378 | * MRS_CYC = tMRD |
| 379 | * tMRD = 4nCK (8nCK for RDIMM) |
| 380 | */ |
| 381 | if (popts->registered_dimm_en) |
| 382 | tmrd_mclk = 8; |
| 383 | else |
| 384 | tmrd_mclk = 4; |
| 385 | } |
| 386 | |
Dave Liu | 99bac47 | 2009-12-08 11:56:48 +0800 | [diff] [blame] | 387 | /* set the turnaround time */ |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 388 | |
| 389 | /* |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 390 | * for single quad-rank DIMM and two-slot DIMMs |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 391 | * to avoid ODT overlap |
| 392 | */ |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 393 | odt_overlap = avoid_odt_overlap(dimm_params); |
| 394 | switch (odt_overlap) { |
| 395 | case 2: |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 396 | twwt_mclk = 2; |
| 397 | trrt_mclk = 1; |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 398 | break; |
| 399 | case 1: |
| 400 | twwt_mclk = 1; |
| 401 | trrt_mclk = 0; |
| 402 | break; |
| 403 | default: |
| 404 | break; |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 405 | } |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 406 | |
York Sun | 123922b | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 407 | /* for faster clock, need more time for data setup */ |
| 408 | trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; |
| 409 | |
York Sun | 856e4b0 | 2011-02-10 10:13:10 -0800 | [diff] [blame] | 410 | if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) |
| 411 | twrt_mclk = 1; |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 412 | |
| 413 | if (popts->dynamic_power == 0) { /* powerdown is not used */ |
| 414 | act_pd_exit_mclk = 1; |
| 415 | pre_pd_exit_mclk = 1; |
| 416 | taxpd_mclk = 1; |
| 417 | } else { |
| 418 | /* act_pd_exit_mclk = tXARD, see above */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 419 | act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 420 | /* Mode register MR0[A12] is '1' - fast exit */ |
| 421 | pre_pd_exit_mclk = act_pd_exit_mclk; |
| 422 | taxpd_mclk = 1; |
| 423 | } |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 424 | #else /* CONFIG_SYS_FSL_DDR2 */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 425 | /* |
| 426 | * (tXARD and tXARDS). Empirical? |
| 427 | * tXARD = 2 for DDR2 |
| 428 | * tXP=2 |
| 429 | * tAXPD=8 |
| 430 | */ |
| 431 | act_pd_exit_mclk = 2; |
| 432 | pre_pd_exit_mclk = 2; |
| 433 | taxpd_mclk = 8; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 434 | tmrd_mclk = 2; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 435 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 436 | |
York Sun | 23f9670 | 2011-05-27 13:44:28 +0800 | [diff] [blame] | 437 | if (popts->trwt_override) |
| 438 | trwt_mclk = popts->trwt; |
| 439 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 440 | ddr->timing_cfg_0 = (0 |
| 441 | | ((trwt_mclk & 0x3) << 30) /* RWT */ |
| 442 | | ((twrt_mclk & 0x3) << 28) /* WRT */ |
| 443 | | ((trrt_mclk & 0x3) << 26) /* RRT */ |
| 444 | | ((twwt_mclk & 0x3) << 24) /* WWT */ |
York Sun | d4263b8 | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 445 | | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */ |
Dave Liu | 22ff3d0 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 446 | | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 447 | | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ |
York Sun | d4263b8 | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 448 | | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 449 | ); |
| 450 | debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); |
| 451 | } |
York Sun | 84baed2 | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 452 | #endif /* !defined(CONFIG_SYS_FSL_DDR1) */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 453 | |
| 454 | /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 455 | static void set_timing_cfg_3(const unsigned int ctrl_num, |
| 456 | fsl_ddr_cfg_regs_t *ddr, |
| 457 | const memctl_options_t *popts, |
| 458 | const common_timing_params_t *common_dimm, |
| 459 | unsigned int cas_latency, |
| 460 | unsigned int additive_latency) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 461 | { |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 462 | /* Extended precharge to activate interval (tRP) */ |
| 463 | unsigned int ext_pretoact = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 464 | /* Extended Activate to precharge interval (tRAS) */ |
| 465 | unsigned int ext_acttopre = 0; |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 466 | /* Extended activate to read/write interval (tRCD) */ |
| 467 | unsigned int ext_acttorw = 0; |
| 468 | /* Extended refresh recovery time (tRFC) */ |
| 469 | unsigned int ext_refrec; |
| 470 | /* Extended MCAS latency from READ cmd */ |
| 471 | unsigned int ext_caslat = 0; |
York Sun | d4263b8 | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 472 | /* Extended additive latency */ |
| 473 | unsigned int ext_add_lat = 0; |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 474 | /* Extended last data to precharge interval (tWR) */ |
| 475 | unsigned int ext_wrrec = 0; |
| 476 | /* Control Adjust */ |
| 477 | unsigned int cntl_adj = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 478 | |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 479 | ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4; |
| 480 | ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4; |
| 481 | ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4; |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 482 | ext_caslat = (2 * cas_latency - 1) >> 4; |
York Sun | d4263b8 | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 483 | ext_add_lat = additive_latency >> 4; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 484 | #ifdef CONFIG_SYS_FSL_DDR4 |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 485 | ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 486 | #else |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 487 | ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4; |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 488 | /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 489 | #endif |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 490 | ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) + |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 491 | (popts->otf_burst_chop_en ? 2 : 0)) >> 4; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 492 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 493 | ddr->timing_cfg_3 = (0 |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 494 | | ((ext_pretoact & 0x1) << 28) |
James Yang | c45f5c0 | 2013-07-22 09:35:26 -0700 | [diff] [blame] | 495 | | ((ext_acttopre & 0x3) << 24) |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 496 | | ((ext_acttorw & 0x1) << 22) |
York Sun | c0c32af | 2018-01-29 09:44:35 -0800 | [diff] [blame] | 497 | | ((ext_refrec & 0x3F) << 16) |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 498 | | ((ext_caslat & 0x3) << 12) |
York Sun | d4263b8 | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 499 | | ((ext_add_lat & 0x1) << 10) |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 500 | | ((ext_wrrec & 0x1) << 8) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 501 | | ((cntl_adj & 0x7) << 0) |
| 502 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 503 | debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 507 | static void set_timing_cfg_1(const unsigned int ctrl_num, |
| 508 | fsl_ddr_cfg_regs_t *ddr, |
| 509 | const memctl_options_t *popts, |
| 510 | const common_timing_params_t *common_dimm, |
| 511 | unsigned int cas_latency) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 512 | { |
| 513 | /* Precharge-to-activate interval (tRP) */ |
| 514 | unsigned char pretoact_mclk; |
| 515 | /* Activate to precharge interval (tRAS) */ |
| 516 | unsigned char acttopre_mclk; |
| 517 | /* Activate to read/write interval (tRCD) */ |
| 518 | unsigned char acttorw_mclk; |
| 519 | /* CASLAT */ |
| 520 | unsigned char caslat_ctrl; |
| 521 | /* Refresh recovery time (tRFC) ; trfc_low */ |
| 522 | unsigned char refrec_ctrl; |
| 523 | /* Last data to precharge minimum interval (tWR) */ |
| 524 | unsigned char wrrec_mclk; |
| 525 | /* Activate-to-activate interval (tRRD) */ |
| 526 | unsigned char acttoact_mclk; |
| 527 | /* Last write data pair to read command issue interval (tWTR) */ |
| 528 | unsigned char wrtord_mclk; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 529 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 530 | /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */ |
| 531 | static const u8 wrrec_table[] = { |
| 532 | 10, 10, 10, 10, 10, |
| 533 | 10, 10, 10, 10, 10, |
| 534 | 12, 12, 14, 14, 16, |
| 535 | 16, 18, 18, 20, 20, |
| 536 | 24, 24, 24, 24}; |
| 537 | #else |
York Sun | f5b6fb7 | 2011-03-02 14:24:11 -0800 | [diff] [blame] | 538 | /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ |
| 539 | static const u8 wrrec_table[] = { |
| 540 | 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 541 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 542 | |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 543 | pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps); |
| 544 | acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps); |
| 545 | acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 546 | |
| 547 | /* |
| 548 | * Translate CAS Latency to a DDR controller field value: |
| 549 | * |
| 550 | * CAS Lat DDR I DDR II Ctrl |
| 551 | * Clocks SPD Bit SPD Bit Value |
| 552 | * ------- ------- ------- ----- |
| 553 | * 1.0 0 0001 |
| 554 | * 1.5 1 0010 |
| 555 | * 2.0 2 2 0011 |
| 556 | * 2.5 3 0100 |
| 557 | * 3.0 4 3 0101 |
| 558 | * 3.5 5 0110 |
| 559 | * 4.0 4 0111 |
| 560 | * 4.5 1000 |
| 561 | * 5.0 5 1001 |
| 562 | */ |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 563 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 564 | caslat_ctrl = (cas_latency + 1) & 0x07; |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 565 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 566 | caslat_ctrl = 2 * cas_latency - 1; |
| 567 | #else |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 568 | /* |
| 569 | * if the CAS latency more than 8 cycle, |
| 570 | * we need set extend bit for it at |
| 571 | * TIMING_CFG_3[EXT_CASLAT] |
| 572 | */ |
York Sun | 66869f9 | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 573 | if (fsl_ddr_get_version(ctrl_num) <= 0x40400) |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 574 | caslat_ctrl = 2 * cas_latency - 1; |
| 575 | else |
| 576 | caslat_ctrl = (cas_latency - 1) << 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 577 | #endif |
| 578 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 579 | #ifdef CONFIG_SYS_FSL_DDR4 |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 580 | refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8; |
| 581 | wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
| 582 | acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U); |
| 583 | wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500)); |
York Sun | 349689b | 2014-04-01 14:20:49 -0700 | [diff] [blame] | 584 | if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) |
| 585 | printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 586 | else |
| 587 | wrrec_mclk = wrrec_table[wrrec_mclk - 1]; |
| 588 | #else |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 589 | refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8; |
| 590 | wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
| 591 | acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps); |
| 592 | wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps); |
York Sun | 349689b | 2014-04-01 14:20:49 -0700 | [diff] [blame] | 593 | if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) |
| 594 | printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); |
York Sun | 45064ad | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 595 | else |
| 596 | wrrec_mclk = wrrec_table[wrrec_mclk - 1]; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 597 | #endif |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 598 | if (popts->otf_burst_chop_en) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 599 | wrrec_mclk += 2; |
| 600 | |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 601 | /* |
| 602 | * JEDEC has min requirement for tRRD |
| 603 | */ |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 604 | #if defined(CONFIG_SYS_FSL_DDR3) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 605 | if (acttoact_mclk < 4) |
| 606 | acttoact_mclk = 4; |
| 607 | #endif |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 608 | /* |
| 609 | * JEDEC has some min requirements for tWTR |
| 610 | */ |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 611 | #if defined(CONFIG_SYS_FSL_DDR2) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 612 | if (wrtord_mclk < 2) |
| 613 | wrtord_mclk = 2; |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 614 | #elif defined(CONFIG_SYS_FSL_DDR3) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 615 | if (wrtord_mclk < 4) |
| 616 | wrtord_mclk = 4; |
| 617 | #endif |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 618 | if (popts->otf_burst_chop_en) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 619 | wrtord_mclk += 2; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 620 | |
| 621 | ddr->timing_cfg_1 = (0 |
Dave Liu | 80ee3ce | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 622 | | ((pretoact_mclk & 0x0F) << 28) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 623 | | ((acttopre_mclk & 0x0F) << 24) |
Dave Liu | 80ee3ce | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 624 | | ((acttorw_mclk & 0xF) << 20) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 625 | | ((caslat_ctrl & 0xF) << 16) |
| 626 | | ((refrec_ctrl & 0xF) << 12) |
Dave Liu | 80ee3ce | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 627 | | ((wrrec_mclk & 0x0F) << 8) |
York Sun | 57495e4 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 628 | | ((acttoact_mclk & 0x0F) << 4) |
| 629 | | ((wrtord_mclk & 0x0F) << 0) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 630 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 631 | debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 635 | static void set_timing_cfg_2(const unsigned int ctrl_num, |
| 636 | fsl_ddr_cfg_regs_t *ddr, |
| 637 | const memctl_options_t *popts, |
| 638 | const common_timing_params_t *common_dimm, |
| 639 | unsigned int cas_latency, |
| 640 | unsigned int additive_latency) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 641 | { |
| 642 | /* Additive latency */ |
| 643 | unsigned char add_lat_mclk; |
| 644 | /* CAS-to-preamble override */ |
| 645 | unsigned short cpo; |
| 646 | /* Write latency */ |
| 647 | unsigned char wr_lat; |
| 648 | /* Read to precharge (tRTP) */ |
| 649 | unsigned char rd_to_pre; |
| 650 | /* Write command to write data strobe timing adjustment */ |
| 651 | unsigned char wr_data_delay; |
| 652 | /* Minimum CKE pulse width (tCKE) */ |
| 653 | unsigned char cke_pls; |
| 654 | /* Window for four activates (tFAW) */ |
| 655 | unsigned short four_act; |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 656 | #ifdef CONFIG_SYS_FSL_DDR3 |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 657 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 658 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 659 | |
| 660 | /* FIXME add check that this must be less than acttorw_mclk */ |
| 661 | add_lat_mclk = additive_latency; |
| 662 | cpo = popts->cpo_override; |
| 663 | |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 664 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 665 | /* |
| 666 | * This is a lie. It should really be 1, but if it is |
| 667 | * set to 1, bits overlap into the old controller's |
| 668 | * otherwise unused ACSM field. If we leave it 0, then |
| 669 | * the HW will magically treat it as 1 for DDR 1. Oh Yea. |
| 670 | */ |
| 671 | wr_lat = 0; |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 672 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Dave Liu | 6a81978 | 2009-03-14 12:48:19 +0800 | [diff] [blame] | 673 | wr_lat = cas_latency - 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 674 | #else |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 675 | wr_lat = compute_cas_write_latency(ctrl_num); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 676 | #endif |
| 677 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 678 | #ifdef CONFIG_SYS_FSL_DDR4 |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 679 | rd_to_pre = picos_to_mclk(ctrl_num, 7500); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 680 | #else |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 681 | rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 682 | #endif |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 683 | /* |
| 684 | * JEDEC has some min requirements for tRTP |
| 685 | */ |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 686 | #if defined(CONFIG_SYS_FSL_DDR2) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 687 | if (rd_to_pre < 2) |
| 688 | rd_to_pre = 2; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 689 | #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 690 | if (rd_to_pre < 4) |
| 691 | rd_to_pre = 4; |
Dave Liu | 6a81978 | 2009-03-14 12:48:19 +0800 | [diff] [blame] | 692 | #endif |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 693 | if (popts->otf_burst_chop_en) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 694 | rd_to_pre += 2; /* according to UM */ |
| 695 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 696 | wr_data_delay = popts->write_data_delay; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 697 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 698 | cpo = 0; |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 699 | cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000)); |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 700 | #elif defined(CONFIG_SYS_FSL_DDR3) |
| 701 | /* |
| 702 | * cke pulse = max(3nCK, 7.5ns) for DDR3-800 |
| 703 | * max(3nCK, 5.625ns) for DDR3-1066, 1333 |
| 704 | * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 |
| 705 | */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 706 | cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 : |
| 707 | (mclk_ps > 1245 ? 5625 : 5000))); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 708 | #else |
York Sun | bb57832 | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 709 | cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 710 | #endif |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 711 | four_act = picos_to_mclk(ctrl_num, |
| 712 | popts->tfaw_window_four_activates_ps); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 713 | |
| 714 | ddr->timing_cfg_2 = (0 |
Dave Liu | 22ff3d0 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 715 | | ((add_lat_mclk & 0xf) << 28) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 716 | | ((cpo & 0x1f) << 23) |
Dave Liu | 22ff3d0 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 717 | | ((wr_lat & 0xf) << 19) |
York Sun | 8936691 | 2016-07-29 09:02:29 -0700 | [diff] [blame] | 718 | | (((wr_lat & 0x10) >> 4) << 18) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 719 | | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) |
| 720 | | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 721 | | ((cke_pls & 0x7) << 6) |
Dave Liu | 22ff3d0 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 722 | | ((four_act & 0x3f) << 0) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 723 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 724 | debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 725 | } |
| 726 | |
york | 9490ff4 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 727 | /* DDR SDRAM Register Control Word */ |
York Sun | 564e938 | 2018-01-29 10:24:08 -0800 | [diff] [blame] | 728 | static void set_ddr_sdram_rcw(const unsigned int ctrl_num, |
| 729 | fsl_ddr_cfg_regs_t *ddr, |
| 730 | const memctl_options_t *popts, |
| 731 | const common_timing_params_t *common_dimm) |
york | 9490ff4 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 732 | { |
York Sun | 564e938 | 2018-01-29 10:24:08 -0800 | [diff] [blame] | 733 | unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000; |
| 734 | unsigned int rc0a, rc0f; |
| 735 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 736 | if (common_dimm->all_dimms_registered && |
| 737 | !common_dimm->all_dimms_unbuffered) { |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 738 | if (popts->rcw_override) { |
| 739 | ddr->ddr_sdram_rcw_1 = popts->rcw_1; |
| 740 | ddr->ddr_sdram_rcw_2 = popts->rcw_2; |
York Sun | 426230a | 2018-01-29 09:44:33 -0800 | [diff] [blame] | 741 | ddr->ddr_sdram_rcw_3 = popts->rcw_3; |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 742 | } else { |
York Sun | 564e938 | 2018-01-29 10:24:08 -0800 | [diff] [blame] | 743 | rc0a = ddr_freq > 3200 ? 0x7 : |
| 744 | (ddr_freq > 2933 ? 0x6 : |
| 745 | (ddr_freq > 2666 ? 0x5 : |
| 746 | (ddr_freq > 2400 ? 0x4 : |
| 747 | (ddr_freq > 2133 ? 0x3 : |
| 748 | (ddr_freq > 1866 ? 0x2 : |
| 749 | (ddr_freq > 1600 ? 1 : 0)))))); |
| 750 | rc0f = ddr_freq > 3200 ? 0x3 : |
| 751 | (ddr_freq > 2400 ? 0x2 : |
| 752 | (ddr_freq > 2133 ? 0x1 : 0)); |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 753 | ddr->ddr_sdram_rcw_1 = |
| 754 | common_dimm->rcw[0] << 28 | \ |
| 755 | common_dimm->rcw[1] << 24 | \ |
| 756 | common_dimm->rcw[2] << 20 | \ |
| 757 | common_dimm->rcw[3] << 16 | \ |
| 758 | common_dimm->rcw[4] << 12 | \ |
| 759 | common_dimm->rcw[5] << 8 | \ |
| 760 | common_dimm->rcw[6] << 4 | \ |
| 761 | common_dimm->rcw[7]; |
| 762 | ddr->ddr_sdram_rcw_2 = |
| 763 | common_dimm->rcw[8] << 28 | \ |
| 764 | common_dimm->rcw[9] << 24 | \ |
York Sun | 564e938 | 2018-01-29 10:24:08 -0800 | [diff] [blame] | 765 | rc0a << 20 | \ |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 766 | common_dimm->rcw[11] << 16 | \ |
| 767 | common_dimm->rcw[12] << 12 | \ |
| 768 | common_dimm->rcw[13] << 8 | \ |
| 769 | common_dimm->rcw[14] << 4 | \ |
York Sun | 564e938 | 2018-01-29 10:24:08 -0800 | [diff] [blame] | 770 | rc0f; |
| 771 | ddr->ddr_sdram_rcw_3 = |
| 772 | ((ddr_freq - 1260 + 19) / 20) << 8; |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 773 | } |
York Sun | 426230a | 2018-01-29 09:44:33 -0800 | [diff] [blame] | 774 | debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", |
| 775 | ddr->ddr_sdram_rcw_1); |
| 776 | debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", |
| 777 | ddr->ddr_sdram_rcw_2); |
| 778 | debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n", |
| 779 | ddr->ddr_sdram_rcw_3); |
york | 9490ff4 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 780 | } |
| 781 | } |
| 782 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 783 | /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ |
| 784 | static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, |
| 785 | const memctl_options_t *popts, |
| 786 | const common_timing_params_t *common_dimm) |
| 787 | { |
| 788 | unsigned int mem_en; /* DDR SDRAM interface logic enable */ |
| 789 | unsigned int sren; /* Self refresh enable (during sleep) */ |
| 790 | unsigned int ecc_en; /* ECC enable. */ |
| 791 | unsigned int rd_en; /* Registered DIMM enable */ |
| 792 | unsigned int sdram_type; /* Type of SDRAM */ |
| 793 | unsigned int dyn_pwr; /* Dynamic power management mode */ |
| 794 | unsigned int dbw; /* DRAM dta bus width */ |
Dave Liu | 22ff3d0 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 795 | unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 796 | unsigned int ncap = 0; /* Non-concurrent auto-precharge */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 797 | unsigned int threet_en; /* Enable 3T timing */ |
| 798 | unsigned int twot_en; /* Enable 2T timing */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 799 | unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ |
| 800 | unsigned int x32_en = 0; /* x32 enable */ |
| 801 | unsigned int pchb8 = 0; /* precharge bit 8 enable */ |
| 802 | unsigned int hse; /* Global half strength override */ |
York Sun | d28cb67 | 2014-09-05 13:52:41 +0800 | [diff] [blame] | 803 | unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 804 | unsigned int mem_halt = 0; /* memory controller halt */ |
| 805 | unsigned int bi = 0; /* Bypass initialization */ |
| 806 | |
| 807 | mem_en = 1; |
| 808 | sren = popts->self_refresh_in_sleep; |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 809 | if (common_dimm->all_dimms_ecc_capable) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 810 | /* Allow setting of ECC only if all DIMMs are ECC. */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 811 | ecc_en = popts->ecc_mode; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 812 | } else { |
| 813 | ecc_en = 0; |
| 814 | } |
| 815 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 816 | if (common_dimm->all_dimms_registered && |
| 817 | !common_dimm->all_dimms_unbuffered) { |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 818 | rd_en = 1; |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 819 | twot_en = 0; |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 820 | } else { |
| 821 | rd_en = 0; |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 822 | twot_en = popts->twot_en; |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 823 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 824 | |
Tom Rini | 6e7df1d | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 825 | sdram_type = CFG_FSL_SDRAM_TYPE; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 826 | |
| 827 | dyn_pwr = popts->dynamic_power; |
| 828 | dbw = popts->data_bus_width; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 829 | /* 8-beat burst enable DDR-III case |
| 830 | * we must clear it when use the on-the-fly mode, |
| 831 | * must set it when use the 32-bits bus mode. |
| 832 | */ |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 833 | if ((sdram_type == SDRAM_TYPE_DDR3) || |
| 834 | (sdram_type == SDRAM_TYPE_DDR4)) { |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 835 | if (popts->burst_length == DDR_BL8) |
| 836 | eight_be = 1; |
| 837 | if (popts->burst_length == DDR_OTF) |
| 838 | eight_be = 0; |
| 839 | if (dbw == 0x1) |
| 840 | eight_be = 1; |
| 841 | } |
| 842 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 843 | threet_en = popts->threet_en; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 844 | ba_intlv_ctl = popts->ba_intlv_ctl; |
| 845 | hse = popts->half_strength_driver_enable; |
| 846 | |
York Sun | d28cb67 | 2014-09-05 13:52:41 +0800 | [diff] [blame] | 847 | /* set when ddr bus width < 64 */ |
| 848 | acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0; |
| 849 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 850 | ddr->ddr_sdram_cfg = (0 |
| 851 | | ((mem_en & 0x1) << 31) |
| 852 | | ((sren & 0x1) << 30) |
| 853 | | ((ecc_en & 0x1) << 29) |
| 854 | | ((rd_en & 0x1) << 28) |
| 855 | | ((sdram_type & 0x7) << 24) |
| 856 | | ((dyn_pwr & 0x1) << 21) |
| 857 | | ((dbw & 0x3) << 19) |
| 858 | | ((eight_be & 0x1) << 18) |
| 859 | | ((ncap & 0x1) << 17) |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 860 | | ((threet_en & 0x1) << 16) |
| 861 | | ((twot_en & 0x1) << 15) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 862 | | ((ba_intlv_ctl & 0x7F) << 8) |
| 863 | | ((x32_en & 0x1) << 5) |
| 864 | | ((pchb8 & 0x1) << 4) |
| 865 | | ((hse & 0x1) << 3) |
York Sun | d28cb67 | 2014-09-05 13:52:41 +0800 | [diff] [blame] | 866 | | ((acc_ecc_en & 0x1) << 2) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 867 | | ((mem_halt & 0x1) << 1) |
| 868 | | ((bi & 0x1) << 0) |
| 869 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 870 | debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 871 | } |
| 872 | |
| 873 | /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 874 | static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, |
| 875 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 876 | const memctl_options_t *popts, |
| 877 | const unsigned int unq_mrs_en) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 878 | { |
| 879 | unsigned int frc_sr = 0; /* Force self refresh */ |
| 880 | unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ |
York Sun | cae7c1b | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 881 | unsigned int odt_cfg = 0; /* ODT configuration */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 882 | unsigned int num_pr; /* Number of posted refreshes */ |
York Sun | 57495e4 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 883 | unsigned int slow = 0; /* DDR will be run less than 1250 */ |
York Sun | b61e061 | 2013-06-25 11:37:47 -0700 | [diff] [blame] | 884 | unsigned int x4_en = 0; /* x4 DRAM enable */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 885 | unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ |
| 886 | unsigned int ap_en; /* Address Parity Enable */ |
| 887 | unsigned int d_init; /* DRAM data initialization */ |
| 888 | unsigned int rcw_en = 0; /* Register Control Word Enable */ |
| 889 | unsigned int md_en = 0; /* Mirrored DIMM Enable */ |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 890 | unsigned int qd_en = 0; /* quad-rank DIMM Enable */ |
York Sun | cae7c1b | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 891 | int i; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 892 | #ifndef CONFIG_SYS_FSL_DDR4 |
| 893 | unsigned int dll_rst_dis = 1; /* DLL reset disable */ |
| 894 | unsigned int dqs_cfg; /* DQS configuration */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 895 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 896 | dqs_cfg = popts->dqs_config; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 897 | #endif |
York Sun | cae7c1b | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 898 | for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
| 899 | if (popts->cs_local_opts[i].odt_rd_cfg |
| 900 | || popts->cs_local_opts[i].odt_wr_cfg) { |
| 901 | odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; |
| 902 | break; |
| 903 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 904 | } |
Joakim Tjernlund | e368c20 | 2015-10-14 16:32:00 +0200 | [diff] [blame] | 905 | sr_ie = popts->self_refresh_interrupt_en; |
York Sun | c0c32af | 2018-01-29 09:44:35 -0800 | [diff] [blame] | 906 | num_pr = popts->package_3ds + 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 907 | |
| 908 | /* |
| 909 | * 8572 manual says |
| 910 | * {TIMING_CFG_1[PRETOACT] |
| 911 | * + [DDR_SDRAM_CFG_2[NUM_PR] |
| 912 | * * ({EXT_REFREC || REFREC} + 8 + 2)]} |
| 913 | * << DDR_SDRAM_INTERVAL[REFINT] |
| 914 | */ |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 915 | #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 916 | obc_cfg = popts->otf_burst_chop_en; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 917 | #else |
| 918 | obc_cfg = 0; |
| 919 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 920 | |
York Sun | 57495e4 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 921 | #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 922 | slow = get_ddr_freq(ctrl_num) < 1249000000; |
York Sun | 57495e4 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 923 | #endif |
| 924 | |
Shengzhou Liu | eb11880 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 925 | if (popts->registered_dimm_en) |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 926 | rcw_en = 1; |
Shengzhou Liu | eb11880 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 927 | |
| 928 | /* DDR4 can have address parity for UDIMM and discrete */ |
Tom Rini | 6e7df1d | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 929 | if ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) && |
Shengzhou Liu | eb11880 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 930 | (!popts->registered_dimm_en)) { |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 931 | ap_en = 0; |
Shengzhou Liu | eb11880 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 932 | } else { |
| 933 | ap_en = popts->ap_en; |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 934 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 935 | |
York Sun | b61e061 | 2013-06-25 11:37:47 -0700 | [diff] [blame] | 936 | x4_en = popts->x4_en ? 1 : 0; |
| 937 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 938 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 939 | /* Use the DDR controller to auto initialize memory. */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 940 | d_init = popts->ecc_init_using_memctl; |
Tom Rini | 829e9d2 | 2022-12-02 16:42:35 -0500 | [diff] [blame] | 941 | ddr->ddr_data_init = 0xDEADBEEF; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 942 | debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); |
| 943 | #else |
| 944 | /* Memory will be initialized via DMA, or not at all. */ |
| 945 | d_init = 0; |
| 946 | #endif |
| 947 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 948 | #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 949 | md_en = popts->mirrored_dimm; |
| 950 | #endif |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 951 | qd_en = popts->quad_rank_present ? 1 : 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 952 | ddr->ddr_sdram_cfg_2 = (0 |
| 953 | | ((frc_sr & 0x1) << 31) |
| 954 | | ((sr_ie & 0x1) << 30) |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 955 | #ifndef CONFIG_SYS_FSL_DDR4 |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 956 | | ((dll_rst_dis & 0x1) << 29) |
| 957 | | ((dqs_cfg & 0x3) << 26) |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 958 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 959 | | ((odt_cfg & 0x3) << 21) |
| 960 | | ((num_pr & 0xf) << 12) |
York Sun | 57495e4 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 961 | | ((slow & 1) << 11) |
York Sun | b61e061 | 2013-06-25 11:37:47 -0700 | [diff] [blame] | 962 | | (x4_en << 10) |
york | 5800e7a | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 963 | | (qd_en << 9) |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 964 | | (unq_mrs_en << 8) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 965 | | ((obc_cfg & 0x1) << 6) |
| 966 | | ((ap_en & 0x1) << 5) |
| 967 | | ((d_init & 0x1) << 4) |
| 968 | | ((rcw_en & 0x1) << 2) |
| 969 | | ((md_en & 0x1) << 0) |
| 970 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 971 | debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 972 | } |
| 973 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 974 | #ifdef CONFIG_SYS_FSL_DDR4 |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 975 | /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 976 | static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, |
| 977 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 978 | const memctl_options_t *popts, |
Valentin Longchamp | 7e157b0 | 2013-10-18 11:47:20 +0200 | [diff] [blame] | 979 | const common_timing_params_t *common_dimm, |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 980 | const unsigned int unq_mrs_en) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 981 | { |
| 982 | unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ |
| 983 | unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 984 | int i; |
| 985 | unsigned int wr_crc = 0; /* Disable */ |
| 986 | unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ |
| 987 | unsigned int srt = 0; /* self-refresh temerature, normal range */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 988 | unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9; |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 989 | unsigned int mpr = 0; /* serial */ |
| 990 | unsigned int wc_lat; |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 991 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 992 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 993 | if (popts->rtt_override) |
| 994 | rtt_wr = popts->rtt_wr_override_value; |
| 995 | else |
| 996 | rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; |
| 997 | |
| 998 | if (common_dimm->extended_op_srt) |
| 999 | srt = common_dimm->extended_op_srt; |
| 1000 | |
| 1001 | esdmode2 = (0 |
| 1002 | | ((wr_crc & 0x1) << 12) |
| 1003 | | ((rtt_wr & 0x3) << 9) |
| 1004 | | ((srt & 0x3) << 6) |
| 1005 | | ((cwl & 0x7) << 3)); |
| 1006 | |
| 1007 | if (mclk_ps >= 1250) |
| 1008 | wc_lat = 0; |
| 1009 | else if (mclk_ps >= 833) |
| 1010 | wc_lat = 1; |
| 1011 | else |
| 1012 | wc_lat = 2; |
| 1013 | |
| 1014 | esdmode3 = (0 |
| 1015 | | ((mpr & 0x3) << 11) |
| 1016 | | ((wc_lat & 0x3) << 9)); |
| 1017 | |
| 1018 | ddr->ddr_sdram_mode_2 = (0 |
| 1019 | | ((esdmode2 & 0xFFFF) << 16) |
| 1020 | | ((esdmode3 & 0xFFFF) << 0) |
| 1021 | ); |
| 1022 | debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); |
| 1023 | |
| 1024 | if (unq_mrs_en) { /* unique mode registers are supported */ |
| 1025 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
| 1026 | if (popts->rtt_override) |
| 1027 | rtt_wr = popts->rtt_wr_override_value; |
| 1028 | else |
| 1029 | rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; |
| 1030 | |
| 1031 | esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ |
| 1032 | esdmode2 |= (rtt_wr & 0x3) << 9; |
| 1033 | switch (i) { |
| 1034 | case 1: |
| 1035 | ddr->ddr_sdram_mode_4 = (0 |
| 1036 | | ((esdmode2 & 0xFFFF) << 16) |
| 1037 | | ((esdmode3 & 0xFFFF) << 0) |
| 1038 | ); |
| 1039 | break; |
| 1040 | case 2: |
| 1041 | ddr->ddr_sdram_mode_6 = (0 |
| 1042 | | ((esdmode2 & 0xFFFF) << 16) |
| 1043 | | ((esdmode3 & 0xFFFF) << 0) |
| 1044 | ); |
| 1045 | break; |
| 1046 | case 3: |
| 1047 | ddr->ddr_sdram_mode_8 = (0 |
| 1048 | | ((esdmode2 & 0xFFFF) << 16) |
| 1049 | | ((esdmode3 & 0xFFFF) << 0) |
| 1050 | ); |
| 1051 | break; |
| 1052 | } |
| 1053 | } |
| 1054 | debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", |
| 1055 | ddr->ddr_sdram_mode_4); |
| 1056 | debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", |
| 1057 | ddr->ddr_sdram_mode_6); |
| 1058 | debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", |
| 1059 | ddr->ddr_sdram_mode_8); |
| 1060 | } |
| 1061 | } |
| 1062 | #elif defined(CONFIG_SYS_FSL_DDR3) |
| 1063 | /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1064 | static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, |
| 1065 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1066 | const memctl_options_t *popts, |
| 1067 | const common_timing_params_t *common_dimm, |
| 1068 | const unsigned int unq_mrs_en) |
| 1069 | { |
| 1070 | unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ |
| 1071 | unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ |
Kumar Gala | 9296683 | 2011-01-20 01:53:15 -0600 | [diff] [blame] | 1072 | int i; |
Dave Liu | 1aa3d08 | 2009-12-16 10:24:38 -0600 | [diff] [blame] | 1073 | unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1074 | unsigned int srt = 0; /* self-refresh temerature, normal range */ |
| 1075 | unsigned int asr = 0; /* auto self-refresh disable */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1076 | unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1077 | unsigned int pasr = 0; /* partial array self refresh disable */ |
| 1078 | |
Dave Liu | 1aa3d08 | 2009-12-16 10:24:38 -0600 | [diff] [blame] | 1079 | if (popts->rtt_override) |
| 1080 | rtt_wr = popts->rtt_wr_override_value; |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1081 | else |
| 1082 | rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; |
Valentin Longchamp | 7e157b0 | 2013-10-18 11:47:20 +0200 | [diff] [blame] | 1083 | |
| 1084 | if (common_dimm->extended_op_srt) |
| 1085 | srt = common_dimm->extended_op_srt; |
| 1086 | |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1087 | esdmode2 = (0 |
| 1088 | | ((rtt_wr & 0x3) << 9) |
| 1089 | | ((srt & 0x1) << 7) |
| 1090 | | ((asr & 0x1) << 6) |
| 1091 | | ((cwl & 0x7) << 3) |
| 1092 | | ((pasr & 0x7) << 0)); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1093 | ddr->ddr_sdram_mode_2 = (0 |
| 1094 | | ((esdmode2 & 0xFFFF) << 16) |
| 1095 | | ((esdmode3 & 0xFFFF) << 0) |
| 1096 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1097 | debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1098 | |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1099 | if (unq_mrs_en) { /* unique mode registers are supported */ |
Kumar Gala | dea7f88 | 2011-11-09 10:05:10 -0600 | [diff] [blame] | 1100 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1101 | if (popts->rtt_override) |
| 1102 | rtt_wr = popts->rtt_wr_override_value; |
| 1103 | else |
| 1104 | rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; |
| 1105 | |
| 1106 | esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ |
| 1107 | esdmode2 |= (rtt_wr & 0x3) << 9; |
| 1108 | switch (i) { |
| 1109 | case 1: |
| 1110 | ddr->ddr_sdram_mode_4 = (0 |
| 1111 | | ((esdmode2 & 0xFFFF) << 16) |
| 1112 | | ((esdmode3 & 0xFFFF) << 0) |
| 1113 | ); |
| 1114 | break; |
| 1115 | case 2: |
| 1116 | ddr->ddr_sdram_mode_6 = (0 |
| 1117 | | ((esdmode2 & 0xFFFF) << 16) |
| 1118 | | ((esdmode3 & 0xFFFF) << 0) |
| 1119 | ); |
| 1120 | break; |
| 1121 | case 3: |
| 1122 | ddr->ddr_sdram_mode_8 = (0 |
| 1123 | | ((esdmode2 & 0xFFFF) << 16) |
| 1124 | | ((esdmode3 & 0xFFFF) << 0) |
| 1125 | ); |
| 1126 | break; |
| 1127 | } |
| 1128 | } |
| 1129 | debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", |
| 1130 | ddr->ddr_sdram_mode_4); |
| 1131 | debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", |
| 1132 | ddr->ddr_sdram_mode_6); |
| 1133 | debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", |
| 1134 | ddr->ddr_sdram_mode_8); |
| 1135 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1136 | } |
| 1137 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1138 | #else /* for DDR2 and DDR1 */ |
| 1139 | /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1140 | static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, |
| 1141 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1142 | const memctl_options_t *popts, |
| 1143 | const common_timing_params_t *common_dimm, |
| 1144 | const unsigned int unq_mrs_en) |
| 1145 | { |
| 1146 | unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ |
| 1147 | unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ |
| 1148 | |
| 1149 | ddr->ddr_sdram_mode_2 = (0 |
| 1150 | | ((esdmode2 & 0xFFFF) << 16) |
| 1151 | | ((esdmode3 & 0xFFFF) << 0) |
| 1152 | ); |
| 1153 | debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); |
| 1154 | } |
| 1155 | #endif |
| 1156 | |
| 1157 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 1158 | /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */ |
| 1159 | static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, |
| 1160 | const memctl_options_t *popts, |
| 1161 | const common_timing_params_t *common_dimm, |
| 1162 | const unsigned int unq_mrs_en) |
| 1163 | { |
| 1164 | int i; |
| 1165 | unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ |
| 1166 | unsigned short esdmode5; /* Extended SDRAM mode 5 */ |
York Sun | 6b95be2 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1167 | int rtt_park = 0; |
York Sun | 8a51429 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1168 | bool four_cs = false; |
Shengzhou Liu | eb11880 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1169 | const unsigned int mclk_ps = get_memory_clk_period_ps(0); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1170 | |
York Sun | 8a51429 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1171 | #if CONFIG_CHIP_SELECTS_PER_CTRL == 4 |
| 1172 | if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && |
| 1173 | (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && |
| 1174 | (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) && |
| 1175 | (ddr->cs[3].config & SDRAM_CS_CONFIG_EN)) |
| 1176 | four_cs = true; |
| 1177 | #endif |
York Sun | 6b95be2 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1178 | if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { |
| 1179 | esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */ |
York Sun | 8a51429 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1180 | rtt_park = four_cs ? 0 : 1; |
York Sun | 6b95be2 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1181 | } else { |
| 1182 | esdmode5 = 0x00000400; /* Data mask enabled */ |
| 1183 | } |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1184 | |
York Sun | 426230a | 2018-01-29 09:44:33 -0800 | [diff] [blame] | 1185 | /* |
| 1186 | * For DDR3, set C/A latency if address parity is enabled. |
| 1187 | * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is |
| 1188 | * handled by register chip and RCW settings. |
| 1189 | */ |
| 1190 | if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && |
Tom Rini | 6e7df1d | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 1191 | ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) || |
York Sun | 426230a | 2018-01-29 09:44:33 -0800 | [diff] [blame] | 1192 | !popts->registered_dimm_en)) { |
Shengzhou Liu | eb11880 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1193 | if (mclk_ps >= 935) { |
| 1194 | /* for DDR4-1600/1866/2133 */ |
| 1195 | esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; |
| 1196 | } else if (mclk_ps >= 833) { |
| 1197 | /* for DDR4-2400 */ |
| 1198 | esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; |
| 1199 | } else { |
| 1200 | printf("parity: mclk_ps = %d not supported\n", mclk_ps); |
| 1201 | } |
| 1202 | } |
| 1203 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1204 | ddr->ddr_sdram_mode_9 = (0 |
| 1205 | | ((esdmode4 & 0xffff) << 16) |
| 1206 | | ((esdmode5 & 0xffff) << 0) |
| 1207 | ); |
York Sun | 66869f9 | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 1208 | |
York Sun | 8a51429 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1209 | /* Normally only the first enabled CS use 0x500, others use 0x400 |
| 1210 | * But when four chip-selects are all enabled, all mode registers |
| 1211 | * need 0x500 to park. |
| 1212 | */ |
York Sun | 66869f9 | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 1213 | |
York Sun | c0c32af | 2018-01-29 09:44:35 -0800 | [diff] [blame] | 1214 | debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1215 | if (unq_mrs_en) { /* unique mode registers are supported */ |
| 1216 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
York Sun | 6b95be2 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1217 | if (!rtt_park && |
| 1218 | (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) { |
| 1219 | esdmode5 |= 0x00000500; /* RTT_PARK */ |
York Sun | 8a51429 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1220 | rtt_park = four_cs ? 0 : 1; |
York Sun | 6b95be2 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1221 | } else { |
| 1222 | esdmode5 = 0x00000400; |
| 1223 | } |
Shengzhou Liu | eb11880 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1224 | |
York Sun | 426230a | 2018-01-29 09:44:33 -0800 | [diff] [blame] | 1225 | if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && |
Tom Rini | 6e7df1d | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 1226 | ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) || |
York Sun | 426230a | 2018-01-29 09:44:33 -0800 | [diff] [blame] | 1227 | !popts->registered_dimm_en)) { |
Shengzhou Liu | eb11880 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1228 | if (mclk_ps >= 935) { |
| 1229 | /* for DDR4-1600/1866/2133 */ |
| 1230 | esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; |
| 1231 | } else if (mclk_ps >= 833) { |
| 1232 | /* for DDR4-2400 */ |
| 1233 | esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; |
| 1234 | } else { |
| 1235 | printf("parity: mclk_ps = %d not supported\n", |
| 1236 | mclk_ps); |
| 1237 | } |
| 1238 | } |
| 1239 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1240 | switch (i) { |
| 1241 | case 1: |
| 1242 | ddr->ddr_sdram_mode_11 = (0 |
| 1243 | | ((esdmode4 & 0xFFFF) << 16) |
| 1244 | | ((esdmode5 & 0xFFFF) << 0) |
| 1245 | ); |
| 1246 | break; |
| 1247 | case 2: |
| 1248 | ddr->ddr_sdram_mode_13 = (0 |
| 1249 | | ((esdmode4 & 0xFFFF) << 16) |
| 1250 | | ((esdmode5 & 0xFFFF) << 0) |
| 1251 | ); |
| 1252 | break; |
| 1253 | case 3: |
| 1254 | ddr->ddr_sdram_mode_15 = (0 |
| 1255 | | ((esdmode4 & 0xFFFF) << 16) |
| 1256 | | ((esdmode5 & 0xFFFF) << 0) |
| 1257 | ); |
| 1258 | break; |
| 1259 | } |
| 1260 | } |
| 1261 | debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n", |
| 1262 | ddr->ddr_sdram_mode_11); |
| 1263 | debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n", |
| 1264 | ddr->ddr_sdram_mode_13); |
| 1265 | debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n", |
| 1266 | ddr->ddr_sdram_mode_15); |
| 1267 | } |
| 1268 | } |
| 1269 | |
| 1270 | /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1271 | static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, |
| 1272 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1273 | const memctl_options_t *popts, |
| 1274 | const common_timing_params_t *common_dimm, |
| 1275 | const unsigned int unq_mrs_en) |
| 1276 | { |
| 1277 | int i; |
| 1278 | unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ |
| 1279 | unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1280 | unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1281 | |
| 1282 | esdmode6 = ((tccdl_min - 4) & 0x7) << 10; |
| 1283 | |
York Sun | 0fb7197 | 2015-11-04 10:03:18 -0800 | [diff] [blame] | 1284 | if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) |
| 1285 | esdmode6 |= 1 << 6; /* Range 2 */ |
| 1286 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1287 | ddr->ddr_sdram_mode_10 = (0 |
| 1288 | | ((esdmode6 & 0xffff) << 16) |
| 1289 | | ((esdmode7 & 0xffff) << 0) |
| 1290 | ); |
York Sun | c0c32af | 2018-01-29 09:44:35 -0800 | [diff] [blame] | 1291 | debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1292 | if (unq_mrs_en) { /* unique mode registers are supported */ |
| 1293 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
| 1294 | switch (i) { |
| 1295 | case 1: |
| 1296 | ddr->ddr_sdram_mode_12 = (0 |
| 1297 | | ((esdmode6 & 0xFFFF) << 16) |
| 1298 | | ((esdmode7 & 0xFFFF) << 0) |
| 1299 | ); |
| 1300 | break; |
| 1301 | case 2: |
| 1302 | ddr->ddr_sdram_mode_14 = (0 |
| 1303 | | ((esdmode6 & 0xFFFF) << 16) |
| 1304 | | ((esdmode7 & 0xFFFF) << 0) |
| 1305 | ); |
| 1306 | break; |
| 1307 | case 3: |
| 1308 | ddr->ddr_sdram_mode_16 = (0 |
| 1309 | | ((esdmode6 & 0xFFFF) << 16) |
| 1310 | | ((esdmode7 & 0xFFFF) << 0) |
| 1311 | ); |
| 1312 | break; |
| 1313 | } |
| 1314 | } |
| 1315 | debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n", |
| 1316 | ddr->ddr_sdram_mode_12); |
| 1317 | debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n", |
| 1318 | ddr->ddr_sdram_mode_14); |
| 1319 | debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n", |
| 1320 | ddr->ddr_sdram_mode_16); |
| 1321 | } |
| 1322 | } |
| 1323 | |
| 1324 | #endif |
| 1325 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1326 | /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1327 | static void set_ddr_sdram_interval(const unsigned int ctrl_num, |
| 1328 | fsl_ddr_cfg_regs_t *ddr, |
| 1329 | const memctl_options_t *popts, |
| 1330 | const common_timing_params_t *common_dimm) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1331 | { |
| 1332 | unsigned int refint; /* Refresh interval */ |
| 1333 | unsigned int bstopre; /* Precharge interval */ |
| 1334 | |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1335 | refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1336 | |
| 1337 | bstopre = popts->bstopre; |
| 1338 | |
| 1339 | /* refint field used 0x3FFF in earlier controllers */ |
| 1340 | ddr->ddr_sdram_interval = (0 |
| 1341 | | ((refint & 0xFFFF) << 16) |
| 1342 | | ((bstopre & 0x3FFF) << 0) |
| 1343 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1344 | debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1345 | } |
| 1346 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1347 | #ifdef CONFIG_SYS_FSL_DDR4 |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1348 | /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1349 | static void set_ddr_sdram_mode(const unsigned int ctrl_num, |
| 1350 | fsl_ddr_cfg_regs_t *ddr, |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1351 | const memctl_options_t *popts, |
| 1352 | const common_timing_params_t *common_dimm, |
| 1353 | unsigned int cas_latency, |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1354 | unsigned int additive_latency, |
| 1355 | const unsigned int unq_mrs_en) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1356 | { |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1357 | int i; |
| 1358 | unsigned short esdmode; /* Extended SDRAM mode */ |
| 1359 | unsigned short sdmode; /* SDRAM mode */ |
| 1360 | |
| 1361 | /* Mode Register - MR1 */ |
| 1362 | unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ |
| 1363 | unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ |
| 1364 | unsigned int rtt; |
| 1365 | unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ |
| 1366 | unsigned int al = 0; /* Posted CAS# additive latency (AL) */ |
| 1367 | unsigned int dic = 0; /* Output driver impedance, 40ohm */ |
| 1368 | unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal), |
| 1369 | 0=Disable (Test/Debug) */ |
| 1370 | |
| 1371 | /* Mode Register - MR0 */ |
| 1372 | unsigned int wr = 0; /* Write Recovery */ |
| 1373 | unsigned int dll_rst; /* DLL Reset */ |
| 1374 | unsigned int mode; /* Normal=0 or Test=1 */ |
| 1375 | unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ |
| 1376 | /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ |
| 1377 | unsigned int bt; |
| 1378 | unsigned int bl; /* BL: Burst Length */ |
| 1379 | |
| 1380 | unsigned int wr_mclk; |
| 1381 | /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */ |
| 1382 | static const u8 wr_table[] = { |
| 1383 | 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6}; |
| 1384 | /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */ |
| 1385 | static const u8 cas_latency_table[] = { |
| 1386 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, |
| 1387 | 9, 9, 10, 10, 11, 11}; |
| 1388 | |
| 1389 | if (popts->rtt_override) |
| 1390 | rtt = popts->rtt_override_value; |
| 1391 | else |
| 1392 | rtt = popts->cs_local_opts[0].odt_rtt_norm; |
| 1393 | |
| 1394 | if (additive_latency == (cas_latency - 1)) |
| 1395 | al = 1; |
| 1396 | if (additive_latency == (cas_latency - 2)) |
| 1397 | al = 2; |
| 1398 | |
| 1399 | if (popts->quad_rank_present) |
| 1400 | dic = 1; /* output driver impedance 240/7 ohm */ |
| 1401 | |
| 1402 | /* |
| 1403 | * The esdmode value will also be used for writing |
| 1404 | * MR1 during write leveling for DDR3, although the |
| 1405 | * bits specifically related to the write leveling |
| 1406 | * scheme will be handled automatically by the DDR |
| 1407 | * controller. so we set the wrlvl_en = 0 here. |
| 1408 | */ |
| 1409 | esdmode = (0 |
| 1410 | | ((qoff & 0x1) << 12) |
| 1411 | | ((tdqs_en & 0x1) << 11) |
| 1412 | | ((rtt & 0x7) << 8) |
| 1413 | | ((wrlvl_en & 0x1) << 7) |
| 1414 | | ((al & 0x3) << 3) |
| 1415 | | ((dic & 0x3) << 1) /* DIC field is split */ |
| 1416 | | ((dll_en & 0x1) << 0) |
| 1417 | ); |
| 1418 | |
| 1419 | /* |
| 1420 | * DLL control for precharge PD |
| 1421 | * 0=slow exit DLL off (tXPDLL) |
| 1422 | * 1=fast exit DLL on (tXP) |
| 1423 | */ |
| 1424 | |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1425 | wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1426 | if (wr_mclk <= 24) { |
| 1427 | wr = wr_table[wr_mclk - 10]; |
| 1428 | } else { |
| 1429 | printf("Error: unsupported write recovery for mode register wr_mclk = %d\n", |
| 1430 | wr_mclk); |
| 1431 | } |
| 1432 | |
| 1433 | dll_rst = 0; /* dll no reset */ |
| 1434 | mode = 0; /* normal mode */ |
| 1435 | |
| 1436 | /* look up table to get the cas latency bits */ |
| 1437 | if (cas_latency >= 9 && cas_latency <= 24) |
| 1438 | caslat = cas_latency_table[cas_latency - 9]; |
| 1439 | else |
| 1440 | printf("Error: unsupported cas latency for mode register\n"); |
| 1441 | |
| 1442 | bt = 0; /* Nibble sequential */ |
| 1443 | |
| 1444 | switch (popts->burst_length) { |
| 1445 | case DDR_BL8: |
| 1446 | bl = 0; |
| 1447 | break; |
| 1448 | case DDR_OTF: |
| 1449 | bl = 1; |
| 1450 | break; |
| 1451 | case DDR_BC4: |
| 1452 | bl = 2; |
| 1453 | break; |
| 1454 | default: |
| 1455 | printf("Error: invalid burst length of %u specified. ", |
| 1456 | popts->burst_length); |
| 1457 | puts("Defaulting to on-the-fly BC4 or BL8 beats.\n"); |
| 1458 | bl = 1; |
| 1459 | break; |
| 1460 | } |
| 1461 | |
| 1462 | sdmode = (0 |
| 1463 | | ((wr & 0x7) << 9) |
| 1464 | | ((dll_rst & 0x1) << 8) |
| 1465 | | ((mode & 0x1) << 7) |
| 1466 | | (((caslat >> 1) & 0x7) << 4) |
| 1467 | | ((bt & 0x1) << 3) |
| 1468 | | ((caslat & 1) << 2) |
| 1469 | | ((bl & 0x3) << 0) |
| 1470 | ); |
| 1471 | |
| 1472 | ddr->ddr_sdram_mode = (0 |
| 1473 | | ((esdmode & 0xFFFF) << 16) |
| 1474 | | ((sdmode & 0xFFFF) << 0) |
| 1475 | ); |
| 1476 | |
| 1477 | debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); |
| 1478 | |
| 1479 | if (unq_mrs_en) { /* unique mode registers are supported */ |
| 1480 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
| 1481 | if (popts->rtt_override) |
| 1482 | rtt = popts->rtt_override_value; |
| 1483 | else |
| 1484 | rtt = popts->cs_local_opts[i].odt_rtt_norm; |
| 1485 | |
| 1486 | esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */ |
| 1487 | esdmode |= (rtt & 0x7) << 8; |
| 1488 | switch (i) { |
| 1489 | case 1: |
| 1490 | ddr->ddr_sdram_mode_3 = (0 |
| 1491 | | ((esdmode & 0xFFFF) << 16) |
| 1492 | | ((sdmode & 0xFFFF) << 0) |
| 1493 | ); |
| 1494 | break; |
| 1495 | case 2: |
| 1496 | ddr->ddr_sdram_mode_5 = (0 |
| 1497 | | ((esdmode & 0xFFFF) << 16) |
| 1498 | | ((sdmode & 0xFFFF) << 0) |
| 1499 | ); |
| 1500 | break; |
| 1501 | case 3: |
| 1502 | ddr->ddr_sdram_mode_7 = (0 |
| 1503 | | ((esdmode & 0xFFFF) << 16) |
| 1504 | | ((sdmode & 0xFFFF) << 0) |
| 1505 | ); |
| 1506 | break; |
| 1507 | } |
| 1508 | } |
| 1509 | debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", |
| 1510 | ddr->ddr_sdram_mode_3); |
| 1511 | debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", |
| 1512 | ddr->ddr_sdram_mode_5); |
| 1513 | debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", |
| 1514 | ddr->ddr_sdram_mode_5); |
| 1515 | } |
| 1516 | } |
| 1517 | |
| 1518 | #elif defined(CONFIG_SYS_FSL_DDR3) |
| 1519 | /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1520 | static void set_ddr_sdram_mode(const unsigned int ctrl_num, |
| 1521 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1522 | const memctl_options_t *popts, |
| 1523 | const common_timing_params_t *common_dimm, |
| 1524 | unsigned int cas_latency, |
| 1525 | unsigned int additive_latency, |
| 1526 | const unsigned int unq_mrs_en) |
| 1527 | { |
| 1528 | int i; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1529 | unsigned short esdmode; /* Extended SDRAM mode */ |
| 1530 | unsigned short sdmode; /* SDRAM mode */ |
| 1531 | |
| 1532 | /* Mode Register - MR1 */ |
| 1533 | unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ |
| 1534 | unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ |
| 1535 | unsigned int rtt; |
| 1536 | unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ |
| 1537 | unsigned int al = 0; /* Posted CAS# additive latency (AL) */ |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1538 | unsigned int dic = 0; /* Output driver impedance, 40ohm */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1539 | unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), |
| 1540 | 1=Disable (Test/Debug) */ |
| 1541 | |
| 1542 | /* Mode Register - MR0 */ |
| 1543 | unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ |
York Sun | fcea306 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1544 | unsigned int wr = 0; /* Write Recovery */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1545 | unsigned int dll_rst; /* DLL Reset */ |
| 1546 | unsigned int mode; /* Normal=0 or Test=1 */ |
| 1547 | unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ |
| 1548 | /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ |
| 1549 | unsigned int bt; |
| 1550 | unsigned int bl; /* BL: Burst Length */ |
| 1551 | |
| 1552 | unsigned int wr_mclk; |
York Sun | f5b6fb7 | 2011-03-02 14:24:11 -0800 | [diff] [blame] | 1553 | /* |
| 1554 | * DDR_SDRAM_MODE doesn't support 9,11,13,15 |
| 1555 | * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 |
| 1556 | * for this table |
| 1557 | */ |
| 1558 | static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1559 | |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1560 | if (popts->rtt_override) |
| 1561 | rtt = popts->rtt_override_value; |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1562 | else |
| 1563 | rtt = popts->cs_local_opts[0].odt_rtt_norm; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1564 | |
| 1565 | if (additive_latency == (cas_latency - 1)) |
| 1566 | al = 1; |
| 1567 | if (additive_latency == (cas_latency - 2)) |
| 1568 | al = 2; |
| 1569 | |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1570 | if (popts->quad_rank_present) |
| 1571 | dic = 1; /* output driver impedance 240/7 ohm */ |
| 1572 | |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1573 | /* |
| 1574 | * The esdmode value will also be used for writing |
| 1575 | * MR1 during write leveling for DDR3, although the |
| 1576 | * bits specifically related to the write leveling |
| 1577 | * scheme will be handled automatically by the DDR |
| 1578 | * controller. so we set the wrlvl_en = 0 here. |
| 1579 | */ |
| 1580 | esdmode = (0 |
| 1581 | | ((qoff & 0x1) << 12) |
| 1582 | | ((tdqs_en & 0x1) << 11) |
Kumar Gala | 6d8565a | 2009-09-10 14:54:55 -0500 | [diff] [blame] | 1583 | | ((rtt & 0x4) << 7) /* rtt field is split */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1584 | | ((wrlvl_en & 0x1) << 7) |
Kumar Gala | 6d8565a | 2009-09-10 14:54:55 -0500 | [diff] [blame] | 1585 | | ((rtt & 0x2) << 5) /* rtt field is split */ |
| 1586 | | ((dic & 0x2) << 4) /* DIC field is split */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1587 | | ((al & 0x3) << 3) |
Kumar Gala | 6d8565a | 2009-09-10 14:54:55 -0500 | [diff] [blame] | 1588 | | ((rtt & 0x1) << 2) /* rtt field is split */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1589 | | ((dic & 0x1) << 1) /* DIC field is split */ |
| 1590 | | ((dll_en & 0x1) << 0) |
| 1591 | ); |
| 1592 | |
| 1593 | /* |
| 1594 | * DLL control for precharge PD |
| 1595 | * 0=slow exit DLL off (tXPDLL) |
| 1596 | * 1=fast exit DLL on (tXP) |
| 1597 | */ |
| 1598 | dll_on = 1; |
York Sun | f5b6fb7 | 2011-03-02 14:24:11 -0800 | [diff] [blame] | 1599 | |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1600 | wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
York Sun | fcea306 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1601 | if (wr_mclk <= 16) { |
| 1602 | wr = wr_table[wr_mclk - 5]; |
| 1603 | } else { |
| 1604 | printf("Error: unsupported write recovery for mode register " |
| 1605 | "wr_mclk = %d\n", wr_mclk); |
| 1606 | } |
York Sun | f5b6fb7 | 2011-03-02 14:24:11 -0800 | [diff] [blame] | 1607 | |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1608 | dll_rst = 0; /* dll no reset */ |
| 1609 | mode = 0; /* normal mode */ |
| 1610 | |
| 1611 | /* look up table to get the cas latency bits */ |
York Sun | fcea306 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1612 | if (cas_latency >= 5 && cas_latency <= 16) { |
| 1613 | unsigned char cas_latency_table[] = { |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1614 | 0x2, /* 5 clocks */ |
| 1615 | 0x4, /* 6 clocks */ |
| 1616 | 0x6, /* 7 clocks */ |
| 1617 | 0x8, /* 8 clocks */ |
| 1618 | 0xa, /* 9 clocks */ |
| 1619 | 0xc, /* 10 clocks */ |
York Sun | fcea306 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1620 | 0xe, /* 11 clocks */ |
| 1621 | 0x1, /* 12 clocks */ |
| 1622 | 0x3, /* 13 clocks */ |
| 1623 | 0x5, /* 14 clocks */ |
| 1624 | 0x7, /* 15 clocks */ |
| 1625 | 0x9, /* 16 clocks */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1626 | }; |
| 1627 | caslat = cas_latency_table[cas_latency - 5]; |
York Sun | fcea306 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1628 | } else { |
| 1629 | printf("Error: unsupported cas latency for mode register\n"); |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1630 | } |
York Sun | fcea306 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1631 | |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1632 | bt = 0; /* Nibble sequential */ |
| 1633 | |
| 1634 | switch (popts->burst_length) { |
| 1635 | case DDR_BL8: |
| 1636 | bl = 0; |
| 1637 | break; |
| 1638 | case DDR_OTF: |
| 1639 | bl = 1; |
| 1640 | break; |
| 1641 | case DDR_BC4: |
| 1642 | bl = 2; |
| 1643 | break; |
| 1644 | default: |
| 1645 | printf("Error: invalid burst length of %u specified. " |
| 1646 | " Defaulting to on-the-fly BC4 or BL8 beats.\n", |
| 1647 | popts->burst_length); |
| 1648 | bl = 1; |
| 1649 | break; |
| 1650 | } |
| 1651 | |
| 1652 | sdmode = (0 |
| 1653 | | ((dll_on & 0x1) << 12) |
| 1654 | | ((wr & 0x7) << 9) |
| 1655 | | ((dll_rst & 0x1) << 8) |
| 1656 | | ((mode & 0x1) << 7) |
| 1657 | | (((caslat >> 1) & 0x7) << 4) |
| 1658 | | ((bt & 0x1) << 3) |
York Sun | fcea306 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1659 | | ((caslat & 1) << 2) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1660 | | ((bl & 0x3) << 0) |
| 1661 | ); |
| 1662 | |
| 1663 | ddr->ddr_sdram_mode = (0 |
| 1664 | | ((esdmode & 0xFFFF) << 16) |
| 1665 | | ((sdmode & 0xFFFF) << 0) |
| 1666 | ); |
| 1667 | |
| 1668 | debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1669 | |
| 1670 | if (unq_mrs_en) { /* unique mode registers are supported */ |
Kumar Gala | dea7f88 | 2011-11-09 10:05:10 -0600 | [diff] [blame] | 1671 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1672 | if (popts->rtt_override) |
| 1673 | rtt = popts->rtt_override_value; |
| 1674 | else |
| 1675 | rtt = popts->cs_local_opts[i].odt_rtt_norm; |
| 1676 | |
| 1677 | esdmode &= 0xFDBB; /* clear bit 9,6,2 */ |
| 1678 | esdmode |= (0 |
| 1679 | | ((rtt & 0x4) << 7) /* rtt field is split */ |
| 1680 | | ((rtt & 0x2) << 5) /* rtt field is split */ |
| 1681 | | ((rtt & 0x1) << 2) /* rtt field is split */ |
| 1682 | ); |
| 1683 | switch (i) { |
| 1684 | case 1: |
| 1685 | ddr->ddr_sdram_mode_3 = (0 |
| 1686 | | ((esdmode & 0xFFFF) << 16) |
| 1687 | | ((sdmode & 0xFFFF) << 0) |
| 1688 | ); |
| 1689 | break; |
| 1690 | case 2: |
| 1691 | ddr->ddr_sdram_mode_5 = (0 |
| 1692 | | ((esdmode & 0xFFFF) << 16) |
| 1693 | | ((sdmode & 0xFFFF) << 0) |
| 1694 | ); |
| 1695 | break; |
| 1696 | case 3: |
| 1697 | ddr->ddr_sdram_mode_7 = (0 |
| 1698 | | ((esdmode & 0xFFFF) << 16) |
| 1699 | | ((sdmode & 0xFFFF) << 0) |
| 1700 | ); |
| 1701 | break; |
| 1702 | } |
| 1703 | } |
| 1704 | debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", |
| 1705 | ddr->ddr_sdram_mode_3); |
| 1706 | debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", |
| 1707 | ddr->ddr_sdram_mode_5); |
| 1708 | debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", |
| 1709 | ddr->ddr_sdram_mode_5); |
| 1710 | } |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1711 | } |
| 1712 | |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1713 | #else /* !CONFIG_SYS_FSL_DDR3 */ |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1714 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1715 | /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1716 | static void set_ddr_sdram_mode(const unsigned int ctrl_num, |
| 1717 | fsl_ddr_cfg_regs_t *ddr, |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1718 | const memctl_options_t *popts, |
| 1719 | const common_timing_params_t *common_dimm, |
| 1720 | unsigned int cas_latency, |
York Sun | e1fd16b | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1721 | unsigned int additive_latency, |
| 1722 | const unsigned int unq_mrs_en) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1723 | { |
| 1724 | unsigned short esdmode; /* Extended SDRAM mode */ |
| 1725 | unsigned short sdmode; /* SDRAM mode */ |
| 1726 | |
| 1727 | /* |
| 1728 | * FIXME: This ought to be pre-calculated in a |
| 1729 | * technology-specific routine, |
| 1730 | * e.g. compute_DDR2_mode_register(), and then the |
| 1731 | * sdmode and esdmode passed in as part of common_dimm. |
| 1732 | */ |
| 1733 | |
| 1734 | /* Extended Mode Register */ |
| 1735 | unsigned int mrs = 0; /* Mode Register Set */ |
| 1736 | unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ |
| 1737 | unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ |
| 1738 | unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ |
| 1739 | unsigned int ocd = 0; /* 0x0=OCD not supported, |
| 1740 | 0x7=OCD default state */ |
| 1741 | unsigned int rtt; |
| 1742 | unsigned int al; /* Posted CAS# additive latency (AL) */ |
| 1743 | unsigned int ods = 0; /* Output Drive Strength: |
| 1744 | 0 = Full strength (18ohm) |
| 1745 | 1 = Reduced strength (4ohm) */ |
| 1746 | unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), |
| 1747 | 1=Disable (Test/Debug) */ |
| 1748 | |
| 1749 | /* Mode Register (MR) */ |
| 1750 | unsigned int mr; /* Mode Register Definition */ |
| 1751 | unsigned int pd; /* Power-Down Mode */ |
| 1752 | unsigned int wr; /* Write Recovery */ |
| 1753 | unsigned int dll_res; /* DLL Reset */ |
| 1754 | unsigned int mode; /* Normal=0 or Test=1 */ |
Kumar Gala | 302e52e | 2008-09-05 14:40:29 -0500 | [diff] [blame] | 1755 | unsigned int caslat = 0;/* CAS# latency */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1756 | /* BT: Burst Type (0=Sequential, 1=Interleaved) */ |
| 1757 | unsigned int bt; |
| 1758 | unsigned int bl; /* BL: Burst Length */ |
| 1759 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 1760 | dqs_en = !popts->dqs_config; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1761 | rtt = fsl_ddr_get_rtt(); |
| 1762 | |
| 1763 | al = additive_latency; |
| 1764 | |
| 1765 | esdmode = (0 |
| 1766 | | ((mrs & 0x3) << 14) |
| 1767 | | ((outputs & 0x1) << 12) |
| 1768 | | ((rdqs_en & 0x1) << 11) |
| 1769 | | ((dqs_en & 0x1) << 10) |
| 1770 | | ((ocd & 0x7) << 7) |
| 1771 | | ((rtt & 0x2) << 5) /* rtt field is split */ |
| 1772 | | ((al & 0x7) << 3) |
| 1773 | | ((rtt & 0x1) << 2) /* rtt field is split */ |
| 1774 | | ((ods & 0x1) << 1) |
| 1775 | | ((dll_en & 0x1) << 0) |
| 1776 | ); |
| 1777 | |
| 1778 | mr = 0; /* FIXME: CHECKME */ |
| 1779 | |
| 1780 | /* |
| 1781 | * 0 = Fast Exit (Normal) |
| 1782 | * 1 = Slow Exit (Low Power) |
| 1783 | */ |
| 1784 | pd = 0; |
| 1785 | |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1786 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1787 | wr = 0; /* Historical */ |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1788 | #elif defined(CONFIG_SYS_FSL_DDR2) |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1789 | wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1790 | #endif |
| 1791 | dll_res = 0; |
| 1792 | mode = 0; |
| 1793 | |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1794 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1795 | if (1 <= cas_latency && cas_latency <= 4) { |
| 1796 | unsigned char mode_caslat_table[4] = { |
| 1797 | 0x5, /* 1.5 clocks */ |
| 1798 | 0x2, /* 2.0 clocks */ |
| 1799 | 0x6, /* 2.5 clocks */ |
| 1800 | 0x3 /* 3.0 clocks */ |
| 1801 | }; |
Kumar Gala | 302e52e | 2008-09-05 14:40:29 -0500 | [diff] [blame] | 1802 | caslat = mode_caslat_table[cas_latency - 1]; |
| 1803 | } else { |
| 1804 | printf("Warning: unknown cas_latency %d\n", cas_latency); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1805 | } |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1806 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1807 | caslat = cas_latency; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1808 | #endif |
| 1809 | bt = 0; |
| 1810 | |
| 1811 | switch (popts->burst_length) { |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1812 | case DDR_BL4: |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1813 | bl = 2; |
| 1814 | break; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1815 | case DDR_BL8: |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1816 | bl = 3; |
| 1817 | break; |
| 1818 | default: |
| 1819 | printf("Error: invalid burst length of %u specified. " |
| 1820 | " Defaulting to 4 beats.\n", |
| 1821 | popts->burst_length); |
| 1822 | bl = 2; |
| 1823 | break; |
| 1824 | } |
| 1825 | |
| 1826 | sdmode = (0 |
| 1827 | | ((mr & 0x3) << 14) |
| 1828 | | ((pd & 0x1) << 12) |
| 1829 | | ((wr & 0x7) << 9) |
| 1830 | | ((dll_res & 0x1) << 8) |
| 1831 | | ((mode & 0x1) << 7) |
| 1832 | | ((caslat & 0x7) << 4) |
| 1833 | | ((bt & 0x1) << 3) |
| 1834 | | ((bl & 0x7) << 0) |
| 1835 | ); |
| 1836 | |
| 1837 | ddr->ddr_sdram_mode = (0 |
| 1838 | | ((esdmode & 0xFFFF) << 16) |
| 1839 | | ((sdmode & 0xFFFF) << 0) |
| 1840 | ); |
Haiying Wang | 1f293b4 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1841 | debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1842 | } |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1843 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1844 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1845 | /* |
| 1846 | * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) |
| 1847 | * The old controller on the 8540/60 doesn't have this register. |
| 1848 | * Hope it's OK to set it (to 0) anyway. |
| 1849 | */ |
| 1850 | static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, |
| 1851 | const memctl_options_t *popts) |
| 1852 | { |
Tom Rini | 9889860 | 2021-05-14 21:34:21 -0400 | [diff] [blame] | 1853 | if (fsl_ddr_get_version(0) >= 0x40701) |
Shengzhou Liu | d8e5163 | 2016-05-04 10:20:21 +0800 | [diff] [blame] | 1854 | /* clk_adjust in 5-bits on T-series and LS-series */ |
Tom Rini | 9889860 | 2021-05-14 21:34:21 -0400 | [diff] [blame] | 1855 | ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22; |
| 1856 | else |
Shengzhou Liu | d8e5163 | 2016-05-04 10:20:21 +0800 | [diff] [blame] | 1857 | /* clk_adjust in 4-bits on earlier MPC85xx and P-series */ |
Tom Rini | 9889860 | 2021-05-14 21:34:21 -0400 | [diff] [blame] | 1858 | ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23; |
Shengzhou Liu | d8e5163 | 2016-05-04 10:20:21 +0800 | [diff] [blame] | 1859 | |
york | 9490ff4 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 1860 | debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [ |