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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002/*
York Sunc0c32af2018-01-29 09:44:35 -08003 * Copyright 2008-2016 Freescale Semiconductor, Inc.
Jaiprakash Singh164a5af2020-06-02 12:44:02 +05304 * Copyright 2017-2020 NXP Semiconductor
Kumar Gala58e5e9a2008-08-26 15:01:29 -05005 */
6
7/*
Shengzhou Liu02fb2762016-11-21 11:36:48 +08008 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05009 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13#include <common.h>
York Sun5614e712013-09-30 09:22:09 -070014#include <fsl_ddr_sdram.h>
Shengzhou Liu02fb2762016-11-21 11:36:48 +080015#include <fsl_errata.h>
York Sun5614e712013-09-30 09:22:09 -070016#include <fsl_ddr.h>
York Sun9a17eb52013-11-18 10:29:32 -080017#include <fsl_immap.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060018#include <log.h>
Simon Glasscd93d622020-05-10 11:40:13 -060019#include <asm/bitops.h>
York Sun5614e712013-09-30 09:22:09 -070020#include <asm/io.h>
Simon Glass457e51c2017-05-17 08:23:10 -060021#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
22 defined(CONFIG_ARM)
Simon Glass6e2941d2017-05-17 08:23:06 -060023#include <asm/arch/clock.h>
24#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -050025
Kumar Gala58e5e9a2008-08-26 15:01:29 -050026/*
27 * Determine Rtt value.
28 *
29 * This should likely be either board or controller specific.
30 *
Dave Liuc360cea2009-03-14 12:48:30 +080031 * Rtt(nominal) - DDR2:
Kumar Gala58e5e9a2008-08-26 15:01:29 -050032 * 0 = Rtt disabled
33 * 1 = 75 ohm
34 * 2 = 150 ohm
35 * 3 = 50 ohm
Dave Liuc360cea2009-03-14 12:48:30 +080036 * Rtt(nominal) - DDR3:
37 * 0 = Rtt disabled
38 * 1 = 60 ohm
39 * 2 = 120 ohm
40 * 3 = 40 ohm
41 * 4 = 20 ohm
42 * 5 = 30 ohm
Kumar Gala58e5e9a2008-08-26 15:01:29 -050043 *
44 * FIXME: Apparently 8641 needs a value of 2
45 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
46 *
47 * FIXME: There was some effort down this line earlier:
48 *
49 * unsigned int i;
50 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
51 * if (popts->dimmslot[i].num_valid_cs
52 * && (popts->cs_local_opts[2*i].odt_rd_cfg
53 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
54 * rtt = 2;
55 * break;
56 * }
57 * }
58 */
59static inline int fsl_ddr_get_rtt(void)
60{
61 int rtt;
62
York Sun5614e712013-09-30 09:22:09 -070063#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050064 rtt = 0;
York Sun5614e712013-09-30 09:22:09 -070065#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050066 rtt = 3;
67#else
Dave Liuc360cea2009-03-14 12:48:30 +080068 rtt = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -050069#endif
70
71 return rtt;
72}
73
York Sun34e026f2014-03-27 17:54:47 -070074#ifdef CONFIG_SYS_FSL_DDR4
75/*
76 * compute CAS write latency according to DDR4 spec
77 * CWL = 9 for <= 1600MT/s
78 * 10 for <= 1866MT/s
79 * 11 for <= 2133MT/s
80 * 12 for <= 2400MT/s
81 * 14 for <= 2667MT/s
82 * 16 for <= 2933MT/s
83 * 18 for higher
84 */
York Sun03e664d2015-01-06 13:18:50 -080085static inline unsigned int compute_cas_write_latency(
86 const unsigned int ctrl_num)
York Sun34e026f2014-03-27 17:54:47 -070087{
88 unsigned int cwl;
York Sun03e664d2015-01-06 13:18:50 -080089 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sun34e026f2014-03-27 17:54:47 -070090 if (mclk_ps >= 1250)
91 cwl = 9;
92 else if (mclk_ps >= 1070)
93 cwl = 10;
94 else if (mclk_ps >= 935)
95 cwl = 11;
96 else if (mclk_ps >= 833)
97 cwl = 12;
98 else if (mclk_ps >= 750)
99 cwl = 14;
100 else if (mclk_ps >= 681)
101 cwl = 16;
102 else
103 cwl = 18;
104
105 return cwl;
106}
107#else
Dave Liuc360cea2009-03-14 12:48:30 +0800108/*
109 * compute the CAS write latency according to DDR3 spec
110 * CWL = 5 if tCK >= 2.5ns
111 * 6 if 2.5ns > tCK >= 1.875ns
112 * 7 if 1.875ns > tCK >= 1.5ns
113 * 8 if 1.5ns > tCK >= 1.25ns
York Sun2bba85f2011-08-24 09:40:25 -0700114 * 9 if 1.25ns > tCK >= 1.07ns
115 * 10 if 1.07ns > tCK >= 0.935ns
116 * 11 if 0.935ns > tCK >= 0.833ns
117 * 12 if 0.833ns > tCK >= 0.75ns
Dave Liuc360cea2009-03-14 12:48:30 +0800118 */
York Sun03e664d2015-01-06 13:18:50 -0800119static inline unsigned int compute_cas_write_latency(
120 const unsigned int ctrl_num)
Dave Liuc360cea2009-03-14 12:48:30 +0800121{
122 unsigned int cwl;
York Sun03e664d2015-01-06 13:18:50 -0800123 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
Dave Liuc360cea2009-03-14 12:48:30 +0800124
125 if (mclk_ps >= 2500)
126 cwl = 5;
127 else if (mclk_ps >= 1875)
128 cwl = 6;
129 else if (mclk_ps >= 1500)
130 cwl = 7;
131 else if (mclk_ps >= 1250)
132 cwl = 8;
York Sun2bba85f2011-08-24 09:40:25 -0700133 else if (mclk_ps >= 1070)
134 cwl = 9;
135 else if (mclk_ps >= 935)
136 cwl = 10;
137 else if (mclk_ps >= 833)
138 cwl = 11;
139 else if (mclk_ps >= 750)
140 cwl = 12;
141 else {
142 cwl = 12;
143 printf("Warning: CWL is out of range\n");
144 }
Dave Liuc360cea2009-03-14 12:48:30 +0800145 return cwl;
146}
York Sun34e026f2014-03-27 17:54:47 -0700147#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800148
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500149/* Chip Select Configuration (CSn_CONFIG) */
york5800e7a2010-07-02 22:25:53 +0000150static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500151 const memctl_options_t *popts,
152 const dimm_params_t *dimm_params)
153{
154 unsigned int cs_n_en = 0; /* Chip Select enable */
155 unsigned int intlv_en = 0; /* Memory controller interleave enable */
156 unsigned int intlv_ctl = 0; /* Interleaving control */
157 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
158 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
159 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
160 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
161 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
162 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
york5800e7a2010-07-02 22:25:53 +0000163 int go_config = 0;
York Sun34e026f2014-03-27 17:54:47 -0700164#ifdef CONFIG_SYS_FSL_DDR4
165 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
166#else
167 unsigned int n_banks_per_sdram_device;
168#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500169
170 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
york5800e7a2010-07-02 22:25:53 +0000171 switch (i) {
172 case 0:
173 if (dimm_params[dimm_number].n_ranks > 0) {
174 go_config = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500175 /* These fields only available in CS0_CONFIG */
York Suna4c66502012-08-17 08:22:39 +0000176 if (!popts->memctl_interleaving)
177 break;
178 switch (popts->memctl_interleaving_mode) {
York Sun6b1e1252014-02-10 13:59:44 -0800179 case FSL_DDR_256B_INTERLEAVING:
York Suna4c66502012-08-17 08:22:39 +0000180 case FSL_DDR_CACHE_LINE_INTERLEAVING:
181 case FSL_DDR_PAGE_INTERLEAVING:
182 case FSL_DDR_BANK_INTERLEAVING:
183 case FSL_DDR_SUPERBANK_INTERLEAVING:
184 intlv_en = popts->memctl_interleaving;
185 intlv_ctl = popts->memctl_interleaving_mode;
186 break;
187 default:
188 break;
189 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500190 }
york5800e7a2010-07-02 22:25:53 +0000191 break;
192 case 1:
193 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
194 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
195 go_config = 1;
196 break;
197 case 2:
198 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
York Suncae7c1b2011-08-26 11:32:40 -0700199 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
york5800e7a2010-07-02 22:25:53 +0000200 go_config = 1;
201 break;
202 case 3:
203 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
204 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
205 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
206 go_config = 1;
207 break;
208 default:
209 break;
210 }
211 if (go_config) {
york5800e7a2010-07-02 22:25:53 +0000212 cs_n_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500213 ap_n_en = popts->cs_local_opts[i].auto_precharge;
214 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
215 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
York Sun34e026f2014-03-27 17:54:47 -0700216#ifdef CONFIG_SYS_FSL_DDR4
Sean Anderson6f6fbb32022-08-30 17:01:07 -0400217 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits - 2;
York Sun34e026f2014-03-27 17:54:47 -0700218 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
219#else
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500220 n_banks_per_sdram_device
york5800e7a2010-07-02 22:25:53 +0000221 = dimm_params[dimm_number].n_banks_per_sdram_device;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500222 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
York Sun34e026f2014-03-27 17:54:47 -0700223#endif
york5800e7a2010-07-02 22:25:53 +0000224 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
225 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500226 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500227 ddr->cs[i].config = (0
228 | ((cs_n_en & 0x1) << 31)
229 | ((intlv_en & 0x3) << 29)
Haiying Wangdbbbb3a2008-10-03 12:36:39 -0400230 | ((intlv_ctl & 0xf) << 24)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500231 | ((ap_n_en & 0x1) << 23)
232
233 /* XXX: some implementation only have 1 bit starting at left */
234 | ((odt_rd_cfg & 0x7) << 20)
235
236 /* XXX: Some implementation only have 1 bit starting at left */
237 | ((odt_wr_cfg & 0x7) << 16)
238
239 | ((ba_bits_cs_n & 0x3) << 14)
240 | ((row_bits_cs_n & 0x7) << 8)
York Sun34e026f2014-03-27 17:54:47 -0700241#ifdef CONFIG_SYS_FSL_DDR4
242 | ((bg_bits_cs_n & 0x3) << 4)
243#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500244 | ((col_bits_cs_n & 0x7) << 0)
245 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400246 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500247}
248
249/* Chip Select Configuration 2 (CSn_CONFIG_2) */
250/* FIXME: 8572 */
251static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
252{
253 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
254
255 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
Haiying Wang1f293b42008-10-03 12:37:26 -0400256 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500257}
258
259/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
260
York Sun5614e712013-09-30 09:22:09 -0700261#if !defined(CONFIG_SYS_FSL_DDR1)
York Sun84baed22014-11-07 12:14:36 -0800262/*
263 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
264 * Return 1 if other two slots configuration. Return 0 if single slot.
265 */
York Sun123922b2012-10-08 07:44:23 +0000266static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
267{
268#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
269 if (dimm_params[0].n_ranks == 4)
York Sun84baed22014-11-07 12:14:36 -0800270 return 2;
York Sun123922b2012-10-08 07:44:23 +0000271#endif
272
273#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
274 if ((dimm_params[0].n_ranks == 2) &&
275 (dimm_params[1].n_ranks == 2))
York Sun84baed22014-11-07 12:14:36 -0800276 return 2;
York Sun123922b2012-10-08 07:44:23 +0000277
278#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
279 if (dimm_params[0].n_ranks == 4)
York Sun84baed22014-11-07 12:14:36 -0800280 return 2;
York Sun123922b2012-10-08 07:44:23 +0000281#endif
York Sun84baed22014-11-07 12:14:36 -0800282
283 if ((dimm_params[0].n_ranks != 0) &&
284 (dimm_params[2].n_ranks != 0))
285 return 1;
York Sun123922b2012-10-08 07:44:23 +0000286#endif
287 return 0;
288}
289
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500290/*
291 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
292 *
293 * Avoid writing for DDR I. The new PQ38 DDR controller
294 * dreams up non-zero default values to be backwards compatible.
295 */
York Sun03e664d2015-01-06 13:18:50 -0800296static void set_timing_cfg_0(const unsigned int ctrl_num,
297 fsl_ddr_cfg_regs_t *ddr,
York Sun123922b2012-10-08 07:44:23 +0000298 const memctl_options_t *popts,
299 const dimm_params_t *dimm_params)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500300{
301 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
302 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
303 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
304 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
305 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
306
307 /* Active powerdown exit timing (tXARD and tXARDS). */
308 unsigned char act_pd_exit_mclk;
309 /* Precharge powerdown exit timing (tXP). */
310 unsigned char pre_pd_exit_mclk;
york5fb8a8a2010-07-02 22:25:56 +0000311 /* ODT powerdown exit timing (tAXPD). */
York Sun34e026f2014-03-27 17:54:47 -0700312 unsigned char taxpd_mclk = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500313 /* Mode register set cycle time (tMRD). */
314 unsigned char tmrd_mclk;
York Sunbb578322014-08-21 16:13:22 -0700315#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
York Sun03e664d2015-01-06 13:18:50 -0800316 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sunbb578322014-08-21 16:13:22 -0700317#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500318
York Sun34e026f2014-03-27 17:54:47 -0700319#ifdef CONFIG_SYS_FSL_DDR4
320 /* tXP=max(4nCK, 6ns) */
Masahiro Yamadab4141192014-11-07 03:03:31 +0900321 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
York Sun66869f92015-03-19 09:30:26 -0700322 unsigned int data_rate = get_ddr_freq(ctrl_num);
323
324 /* for faster clock, need more time for data setup */
325 trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
York Sun6c6e0062015-11-04 10:03:21 -0800326
327 /*
328 * for single quad-rank DIMM and two-slot DIMMs
329 * to avoid ODT overlap
330 */
331 switch (avoid_odt_overlap(dimm_params)) {
332 case 2:
333 twrt_mclk = 2;
334 twwt_mclk = 2;
335 trrt_mclk = 2;
336 break;
337 default:
338 twrt_mclk = 1;
339 twwt_mclk = 1;
340 trrt_mclk = 0;
341 break;
342 }
343
York Sun03e664d2015-01-06 13:18:50 -0800344 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
York Sun34e026f2014-03-27 17:54:47 -0700345 pre_pd_exit_mclk = act_pd_exit_mclk;
346 /*
347 * MRS_CYC = max(tMRD, tMOD)
348 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
349 */
York Sun03e664d2015-01-06 13:18:50 -0800350 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
York Sun34e026f2014-03-27 17:54:47 -0700351#elif defined(CONFIG_SYS_FSL_DDR3)
York Sun03e664d2015-01-06 13:18:50 -0800352 unsigned int data_rate = get_ddr_freq(ctrl_num);
York Sunbb578322014-08-21 16:13:22 -0700353 int txp;
York Sun938bbb62014-12-02 11:18:09 -0800354 unsigned int ip_rev;
York Sun84baed22014-11-07 12:14:36 -0800355 int odt_overlap;
Dave Liuc360cea2009-03-14 12:48:30 +0800356 /*
357 * (tXARD and tXARDS). Empirical?
358 * The DDR3 spec has not tXARD,
359 * we use the tXP instead of it.
York Sunbb578322014-08-21 16:13:22 -0700360 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
361 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
Dave Liuc360cea2009-03-14 12:48:30 +0800362 * spec has not the tAXPD, we use
york5fb8a8a2010-07-02 22:25:56 +0000363 * tAXPD=1, need design to confirm.
Dave Liuc360cea2009-03-14 12:48:30 +0800364 */
Masahiro Yamadab4141192014-11-07 03:03:31 +0900365 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
York Sunbb578322014-08-21 16:13:22 -0700366
York Sun66869f92015-03-19 09:30:26 -0700367 ip_rev = fsl_ddr_get_version(ctrl_num);
York Sun938bbb62014-12-02 11:18:09 -0800368 if (ip_rev >= 0x40700) {
369 /*
370 * MRS_CYC = max(tMRD, tMOD)
371 * tMRD = 4nCK (8nCK for RDIMM)
372 * tMOD = max(12nCK, 15ns)
373 */
York Sun03e664d2015-01-06 13:18:50 -0800374 tmrd_mclk = max((unsigned int)12,
375 picos_to_mclk(ctrl_num, 15000));
York Sun938bbb62014-12-02 11:18:09 -0800376 } else {
377 /*
378 * MRS_CYC = tMRD
379 * tMRD = 4nCK (8nCK for RDIMM)
380 */
381 if (popts->registered_dimm_en)
382 tmrd_mclk = 8;
383 else
384 tmrd_mclk = 4;
385 }
386
Dave Liu99bac472009-12-08 11:56:48 +0800387 /* set the turnaround time */
York Sun123922b2012-10-08 07:44:23 +0000388
389 /*
York Sun84baed22014-11-07 12:14:36 -0800390 * for single quad-rank DIMM and two-slot DIMMs
York Sun123922b2012-10-08 07:44:23 +0000391 * to avoid ODT overlap
392 */
York Sun84baed22014-11-07 12:14:36 -0800393 odt_overlap = avoid_odt_overlap(dimm_params);
394 switch (odt_overlap) {
395 case 2:
York Sun123922b2012-10-08 07:44:23 +0000396 twwt_mclk = 2;
397 trrt_mclk = 1;
York Sun84baed22014-11-07 12:14:36 -0800398 break;
399 case 1:
400 twwt_mclk = 1;
401 trrt_mclk = 0;
402 break;
403 default:
404 break;
York Sun123922b2012-10-08 07:44:23 +0000405 }
York Sun84baed22014-11-07 12:14:36 -0800406
York Sun123922b2012-10-08 07:44:23 +0000407 /* for faster clock, need more time for data setup */
408 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
409
York Sun856e4b02011-02-10 10:13:10 -0800410 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
411 twrt_mclk = 1;
York Sune1fd16b2011-01-10 12:03:00 +0000412
413 if (popts->dynamic_power == 0) { /* powerdown is not used */
414 act_pd_exit_mclk = 1;
415 pre_pd_exit_mclk = 1;
416 taxpd_mclk = 1;
417 } else {
418 /* act_pd_exit_mclk = tXARD, see above */
York Sun03e664d2015-01-06 13:18:50 -0800419 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
York Sune1fd16b2011-01-10 12:03:00 +0000420 /* Mode register MR0[A12] is '1' - fast exit */
421 pre_pd_exit_mclk = act_pd_exit_mclk;
422 taxpd_mclk = 1;
423 }
York Sun5614e712013-09-30 09:22:09 -0700424#else /* CONFIG_SYS_FSL_DDR2 */
Dave Liuc360cea2009-03-14 12:48:30 +0800425 /*
426 * (tXARD and tXARDS). Empirical?
427 * tXARD = 2 for DDR2
428 * tXP=2
429 * tAXPD=8
430 */
431 act_pd_exit_mclk = 2;
432 pre_pd_exit_mclk = 2;
433 taxpd_mclk = 8;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500434 tmrd_mclk = 2;
Dave Liuc360cea2009-03-14 12:48:30 +0800435#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500436
York Sun23f96702011-05-27 13:44:28 +0800437 if (popts->trwt_override)
438 trwt_mclk = popts->trwt;
439
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500440 ddr->timing_cfg_0 = (0
441 | ((trwt_mclk & 0x3) << 30) /* RWT */
442 | ((twrt_mclk & 0x3) << 28) /* WRT */
443 | ((trrt_mclk & 0x3) << 26) /* RRT */
444 | ((twwt_mclk & 0x3) << 24) /* WWT */
York Sund4263b82013-06-03 12:39:06 -0700445 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
Dave Liu22ff3d02008-11-21 16:31:29 +0800446 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500447 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
York Sund4263b82013-06-03 12:39:06 -0700448 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500449 );
450 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
451}
York Sun84baed22014-11-07 12:14:36 -0800452#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500453
454/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
York Sun03e664d2015-01-06 13:18:50 -0800455static void set_timing_cfg_3(const unsigned int ctrl_num,
456 fsl_ddr_cfg_regs_t *ddr,
457 const memctl_options_t *popts,
458 const common_timing_params_t *common_dimm,
459 unsigned int cas_latency,
460 unsigned int additive_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500461{
York Sun45064ad2012-08-17 08:22:40 +0000462 /* Extended precharge to activate interval (tRP) */
463 unsigned int ext_pretoact = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500464 /* Extended Activate to precharge interval (tRAS) */
465 unsigned int ext_acttopre = 0;
York Sun45064ad2012-08-17 08:22:40 +0000466 /* Extended activate to read/write interval (tRCD) */
467 unsigned int ext_acttorw = 0;
468 /* Extended refresh recovery time (tRFC) */
469 unsigned int ext_refrec;
470 /* Extended MCAS latency from READ cmd */
471 unsigned int ext_caslat = 0;
York Sund4263b82013-06-03 12:39:06 -0700472 /* Extended additive latency */
473 unsigned int ext_add_lat = 0;
York Sun45064ad2012-08-17 08:22:40 +0000474 /* Extended last data to precharge interval (tWR) */
475 unsigned int ext_wrrec = 0;
476 /* Control Adjust */
477 unsigned int cntl_adj = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500478
York Sun03e664d2015-01-06 13:18:50 -0800479 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
480 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
481 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
York Sun45064ad2012-08-17 08:22:40 +0000482 ext_caslat = (2 * cas_latency - 1) >> 4;
York Sund4263b82013-06-03 12:39:06 -0700483 ext_add_lat = additive_latency >> 4;
York Sun34e026f2014-03-27 17:54:47 -0700484#ifdef CONFIG_SYS_FSL_DDR4
York Sun03e664d2015-01-06 13:18:50 -0800485 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
York Sun34e026f2014-03-27 17:54:47 -0700486#else
York Sun03e664d2015-01-06 13:18:50 -0800487 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
York Sun45064ad2012-08-17 08:22:40 +0000488 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
York Sun34e026f2014-03-27 17:54:47 -0700489#endif
York Sun03e664d2015-01-06 13:18:50 -0800490 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530491 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
Dave Liuc360cea2009-03-14 12:48:30 +0800492
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500493 ddr->timing_cfg_3 = (0
York Sun45064ad2012-08-17 08:22:40 +0000494 | ((ext_pretoact & 0x1) << 28)
James Yangc45f5c02013-07-22 09:35:26 -0700495 | ((ext_acttopre & 0x3) << 24)
York Sun45064ad2012-08-17 08:22:40 +0000496 | ((ext_acttorw & 0x1) << 22)
York Sunc0c32af2018-01-29 09:44:35 -0800497 | ((ext_refrec & 0x3F) << 16)
York Sun45064ad2012-08-17 08:22:40 +0000498 | ((ext_caslat & 0x3) << 12)
York Sund4263b82013-06-03 12:39:06 -0700499 | ((ext_add_lat & 0x1) << 10)
York Sun45064ad2012-08-17 08:22:40 +0000500 | ((ext_wrrec & 0x1) << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500501 | ((cntl_adj & 0x7) << 0)
502 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400503 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500504}
505
506/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
York Sun03e664d2015-01-06 13:18:50 -0800507static void set_timing_cfg_1(const unsigned int ctrl_num,
508 fsl_ddr_cfg_regs_t *ddr,
509 const memctl_options_t *popts,
510 const common_timing_params_t *common_dimm,
511 unsigned int cas_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500512{
513 /* Precharge-to-activate interval (tRP) */
514 unsigned char pretoact_mclk;
515 /* Activate to precharge interval (tRAS) */
516 unsigned char acttopre_mclk;
517 /* Activate to read/write interval (tRCD) */
518 unsigned char acttorw_mclk;
519 /* CASLAT */
520 unsigned char caslat_ctrl;
521 /* Refresh recovery time (tRFC) ; trfc_low */
522 unsigned char refrec_ctrl;
523 /* Last data to precharge minimum interval (tWR) */
524 unsigned char wrrec_mclk;
525 /* Activate-to-activate interval (tRRD) */
526 unsigned char acttoact_mclk;
527 /* Last write data pair to read command issue interval (tWTR) */
528 unsigned char wrtord_mclk;
York Sun34e026f2014-03-27 17:54:47 -0700529#ifdef CONFIG_SYS_FSL_DDR4
530 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
531 static const u8 wrrec_table[] = {
532 10, 10, 10, 10, 10,
533 10, 10, 10, 10, 10,
534 12, 12, 14, 14, 16,
535 16, 18, 18, 20, 20,
536 24, 24, 24, 24};
537#else
York Sunf5b6fb72011-03-02 14:24:11 -0800538 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
539 static const u8 wrrec_table[] = {
540 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
York Sun34e026f2014-03-27 17:54:47 -0700541#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500542
York Sun03e664d2015-01-06 13:18:50 -0800543 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
544 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
545 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500546
547 /*
548 * Translate CAS Latency to a DDR controller field value:
549 *
550 * CAS Lat DDR I DDR II Ctrl
551 * Clocks SPD Bit SPD Bit Value
552 * ------- ------- ------- -----
553 * 1.0 0 0001
554 * 1.5 1 0010
555 * 2.0 2 2 0011
556 * 2.5 3 0100
557 * 3.0 4 3 0101
558 * 3.5 5 0110
559 * 4.0 4 0111
560 * 4.5 1000
561 * 5.0 5 1001
562 */
York Sun5614e712013-09-30 09:22:09 -0700563#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500564 caslat_ctrl = (cas_latency + 1) & 0x07;
York Sun5614e712013-09-30 09:22:09 -0700565#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500566 caslat_ctrl = 2 * cas_latency - 1;
567#else
Dave Liuc360cea2009-03-14 12:48:30 +0800568 /*
569 * if the CAS latency more than 8 cycle,
570 * we need set extend bit for it at
571 * TIMING_CFG_3[EXT_CASLAT]
572 */
York Sun66869f92015-03-19 09:30:26 -0700573 if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
York Sun34e026f2014-03-27 17:54:47 -0700574 caslat_ctrl = 2 * cas_latency - 1;
575 else
576 caslat_ctrl = (cas_latency - 1) << 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500577#endif
578
York Sun34e026f2014-03-27 17:54:47 -0700579#ifdef CONFIG_SYS_FSL_DDR4
York Sun03e664d2015-01-06 13:18:50 -0800580 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
581 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
582 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
583 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
York Sun349689b2014-04-01 14:20:49 -0700584 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
585 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
York Sun34e026f2014-03-27 17:54:47 -0700586 else
587 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
588#else
York Sun03e664d2015-01-06 13:18:50 -0800589 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
590 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
591 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
592 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
York Sun349689b2014-04-01 14:20:49 -0700593 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
594 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
York Sun45064ad2012-08-17 08:22:40 +0000595 else
596 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
York Sun34e026f2014-03-27 17:54:47 -0700597#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530598 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800599 wrrec_mclk += 2;
600
Dave Liuc360cea2009-03-14 12:48:30 +0800601 /*
602 * JEDEC has min requirement for tRRD
603 */
York Sun5614e712013-09-30 09:22:09 -0700604#if defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800605 if (acttoact_mclk < 4)
606 acttoact_mclk = 4;
607#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800608 /*
609 * JEDEC has some min requirements for tWTR
610 */
York Sun5614e712013-09-30 09:22:09 -0700611#if defined(CONFIG_SYS_FSL_DDR2)
Dave Liuc360cea2009-03-14 12:48:30 +0800612 if (wrtord_mclk < 2)
613 wrtord_mclk = 2;
York Sun5614e712013-09-30 09:22:09 -0700614#elif defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800615 if (wrtord_mclk < 4)
616 wrtord_mclk = 4;
617#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530618 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800619 wrtord_mclk += 2;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500620
621 ddr->timing_cfg_1 = (0
Dave Liu80ee3ce2008-11-21 16:31:22 +0800622 | ((pretoact_mclk & 0x0F) << 28)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500623 | ((acttopre_mclk & 0x0F) << 24)
Dave Liu80ee3ce2008-11-21 16:31:22 +0800624 | ((acttorw_mclk & 0xF) << 20)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500625 | ((caslat_ctrl & 0xF) << 16)
626 | ((refrec_ctrl & 0xF) << 12)
Dave Liu80ee3ce2008-11-21 16:31:22 +0800627 | ((wrrec_mclk & 0x0F) << 8)
York Sun57495e42012-10-08 07:44:22 +0000628 | ((acttoact_mclk & 0x0F) << 4)
629 | ((wrtord_mclk & 0x0F) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500630 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400631 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500632}
633
634/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
York Sun03e664d2015-01-06 13:18:50 -0800635static void set_timing_cfg_2(const unsigned int ctrl_num,
636 fsl_ddr_cfg_regs_t *ddr,
637 const memctl_options_t *popts,
638 const common_timing_params_t *common_dimm,
639 unsigned int cas_latency,
640 unsigned int additive_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500641{
642 /* Additive latency */
643 unsigned char add_lat_mclk;
644 /* CAS-to-preamble override */
645 unsigned short cpo;
646 /* Write latency */
647 unsigned char wr_lat;
648 /* Read to precharge (tRTP) */
649 unsigned char rd_to_pre;
650 /* Write command to write data strobe timing adjustment */
651 unsigned char wr_data_delay;
652 /* Minimum CKE pulse width (tCKE) */
653 unsigned char cke_pls;
654 /* Window for four activates (tFAW) */
655 unsigned short four_act;
York Sunbb578322014-08-21 16:13:22 -0700656#ifdef CONFIG_SYS_FSL_DDR3
York Sun03e664d2015-01-06 13:18:50 -0800657 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sunbb578322014-08-21 16:13:22 -0700658#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500659
660 /* FIXME add check that this must be less than acttorw_mclk */
661 add_lat_mclk = additive_latency;
662 cpo = popts->cpo_override;
663
York Sun5614e712013-09-30 09:22:09 -0700664#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500665 /*
666 * This is a lie. It should really be 1, but if it is
667 * set to 1, bits overlap into the old controller's
668 * otherwise unused ACSM field. If we leave it 0, then
669 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
670 */
671 wr_lat = 0;
York Sun5614e712013-09-30 09:22:09 -0700672#elif defined(CONFIG_SYS_FSL_DDR2)
Dave Liu6a819782009-03-14 12:48:19 +0800673 wr_lat = cas_latency - 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500674#else
York Sun03e664d2015-01-06 13:18:50 -0800675 wr_lat = compute_cas_write_latency(ctrl_num);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500676#endif
677
York Sun34e026f2014-03-27 17:54:47 -0700678#ifdef CONFIG_SYS_FSL_DDR4
York Sun03e664d2015-01-06 13:18:50 -0800679 rd_to_pre = picos_to_mclk(ctrl_num, 7500);
York Sun34e026f2014-03-27 17:54:47 -0700680#else
York Sun03e664d2015-01-06 13:18:50 -0800681 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
York Sun34e026f2014-03-27 17:54:47 -0700682#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800683 /*
684 * JEDEC has some min requirements for tRTP
685 */
York Sun5614e712013-09-30 09:22:09 -0700686#if defined(CONFIG_SYS_FSL_DDR2)
Dave Liuc360cea2009-03-14 12:48:30 +0800687 if (rd_to_pre < 2)
688 rd_to_pre = 2;
York Sun34e026f2014-03-27 17:54:47 -0700689#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800690 if (rd_to_pre < 4)
691 rd_to_pre = 4;
Dave Liu6a819782009-03-14 12:48:19 +0800692#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530693 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800694 rd_to_pre += 2; /* according to UM */
695
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500696 wr_data_delay = popts->write_data_delay;
York Sun34e026f2014-03-27 17:54:47 -0700697#ifdef CONFIG_SYS_FSL_DDR4
698 cpo = 0;
York Sun03e664d2015-01-06 13:18:50 -0800699 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
York Sunbb578322014-08-21 16:13:22 -0700700#elif defined(CONFIG_SYS_FSL_DDR3)
701 /*
702 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
703 * max(3nCK, 5.625ns) for DDR3-1066, 1333
704 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
705 */
York Sun03e664d2015-01-06 13:18:50 -0800706 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
707 (mclk_ps > 1245 ? 5625 : 5000)));
York Sun34e026f2014-03-27 17:54:47 -0700708#else
York Sunbb578322014-08-21 16:13:22 -0700709 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
York Sun34e026f2014-03-27 17:54:47 -0700710#endif
York Sun03e664d2015-01-06 13:18:50 -0800711 four_act = picos_to_mclk(ctrl_num,
712 popts->tfaw_window_four_activates_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500713
714 ddr->timing_cfg_2 = (0
Dave Liu22ff3d02008-11-21 16:31:29 +0800715 | ((add_lat_mclk & 0xf) << 28)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500716 | ((cpo & 0x1f) << 23)
Dave Liu22ff3d02008-11-21 16:31:29 +0800717 | ((wr_lat & 0xf) << 19)
York Sun89366912016-07-29 09:02:29 -0700718 | (((wr_lat & 0x10) >> 4) << 18)
Dave Liuc360cea2009-03-14 12:48:30 +0800719 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
720 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500721 | ((cke_pls & 0x7) << 6)
Dave Liu22ff3d02008-11-21 16:31:29 +0800722 | ((four_act & 0x3f) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500723 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400724 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500725}
726
york9490ff42010-07-02 22:25:55 +0000727/* DDR SDRAM Register Control Word */
York Sun564e9382018-01-29 10:24:08 -0800728static void set_ddr_sdram_rcw(const unsigned int ctrl_num,
729 fsl_ddr_cfg_regs_t *ddr,
730 const memctl_options_t *popts,
731 const common_timing_params_t *common_dimm)
york9490ff42010-07-02 22:25:55 +0000732{
York Sun564e9382018-01-29 10:24:08 -0800733 unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
734 unsigned int rc0a, rc0f;
735
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530736 if (common_dimm->all_dimms_registered &&
737 !common_dimm->all_dimms_unbuffered) {
York Sune1fd16b2011-01-10 12:03:00 +0000738 if (popts->rcw_override) {
739 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
740 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
York Sun426230a2018-01-29 09:44:33 -0800741 ddr->ddr_sdram_rcw_3 = popts->rcw_3;
York Sune1fd16b2011-01-10 12:03:00 +0000742 } else {
York Sun564e9382018-01-29 10:24:08 -0800743 rc0a = ddr_freq > 3200 ? 0x7 :
744 (ddr_freq > 2933 ? 0x6 :
745 (ddr_freq > 2666 ? 0x5 :
746 (ddr_freq > 2400 ? 0x4 :
747 (ddr_freq > 2133 ? 0x3 :
748 (ddr_freq > 1866 ? 0x2 :
749 (ddr_freq > 1600 ? 1 : 0))))));
750 rc0f = ddr_freq > 3200 ? 0x3 :
751 (ddr_freq > 2400 ? 0x2 :
752 (ddr_freq > 2133 ? 0x1 : 0));
York Sune1fd16b2011-01-10 12:03:00 +0000753 ddr->ddr_sdram_rcw_1 =
754 common_dimm->rcw[0] << 28 | \
755 common_dimm->rcw[1] << 24 | \
756 common_dimm->rcw[2] << 20 | \
757 common_dimm->rcw[3] << 16 | \
758 common_dimm->rcw[4] << 12 | \
759 common_dimm->rcw[5] << 8 | \
760 common_dimm->rcw[6] << 4 | \
761 common_dimm->rcw[7];
762 ddr->ddr_sdram_rcw_2 =
763 common_dimm->rcw[8] << 28 | \
764 common_dimm->rcw[9] << 24 | \
York Sun564e9382018-01-29 10:24:08 -0800765 rc0a << 20 | \
York Sune1fd16b2011-01-10 12:03:00 +0000766 common_dimm->rcw[11] << 16 | \
767 common_dimm->rcw[12] << 12 | \
768 common_dimm->rcw[13] << 8 | \
769 common_dimm->rcw[14] << 4 | \
York Sun564e9382018-01-29 10:24:08 -0800770 rc0f;
771 ddr->ddr_sdram_rcw_3 =
772 ((ddr_freq - 1260 + 19) / 20) << 8;
York Sune1fd16b2011-01-10 12:03:00 +0000773 }
York Sun426230a2018-01-29 09:44:33 -0800774 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
775 ddr->ddr_sdram_rcw_1);
776 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
777 ddr->ddr_sdram_rcw_2);
778 debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
779 ddr->ddr_sdram_rcw_3);
york9490ff42010-07-02 22:25:55 +0000780 }
781}
782
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500783/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
784static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
785 const memctl_options_t *popts,
786 const common_timing_params_t *common_dimm)
787{
788 unsigned int mem_en; /* DDR SDRAM interface logic enable */
789 unsigned int sren; /* Self refresh enable (during sleep) */
790 unsigned int ecc_en; /* ECC enable. */
791 unsigned int rd_en; /* Registered DIMM enable */
792 unsigned int sdram_type; /* Type of SDRAM */
793 unsigned int dyn_pwr; /* Dynamic power management mode */
794 unsigned int dbw; /* DRAM dta bus width */
Dave Liu22ff3d02008-11-21 16:31:29 +0800795 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500796 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530797 unsigned int threet_en; /* Enable 3T timing */
798 unsigned int twot_en; /* Enable 2T timing */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500799 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
800 unsigned int x32_en = 0; /* x32 enable */
801 unsigned int pchb8 = 0; /* precharge bit 8 enable */
802 unsigned int hse; /* Global half strength override */
York Sund28cb672014-09-05 13:52:41 +0800803 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500804 unsigned int mem_halt = 0; /* memory controller halt */
805 unsigned int bi = 0; /* Bypass initialization */
806
807 mem_en = 1;
808 sren = popts->self_refresh_in_sleep;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530809 if (common_dimm->all_dimms_ecc_capable) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500810 /* Allow setting of ECC only if all DIMMs are ECC. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530811 ecc_en = popts->ecc_mode;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500812 } else {
813 ecc_en = 0;
814 }
815
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530816 if (common_dimm->all_dimms_registered &&
817 !common_dimm->all_dimms_unbuffered) {
York Sune1fd16b2011-01-10 12:03:00 +0000818 rd_en = 1;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530819 twot_en = 0;
York Sune1fd16b2011-01-10 12:03:00 +0000820 } else {
821 rd_en = 0;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530822 twot_en = popts->twot_en;
York Sune1fd16b2011-01-10 12:03:00 +0000823 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500824
Tom Rini6e7df1d2023-01-10 11:19:45 -0500825 sdram_type = CFG_FSL_SDRAM_TYPE;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500826
827 dyn_pwr = popts->dynamic_power;
828 dbw = popts->data_bus_width;
Dave Liuc360cea2009-03-14 12:48:30 +0800829 /* 8-beat burst enable DDR-III case
830 * we must clear it when use the on-the-fly mode,
831 * must set it when use the 32-bits bus mode.
832 */
York Sun34e026f2014-03-27 17:54:47 -0700833 if ((sdram_type == SDRAM_TYPE_DDR3) ||
834 (sdram_type == SDRAM_TYPE_DDR4)) {
Dave Liuc360cea2009-03-14 12:48:30 +0800835 if (popts->burst_length == DDR_BL8)
836 eight_be = 1;
837 if (popts->burst_length == DDR_OTF)
838 eight_be = 0;
839 if (dbw == 0x1)
840 eight_be = 1;
841 }
842
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530843 threet_en = popts->threet_en;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500844 ba_intlv_ctl = popts->ba_intlv_ctl;
845 hse = popts->half_strength_driver_enable;
846
York Sund28cb672014-09-05 13:52:41 +0800847 /* set when ddr bus width < 64 */
848 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
849
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500850 ddr->ddr_sdram_cfg = (0
851 | ((mem_en & 0x1) << 31)
852 | ((sren & 0x1) << 30)
853 | ((ecc_en & 0x1) << 29)
854 | ((rd_en & 0x1) << 28)
855 | ((sdram_type & 0x7) << 24)
856 | ((dyn_pwr & 0x1) << 21)
857 | ((dbw & 0x3) << 19)
858 | ((eight_be & 0x1) << 18)
859 | ((ncap & 0x1) << 17)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530860 | ((threet_en & 0x1) << 16)
861 | ((twot_en & 0x1) << 15)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500862 | ((ba_intlv_ctl & 0x7F) << 8)
863 | ((x32_en & 0x1) << 5)
864 | ((pchb8 & 0x1) << 4)
865 | ((hse & 0x1) << 3)
York Sund28cb672014-09-05 13:52:41 +0800866 | ((acc_ecc_en & 0x1) << 2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500867 | ((mem_halt & 0x1) << 1)
868 | ((bi & 0x1) << 0)
869 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400870 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500871}
872
873/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
York Sun03e664d2015-01-06 13:18:50 -0800874static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
875 fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000876 const memctl_options_t *popts,
877 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500878{
879 unsigned int frc_sr = 0; /* Force self refresh */
880 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
York Suncae7c1b2011-08-26 11:32:40 -0700881 unsigned int odt_cfg = 0; /* ODT configuration */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500882 unsigned int num_pr; /* Number of posted refreshes */
York Sun57495e42012-10-08 07:44:22 +0000883 unsigned int slow = 0; /* DDR will be run less than 1250 */
York Sunb61e0612013-06-25 11:37:47 -0700884 unsigned int x4_en = 0; /* x4 DRAM enable */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500885 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
886 unsigned int ap_en; /* Address Parity Enable */
887 unsigned int d_init; /* DRAM data initialization */
888 unsigned int rcw_en = 0; /* Register Control Word Enable */
889 unsigned int md_en = 0; /* Mirrored DIMM Enable */
york5800e7a2010-07-02 22:25:53 +0000890 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
York Suncae7c1b2011-08-26 11:32:40 -0700891 int i;
York Sun34e026f2014-03-27 17:54:47 -0700892#ifndef CONFIG_SYS_FSL_DDR4
893 unsigned int dll_rst_dis = 1; /* DLL reset disable */
894 unsigned int dqs_cfg; /* DQS configuration */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500895
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530896 dqs_cfg = popts->dqs_config;
York Sun34e026f2014-03-27 17:54:47 -0700897#endif
York Suncae7c1b2011-08-26 11:32:40 -0700898 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
899 if (popts->cs_local_opts[i].odt_rd_cfg
900 || popts->cs_local_opts[i].odt_wr_cfg) {
901 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
902 break;
903 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500904 }
Joakim Tjernlunde368c202015-10-14 16:32:00 +0200905 sr_ie = popts->self_refresh_interrupt_en;
York Sunc0c32af2018-01-29 09:44:35 -0800906 num_pr = popts->package_3ds + 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500907
908 /*
909 * 8572 manual says
910 * {TIMING_CFG_1[PRETOACT]
911 * + [DDR_SDRAM_CFG_2[NUM_PR]
912 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
913 * << DDR_SDRAM_INTERVAL[REFINT]
914 */
York Sun34e026f2014-03-27 17:54:47 -0700915#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530916 obc_cfg = popts->otf_burst_chop_en;
Dave Liuc360cea2009-03-14 12:48:30 +0800917#else
918 obc_cfg = 0;
919#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500920
York Sun57495e42012-10-08 07:44:22 +0000921#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
York Sun03e664d2015-01-06 13:18:50 -0800922 slow = get_ddr_freq(ctrl_num) < 1249000000;
York Sun57495e42012-10-08 07:44:22 +0000923#endif
924
Shengzhou Liueb118802016-03-10 17:36:56 +0800925 if (popts->registered_dimm_en)
York Sune1fd16b2011-01-10 12:03:00 +0000926 rcw_en = 1;
Shengzhou Liueb118802016-03-10 17:36:56 +0800927
928 /* DDR4 can have address parity for UDIMM and discrete */
Tom Rini6e7df1d2023-01-10 11:19:45 -0500929 if ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
Shengzhou Liueb118802016-03-10 17:36:56 +0800930 (!popts->registered_dimm_en)) {
York Sune1fd16b2011-01-10 12:03:00 +0000931 ap_en = 0;
Shengzhou Liueb118802016-03-10 17:36:56 +0800932 } else {
933 ap_en = popts->ap_en;
York Sune1fd16b2011-01-10 12:03:00 +0000934 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500935
York Sunb61e0612013-06-25 11:37:47 -0700936 x4_en = popts->x4_en ? 1 : 0;
937
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500938#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
939 /* Use the DDR controller to auto initialize memory. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530940 d_init = popts->ecc_init_using_memctl;
Tom Rini829e9d22022-12-02 16:42:35 -0500941 ddr->ddr_data_init = 0xDEADBEEF;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500942 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
943#else
944 /* Memory will be initialized via DMA, or not at all. */
945 d_init = 0;
946#endif
947
York Sun34e026f2014-03-27 17:54:47 -0700948#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800949 md_en = popts->mirrored_dimm;
950#endif
york5800e7a2010-07-02 22:25:53 +0000951 qd_en = popts->quad_rank_present ? 1 : 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500952 ddr->ddr_sdram_cfg_2 = (0
953 | ((frc_sr & 0x1) << 31)
954 | ((sr_ie & 0x1) << 30)
York Sun34e026f2014-03-27 17:54:47 -0700955#ifndef CONFIG_SYS_FSL_DDR4
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500956 | ((dll_rst_dis & 0x1) << 29)
957 | ((dqs_cfg & 0x3) << 26)
York Sun34e026f2014-03-27 17:54:47 -0700958#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500959 | ((odt_cfg & 0x3) << 21)
960 | ((num_pr & 0xf) << 12)
York Sun57495e42012-10-08 07:44:22 +0000961 | ((slow & 1) << 11)
York Sunb61e0612013-06-25 11:37:47 -0700962 | (x4_en << 10)
york5800e7a2010-07-02 22:25:53 +0000963 | (qd_en << 9)
York Sune1fd16b2011-01-10 12:03:00 +0000964 | (unq_mrs_en << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500965 | ((obc_cfg & 0x1) << 6)
966 | ((ap_en & 0x1) << 5)
967 | ((d_init & 0x1) << 4)
968 | ((rcw_en & 0x1) << 2)
969 | ((md_en & 0x1) << 0)
970 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400971 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500972}
973
York Sun34e026f2014-03-27 17:54:47 -0700974#ifdef CONFIG_SYS_FSL_DDR4
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500975/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
York Sun03e664d2015-01-06 13:18:50 -0800976static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
977 fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000978 const memctl_options_t *popts,
Valentin Longchamp7e157b02013-10-18 11:47:20 +0200979 const common_timing_params_t *common_dimm,
York Sune1fd16b2011-01-10 12:03:00 +0000980 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500981{
982 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
983 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
York Sun34e026f2014-03-27 17:54:47 -0700984 int i;
985 unsigned int wr_crc = 0; /* Disable */
986 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
987 unsigned int srt = 0; /* self-refresh temerature, normal range */
York Sun03e664d2015-01-06 13:18:50 -0800988 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
York Sun34e026f2014-03-27 17:54:47 -0700989 unsigned int mpr = 0; /* serial */
990 unsigned int wc_lat;
York Sun03e664d2015-01-06 13:18:50 -0800991 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500992
York Sun34e026f2014-03-27 17:54:47 -0700993 if (popts->rtt_override)
994 rtt_wr = popts->rtt_wr_override_value;
995 else
996 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
997
998 if (common_dimm->extended_op_srt)
999 srt = common_dimm->extended_op_srt;
1000
1001 esdmode2 = (0
1002 | ((wr_crc & 0x1) << 12)
1003 | ((rtt_wr & 0x3) << 9)
1004 | ((srt & 0x3) << 6)
1005 | ((cwl & 0x7) << 3));
1006
1007 if (mclk_ps >= 1250)
1008 wc_lat = 0;
1009 else if (mclk_ps >= 833)
1010 wc_lat = 1;
1011 else
1012 wc_lat = 2;
1013
1014 esdmode3 = (0
1015 | ((mpr & 0x3) << 11)
1016 | ((wc_lat & 0x3) << 9));
1017
1018 ddr->ddr_sdram_mode_2 = (0
1019 | ((esdmode2 & 0xFFFF) << 16)
1020 | ((esdmode3 & 0xFFFF) << 0)
1021 );
1022 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1023
1024 if (unq_mrs_en) { /* unique mode registers are supported */
1025 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1026 if (popts->rtt_override)
1027 rtt_wr = popts->rtt_wr_override_value;
1028 else
1029 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1030
1031 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1032 esdmode2 |= (rtt_wr & 0x3) << 9;
1033 switch (i) {
1034 case 1:
1035 ddr->ddr_sdram_mode_4 = (0
1036 | ((esdmode2 & 0xFFFF) << 16)
1037 | ((esdmode3 & 0xFFFF) << 0)
1038 );
1039 break;
1040 case 2:
1041 ddr->ddr_sdram_mode_6 = (0
1042 | ((esdmode2 & 0xFFFF) << 16)
1043 | ((esdmode3 & 0xFFFF) << 0)
1044 );
1045 break;
1046 case 3:
1047 ddr->ddr_sdram_mode_8 = (0
1048 | ((esdmode2 & 0xFFFF) << 16)
1049 | ((esdmode3 & 0xFFFF) << 0)
1050 );
1051 break;
1052 }
1053 }
1054 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1055 ddr->ddr_sdram_mode_4);
1056 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1057 ddr->ddr_sdram_mode_6);
1058 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1059 ddr->ddr_sdram_mode_8);
1060 }
1061}
1062#elif defined(CONFIG_SYS_FSL_DDR3)
1063/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
York Sun03e664d2015-01-06 13:18:50 -08001064static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1065 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07001066 const memctl_options_t *popts,
1067 const common_timing_params_t *common_dimm,
1068 const unsigned int unq_mrs_en)
1069{
1070 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1071 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
Kumar Gala92966832011-01-20 01:53:15 -06001072 int i;
Dave Liu1aa3d082009-12-16 10:24:38 -06001073 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
Dave Liuc360cea2009-03-14 12:48:30 +08001074 unsigned int srt = 0; /* self-refresh temerature, normal range */
1075 unsigned int asr = 0; /* auto self-refresh disable */
York Sun03e664d2015-01-06 13:18:50 -08001076 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
Dave Liuc360cea2009-03-14 12:48:30 +08001077 unsigned int pasr = 0; /* partial array self refresh disable */
1078
Dave Liu1aa3d082009-12-16 10:24:38 -06001079 if (popts->rtt_override)
1080 rtt_wr = popts->rtt_wr_override_value;
York Sune1fd16b2011-01-10 12:03:00 +00001081 else
1082 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
Valentin Longchamp7e157b02013-10-18 11:47:20 +02001083
1084 if (common_dimm->extended_op_srt)
1085 srt = common_dimm->extended_op_srt;
1086
Dave Liuc360cea2009-03-14 12:48:30 +08001087 esdmode2 = (0
1088 | ((rtt_wr & 0x3) << 9)
1089 | ((srt & 0x1) << 7)
1090 | ((asr & 0x1) << 6)
1091 | ((cwl & 0x7) << 3)
1092 | ((pasr & 0x7) << 0));
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001093 ddr->ddr_sdram_mode_2 = (0
1094 | ((esdmode2 & 0xFFFF) << 16)
1095 | ((esdmode3 & 0xFFFF) << 0)
1096 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001097 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
York Sune1fd16b2011-01-10 12:03:00 +00001098
York Sune1fd16b2011-01-10 12:03:00 +00001099 if (unq_mrs_en) { /* unique mode registers are supported */
Kumar Galadea7f882011-11-09 10:05:10 -06001100 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sune1fd16b2011-01-10 12:03:00 +00001101 if (popts->rtt_override)
1102 rtt_wr = popts->rtt_wr_override_value;
1103 else
1104 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1105
1106 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1107 esdmode2 |= (rtt_wr & 0x3) << 9;
1108 switch (i) {
1109 case 1:
1110 ddr->ddr_sdram_mode_4 = (0
1111 | ((esdmode2 & 0xFFFF) << 16)
1112 | ((esdmode3 & 0xFFFF) << 0)
1113 );
1114 break;
1115 case 2:
1116 ddr->ddr_sdram_mode_6 = (0
1117 | ((esdmode2 & 0xFFFF) << 16)
1118 | ((esdmode3 & 0xFFFF) << 0)
1119 );
1120 break;
1121 case 3:
1122 ddr->ddr_sdram_mode_8 = (0
1123 | ((esdmode2 & 0xFFFF) << 16)
1124 | ((esdmode3 & 0xFFFF) << 0)
1125 );
1126 break;
1127 }
1128 }
1129 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1130 ddr->ddr_sdram_mode_4);
1131 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1132 ddr->ddr_sdram_mode_6);
1133 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1134 ddr->ddr_sdram_mode_8);
1135 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001136}
1137
York Sun34e026f2014-03-27 17:54:47 -07001138#else /* for DDR2 and DDR1 */
1139/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
York Sun03e664d2015-01-06 13:18:50 -08001140static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1141 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07001142 const memctl_options_t *popts,
1143 const common_timing_params_t *common_dimm,
1144 const unsigned int unq_mrs_en)
1145{
1146 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1147 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1148
1149 ddr->ddr_sdram_mode_2 = (0
1150 | ((esdmode2 & 0xFFFF) << 16)
1151 | ((esdmode3 & 0xFFFF) << 0)
1152 );
1153 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1154}
1155#endif
1156
1157#ifdef CONFIG_SYS_FSL_DDR4
1158/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1159static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1160 const memctl_options_t *popts,
1161 const common_timing_params_t *common_dimm,
1162 const unsigned int unq_mrs_en)
1163{
1164 int i;
1165 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1166 unsigned short esdmode5; /* Extended SDRAM mode 5 */
York Sun6b95be22015-03-19 09:30:27 -07001167 int rtt_park = 0;
York Sun8a514292015-11-04 10:03:19 -08001168 bool four_cs = false;
Shengzhou Liueb118802016-03-10 17:36:56 +08001169 const unsigned int mclk_ps = get_memory_clk_period_ps(0);
York Sun34e026f2014-03-27 17:54:47 -07001170
York Sun8a514292015-11-04 10:03:19 -08001171#if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1172 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1173 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1174 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1175 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1176 four_cs = true;
1177#endif
York Sun6b95be22015-03-19 09:30:27 -07001178 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1179 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
York Sun8a514292015-11-04 10:03:19 -08001180 rtt_park = four_cs ? 0 : 1;
York Sun6b95be22015-03-19 09:30:27 -07001181 } else {
1182 esdmode5 = 0x00000400; /* Data mask enabled */
1183 }
York Sun34e026f2014-03-27 17:54:47 -07001184
York Sun426230a2018-01-29 09:44:33 -08001185 /*
1186 * For DDR3, set C/A latency if address parity is enabled.
1187 * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
1188 * handled by register chip and RCW settings.
1189 */
1190 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
Tom Rini6e7df1d2023-01-10 11:19:45 -05001191 ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
York Sun426230a2018-01-29 09:44:33 -08001192 !popts->registered_dimm_en)) {
Shengzhou Liueb118802016-03-10 17:36:56 +08001193 if (mclk_ps >= 935) {
1194 /* for DDR4-1600/1866/2133 */
1195 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1196 } else if (mclk_ps >= 833) {
1197 /* for DDR4-2400 */
1198 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1199 } else {
1200 printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1201 }
1202 }
1203
York Sun34e026f2014-03-27 17:54:47 -07001204 ddr->ddr_sdram_mode_9 = (0
1205 | ((esdmode4 & 0xffff) << 16)
1206 | ((esdmode5 & 0xffff) << 0)
1207 );
York Sun66869f92015-03-19 09:30:26 -07001208
York Sun8a514292015-11-04 10:03:19 -08001209 /* Normally only the first enabled CS use 0x500, others use 0x400
1210 * But when four chip-selects are all enabled, all mode registers
1211 * need 0x500 to park.
1212 */
York Sun66869f92015-03-19 09:30:26 -07001213
York Sunc0c32af2018-01-29 09:44:35 -08001214 debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9);
York Sun34e026f2014-03-27 17:54:47 -07001215 if (unq_mrs_en) { /* unique mode registers are supported */
1216 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sun6b95be22015-03-19 09:30:27 -07001217 if (!rtt_park &&
1218 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1219 esdmode5 |= 0x00000500; /* RTT_PARK */
York Sun8a514292015-11-04 10:03:19 -08001220 rtt_park = four_cs ? 0 : 1;
York Sun6b95be22015-03-19 09:30:27 -07001221 } else {
1222 esdmode5 = 0x00000400;
1223 }
Shengzhou Liueb118802016-03-10 17:36:56 +08001224
York Sun426230a2018-01-29 09:44:33 -08001225 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
Tom Rini6e7df1d2023-01-10 11:19:45 -05001226 ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
York Sun426230a2018-01-29 09:44:33 -08001227 !popts->registered_dimm_en)) {
Shengzhou Liueb118802016-03-10 17:36:56 +08001228 if (mclk_ps >= 935) {
1229 /* for DDR4-1600/1866/2133 */
1230 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1231 } else if (mclk_ps >= 833) {
1232 /* for DDR4-2400 */
1233 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1234 } else {
1235 printf("parity: mclk_ps = %d not supported\n",
1236 mclk_ps);
1237 }
1238 }
1239
York Sun34e026f2014-03-27 17:54:47 -07001240 switch (i) {
1241 case 1:
1242 ddr->ddr_sdram_mode_11 = (0
1243 | ((esdmode4 & 0xFFFF) << 16)
1244 | ((esdmode5 & 0xFFFF) << 0)
1245 );
1246 break;
1247 case 2:
1248 ddr->ddr_sdram_mode_13 = (0
1249 | ((esdmode4 & 0xFFFF) << 16)
1250 | ((esdmode5 & 0xFFFF) << 0)
1251 );
1252 break;
1253 case 3:
1254 ddr->ddr_sdram_mode_15 = (0
1255 | ((esdmode4 & 0xFFFF) << 16)
1256 | ((esdmode5 & 0xFFFF) << 0)
1257 );
1258 break;
1259 }
1260 }
1261 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1262 ddr->ddr_sdram_mode_11);
1263 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1264 ddr->ddr_sdram_mode_13);
1265 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1266 ddr->ddr_sdram_mode_15);
1267 }
1268}
1269
1270/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
York Sun03e664d2015-01-06 13:18:50 -08001271static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1272 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07001273 const memctl_options_t *popts,
1274 const common_timing_params_t *common_dimm,
1275 const unsigned int unq_mrs_en)
1276{
1277 int i;
1278 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1279 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
York Sun03e664d2015-01-06 13:18:50 -08001280 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
York Sun34e026f2014-03-27 17:54:47 -07001281
1282 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1283
York Sun0fb71972015-11-04 10:03:18 -08001284 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1285 esdmode6 |= 1 << 6; /* Range 2 */
1286
York Sun34e026f2014-03-27 17:54:47 -07001287 ddr->ddr_sdram_mode_10 = (0
1288 | ((esdmode6 & 0xffff) << 16)
1289 | ((esdmode7 & 0xffff) << 0)
1290 );
York Sunc0c32af2018-01-29 09:44:35 -08001291 debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10);
York Sun34e026f2014-03-27 17:54:47 -07001292 if (unq_mrs_en) { /* unique mode registers are supported */
1293 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1294 switch (i) {
1295 case 1:
1296 ddr->ddr_sdram_mode_12 = (0
1297 | ((esdmode6 & 0xFFFF) << 16)
1298 | ((esdmode7 & 0xFFFF) << 0)
1299 );
1300 break;
1301 case 2:
1302 ddr->ddr_sdram_mode_14 = (0
1303 | ((esdmode6 & 0xFFFF) << 16)
1304 | ((esdmode7 & 0xFFFF) << 0)
1305 );
1306 break;
1307 case 3:
1308 ddr->ddr_sdram_mode_16 = (0
1309 | ((esdmode6 & 0xFFFF) << 16)
1310 | ((esdmode7 & 0xFFFF) << 0)
1311 );
1312 break;
1313 }
1314 }
1315 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1316 ddr->ddr_sdram_mode_12);
1317 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1318 ddr->ddr_sdram_mode_14);
1319 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1320 ddr->ddr_sdram_mode_16);
1321 }
1322}
1323
1324#endif
1325
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001326/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
York Sun03e664d2015-01-06 13:18:50 -08001327static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1328 fsl_ddr_cfg_regs_t *ddr,
1329 const memctl_options_t *popts,
1330 const common_timing_params_t *common_dimm)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001331{
1332 unsigned int refint; /* Refresh interval */
1333 unsigned int bstopre; /* Precharge interval */
1334
York Sun03e664d2015-01-06 13:18:50 -08001335 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001336
1337 bstopre = popts->bstopre;
1338
1339 /* refint field used 0x3FFF in earlier controllers */
1340 ddr->ddr_sdram_interval = (0
1341 | ((refint & 0xFFFF) << 16)
1342 | ((bstopre & 0x3FFF) << 0)
1343 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001344 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001345}
1346
York Sun34e026f2014-03-27 17:54:47 -07001347#ifdef CONFIG_SYS_FSL_DDR4
Dave Liuc360cea2009-03-14 12:48:30 +08001348/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
York Sun03e664d2015-01-06 13:18:50 -08001349static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1350 fsl_ddr_cfg_regs_t *ddr,
Dave Liuc360cea2009-03-14 12:48:30 +08001351 const memctl_options_t *popts,
1352 const common_timing_params_t *common_dimm,
1353 unsigned int cas_latency,
York Sune1fd16b2011-01-10 12:03:00 +00001354 unsigned int additive_latency,
1355 const unsigned int unq_mrs_en)
Dave Liuc360cea2009-03-14 12:48:30 +08001356{
York Sun34e026f2014-03-27 17:54:47 -07001357 int i;
1358 unsigned short esdmode; /* Extended SDRAM mode */
1359 unsigned short sdmode; /* SDRAM mode */
1360
1361 /* Mode Register - MR1 */
1362 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1363 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1364 unsigned int rtt;
1365 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1366 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1367 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1368 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1369 0=Disable (Test/Debug) */
1370
1371 /* Mode Register - MR0 */
1372 unsigned int wr = 0; /* Write Recovery */
1373 unsigned int dll_rst; /* DLL Reset */
1374 unsigned int mode; /* Normal=0 or Test=1 */
1375 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1376 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1377 unsigned int bt;
1378 unsigned int bl; /* BL: Burst Length */
1379
1380 unsigned int wr_mclk;
1381 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1382 static const u8 wr_table[] = {
1383 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1384 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1385 static const u8 cas_latency_table[] = {
1386 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1387 9, 9, 10, 10, 11, 11};
1388
1389 if (popts->rtt_override)
1390 rtt = popts->rtt_override_value;
1391 else
1392 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1393
1394 if (additive_latency == (cas_latency - 1))
1395 al = 1;
1396 if (additive_latency == (cas_latency - 2))
1397 al = 2;
1398
1399 if (popts->quad_rank_present)
1400 dic = 1; /* output driver impedance 240/7 ohm */
1401
1402 /*
1403 * The esdmode value will also be used for writing
1404 * MR1 during write leveling for DDR3, although the
1405 * bits specifically related to the write leveling
1406 * scheme will be handled automatically by the DDR
1407 * controller. so we set the wrlvl_en = 0 here.
1408 */
1409 esdmode = (0
1410 | ((qoff & 0x1) << 12)
1411 | ((tdqs_en & 0x1) << 11)
1412 | ((rtt & 0x7) << 8)
1413 | ((wrlvl_en & 0x1) << 7)
1414 | ((al & 0x3) << 3)
1415 | ((dic & 0x3) << 1) /* DIC field is split */
1416 | ((dll_en & 0x1) << 0)
1417 );
1418
1419 /*
1420 * DLL control for precharge PD
1421 * 0=slow exit DLL off (tXPDLL)
1422 * 1=fast exit DLL on (tXP)
1423 */
1424
York Sun03e664d2015-01-06 13:18:50 -08001425 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
York Sun34e026f2014-03-27 17:54:47 -07001426 if (wr_mclk <= 24) {
1427 wr = wr_table[wr_mclk - 10];
1428 } else {
1429 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1430 wr_mclk);
1431 }
1432
1433 dll_rst = 0; /* dll no reset */
1434 mode = 0; /* normal mode */
1435
1436 /* look up table to get the cas latency bits */
1437 if (cas_latency >= 9 && cas_latency <= 24)
1438 caslat = cas_latency_table[cas_latency - 9];
1439 else
1440 printf("Error: unsupported cas latency for mode register\n");
1441
1442 bt = 0; /* Nibble sequential */
1443
1444 switch (popts->burst_length) {
1445 case DDR_BL8:
1446 bl = 0;
1447 break;
1448 case DDR_OTF:
1449 bl = 1;
1450 break;
1451 case DDR_BC4:
1452 bl = 2;
1453 break;
1454 default:
1455 printf("Error: invalid burst length of %u specified. ",
1456 popts->burst_length);
1457 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1458 bl = 1;
1459 break;
1460 }
1461
1462 sdmode = (0
1463 | ((wr & 0x7) << 9)
1464 | ((dll_rst & 0x1) << 8)
1465 | ((mode & 0x1) << 7)
1466 | (((caslat >> 1) & 0x7) << 4)
1467 | ((bt & 0x1) << 3)
1468 | ((caslat & 1) << 2)
1469 | ((bl & 0x3) << 0)
1470 );
1471
1472 ddr->ddr_sdram_mode = (0
1473 | ((esdmode & 0xFFFF) << 16)
1474 | ((sdmode & 0xFFFF) << 0)
1475 );
1476
1477 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1478
1479 if (unq_mrs_en) { /* unique mode registers are supported */
1480 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1481 if (popts->rtt_override)
1482 rtt = popts->rtt_override_value;
1483 else
1484 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1485
1486 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1487 esdmode |= (rtt & 0x7) << 8;
1488 switch (i) {
1489 case 1:
1490 ddr->ddr_sdram_mode_3 = (0
1491 | ((esdmode & 0xFFFF) << 16)
1492 | ((sdmode & 0xFFFF) << 0)
1493 );
1494 break;
1495 case 2:
1496 ddr->ddr_sdram_mode_5 = (0
1497 | ((esdmode & 0xFFFF) << 16)
1498 | ((sdmode & 0xFFFF) << 0)
1499 );
1500 break;
1501 case 3:
1502 ddr->ddr_sdram_mode_7 = (0
1503 | ((esdmode & 0xFFFF) << 16)
1504 | ((sdmode & 0xFFFF) << 0)
1505 );
1506 break;
1507 }
1508 }
1509 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1510 ddr->ddr_sdram_mode_3);
1511 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1512 ddr->ddr_sdram_mode_5);
1513 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1514 ddr->ddr_sdram_mode_5);
1515 }
1516}
1517
1518#elif defined(CONFIG_SYS_FSL_DDR3)
1519/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
York Sun03e664d2015-01-06 13:18:50 -08001520static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1521 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07001522 const memctl_options_t *popts,
1523 const common_timing_params_t *common_dimm,
1524 unsigned int cas_latency,
1525 unsigned int additive_latency,
1526 const unsigned int unq_mrs_en)
1527{
1528 int i;
Dave Liuc360cea2009-03-14 12:48:30 +08001529 unsigned short esdmode; /* Extended SDRAM mode */
1530 unsigned short sdmode; /* SDRAM mode */
1531
1532 /* Mode Register - MR1 */
1533 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1534 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1535 unsigned int rtt;
1536 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1537 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
York Sune1fd16b2011-01-10 12:03:00 +00001538 unsigned int dic = 0; /* Output driver impedance, 40ohm */
Dave Liuc360cea2009-03-14 12:48:30 +08001539 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1540 1=Disable (Test/Debug) */
1541
1542 /* Mode Register - MR0 */
1543 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
York Sunfcea3062012-08-17 08:22:38 +00001544 unsigned int wr = 0; /* Write Recovery */
Dave Liuc360cea2009-03-14 12:48:30 +08001545 unsigned int dll_rst; /* DLL Reset */
1546 unsigned int mode; /* Normal=0 or Test=1 */
1547 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1548 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1549 unsigned int bt;
1550 unsigned int bl; /* BL: Burst Length */
1551
1552 unsigned int wr_mclk;
York Sunf5b6fb72011-03-02 14:24:11 -08001553 /*
1554 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1555 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1556 * for this table
1557 */
1558 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
Dave Liuc360cea2009-03-14 12:48:30 +08001559
Dave Liuc360cea2009-03-14 12:48:30 +08001560 if (popts->rtt_override)
1561 rtt = popts->rtt_override_value;
York Sune1fd16b2011-01-10 12:03:00 +00001562 else
1563 rtt = popts->cs_local_opts[0].odt_rtt_norm;
Dave Liuc360cea2009-03-14 12:48:30 +08001564
1565 if (additive_latency == (cas_latency - 1))
1566 al = 1;
1567 if (additive_latency == (cas_latency - 2))
1568 al = 2;
1569
York Sune1fd16b2011-01-10 12:03:00 +00001570 if (popts->quad_rank_present)
1571 dic = 1; /* output driver impedance 240/7 ohm */
1572
Dave Liuc360cea2009-03-14 12:48:30 +08001573 /*
1574 * The esdmode value will also be used for writing
1575 * MR1 during write leveling for DDR3, although the
1576 * bits specifically related to the write leveling
1577 * scheme will be handled automatically by the DDR
1578 * controller. so we set the wrlvl_en = 0 here.
1579 */
1580 esdmode = (0
1581 | ((qoff & 0x1) << 12)
1582 | ((tdqs_en & 0x1) << 11)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001583 | ((rtt & 0x4) << 7) /* rtt field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001584 | ((wrlvl_en & 0x1) << 7)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001585 | ((rtt & 0x2) << 5) /* rtt field is split */
1586 | ((dic & 0x2) << 4) /* DIC field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001587 | ((al & 0x3) << 3)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001588 | ((rtt & 0x1) << 2) /* rtt field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001589 | ((dic & 0x1) << 1) /* DIC field is split */
1590 | ((dll_en & 0x1) << 0)
1591 );
1592
1593 /*
1594 * DLL control for precharge PD
1595 * 0=slow exit DLL off (tXPDLL)
1596 * 1=fast exit DLL on (tXP)
1597 */
1598 dll_on = 1;
York Sunf5b6fb72011-03-02 14:24:11 -08001599
York Sun03e664d2015-01-06 13:18:50 -08001600 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
York Sunfcea3062012-08-17 08:22:38 +00001601 if (wr_mclk <= 16) {
1602 wr = wr_table[wr_mclk - 5];
1603 } else {
1604 printf("Error: unsupported write recovery for mode register "
1605 "wr_mclk = %d\n", wr_mclk);
1606 }
York Sunf5b6fb72011-03-02 14:24:11 -08001607
Dave Liuc360cea2009-03-14 12:48:30 +08001608 dll_rst = 0; /* dll no reset */
1609 mode = 0; /* normal mode */
1610
1611 /* look up table to get the cas latency bits */
York Sunfcea3062012-08-17 08:22:38 +00001612 if (cas_latency >= 5 && cas_latency <= 16) {
1613 unsigned char cas_latency_table[] = {
Dave Liuc360cea2009-03-14 12:48:30 +08001614 0x2, /* 5 clocks */
1615 0x4, /* 6 clocks */
1616 0x6, /* 7 clocks */
1617 0x8, /* 8 clocks */
1618 0xa, /* 9 clocks */
1619 0xc, /* 10 clocks */
York Sunfcea3062012-08-17 08:22:38 +00001620 0xe, /* 11 clocks */
1621 0x1, /* 12 clocks */
1622 0x3, /* 13 clocks */
1623 0x5, /* 14 clocks */
1624 0x7, /* 15 clocks */
1625 0x9, /* 16 clocks */
Dave Liuc360cea2009-03-14 12:48:30 +08001626 };
1627 caslat = cas_latency_table[cas_latency - 5];
York Sunfcea3062012-08-17 08:22:38 +00001628 } else {
1629 printf("Error: unsupported cas latency for mode register\n");
Dave Liuc360cea2009-03-14 12:48:30 +08001630 }
York Sunfcea3062012-08-17 08:22:38 +00001631
Dave Liuc360cea2009-03-14 12:48:30 +08001632 bt = 0; /* Nibble sequential */
1633
1634 switch (popts->burst_length) {
1635 case DDR_BL8:
1636 bl = 0;
1637 break;
1638 case DDR_OTF:
1639 bl = 1;
1640 break;
1641 case DDR_BC4:
1642 bl = 2;
1643 break;
1644 default:
1645 printf("Error: invalid burst length of %u specified. "
1646 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1647 popts->burst_length);
1648 bl = 1;
1649 break;
1650 }
1651
1652 sdmode = (0
1653 | ((dll_on & 0x1) << 12)
1654 | ((wr & 0x7) << 9)
1655 | ((dll_rst & 0x1) << 8)
1656 | ((mode & 0x1) << 7)
1657 | (((caslat >> 1) & 0x7) << 4)
1658 | ((bt & 0x1) << 3)
York Sunfcea3062012-08-17 08:22:38 +00001659 | ((caslat & 1) << 2)
Dave Liuc360cea2009-03-14 12:48:30 +08001660 | ((bl & 0x3) << 0)
1661 );
1662
1663 ddr->ddr_sdram_mode = (0
1664 | ((esdmode & 0xFFFF) << 16)
1665 | ((sdmode & 0xFFFF) << 0)
1666 );
1667
1668 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
York Sune1fd16b2011-01-10 12:03:00 +00001669
1670 if (unq_mrs_en) { /* unique mode registers are supported */
Kumar Galadea7f882011-11-09 10:05:10 -06001671 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sune1fd16b2011-01-10 12:03:00 +00001672 if (popts->rtt_override)
1673 rtt = popts->rtt_override_value;
1674 else
1675 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1676
1677 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1678 esdmode |= (0
1679 | ((rtt & 0x4) << 7) /* rtt field is split */
1680 | ((rtt & 0x2) << 5) /* rtt field is split */
1681 | ((rtt & 0x1) << 2) /* rtt field is split */
1682 );
1683 switch (i) {
1684 case 1:
1685 ddr->ddr_sdram_mode_3 = (0
1686 | ((esdmode & 0xFFFF) << 16)
1687 | ((sdmode & 0xFFFF) << 0)
1688 );
1689 break;
1690 case 2:
1691 ddr->ddr_sdram_mode_5 = (0
1692 | ((esdmode & 0xFFFF) << 16)
1693 | ((sdmode & 0xFFFF) << 0)
1694 );
1695 break;
1696 case 3:
1697 ddr->ddr_sdram_mode_7 = (0
1698 | ((esdmode & 0xFFFF) << 16)
1699 | ((sdmode & 0xFFFF) << 0)
1700 );
1701 break;
1702 }
1703 }
1704 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1705 ddr->ddr_sdram_mode_3);
1706 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1707 ddr->ddr_sdram_mode_5);
1708 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1709 ddr->ddr_sdram_mode_5);
1710 }
Dave Liuc360cea2009-03-14 12:48:30 +08001711}
1712
York Sun5614e712013-09-30 09:22:09 -07001713#else /* !CONFIG_SYS_FSL_DDR3 */
Dave Liuc360cea2009-03-14 12:48:30 +08001714
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001715/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
York Sun03e664d2015-01-06 13:18:50 -08001716static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1717 fsl_ddr_cfg_regs_t *ddr,
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001718 const memctl_options_t *popts,
1719 const common_timing_params_t *common_dimm,
1720 unsigned int cas_latency,
York Sune1fd16b2011-01-10 12:03:00 +00001721 unsigned int additive_latency,
1722 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001723{
1724 unsigned short esdmode; /* Extended SDRAM mode */
1725 unsigned short sdmode; /* SDRAM mode */
1726
1727 /*
1728 * FIXME: This ought to be pre-calculated in a
1729 * technology-specific routine,
1730 * e.g. compute_DDR2_mode_register(), and then the
1731 * sdmode and esdmode passed in as part of common_dimm.
1732 */
1733
1734 /* Extended Mode Register */
1735 unsigned int mrs = 0; /* Mode Register Set */
1736 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1737 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1738 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1739 unsigned int ocd = 0; /* 0x0=OCD not supported,
1740 0x7=OCD default state */
1741 unsigned int rtt;
1742 unsigned int al; /* Posted CAS# additive latency (AL) */
1743 unsigned int ods = 0; /* Output Drive Strength:
1744 0 = Full strength (18ohm)
1745 1 = Reduced strength (4ohm) */
1746 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1747 1=Disable (Test/Debug) */
1748
1749 /* Mode Register (MR) */
1750 unsigned int mr; /* Mode Register Definition */
1751 unsigned int pd; /* Power-Down Mode */
1752 unsigned int wr; /* Write Recovery */
1753 unsigned int dll_res; /* DLL Reset */
1754 unsigned int mode; /* Normal=0 or Test=1 */
Kumar Gala302e52e2008-09-05 14:40:29 -05001755 unsigned int caslat = 0;/* CAS# latency */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001756 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1757 unsigned int bt;
1758 unsigned int bl; /* BL: Burst Length */
1759
Priyanka Jain0dd38a32013-09-25 10:41:19 +05301760 dqs_en = !popts->dqs_config;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001761 rtt = fsl_ddr_get_rtt();
1762
1763 al = additive_latency;
1764
1765 esdmode = (0
1766 | ((mrs & 0x3) << 14)
1767 | ((outputs & 0x1) << 12)
1768 | ((rdqs_en & 0x1) << 11)
1769 | ((dqs_en & 0x1) << 10)
1770 | ((ocd & 0x7) << 7)
1771 | ((rtt & 0x2) << 5) /* rtt field is split */
1772 | ((al & 0x7) << 3)
1773 | ((rtt & 0x1) << 2) /* rtt field is split */
1774 | ((ods & 0x1) << 1)
1775 | ((dll_en & 0x1) << 0)
1776 );
1777
1778 mr = 0; /* FIXME: CHECKME */
1779
1780 /*
1781 * 0 = Fast Exit (Normal)
1782 * 1 = Slow Exit (Low Power)
1783 */
1784 pd = 0;
1785
York Sun5614e712013-09-30 09:22:09 -07001786#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001787 wr = 0; /* Historical */
York Sun5614e712013-09-30 09:22:09 -07001788#elif defined(CONFIG_SYS_FSL_DDR2)
York Sun03e664d2015-01-06 13:18:50 -08001789 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001790#endif
1791 dll_res = 0;
1792 mode = 0;
1793
York Sun5614e712013-09-30 09:22:09 -07001794#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001795 if (1 <= cas_latency && cas_latency <= 4) {
1796 unsigned char mode_caslat_table[4] = {
1797 0x5, /* 1.5 clocks */
1798 0x2, /* 2.0 clocks */
1799 0x6, /* 2.5 clocks */
1800 0x3 /* 3.0 clocks */
1801 };
Kumar Gala302e52e2008-09-05 14:40:29 -05001802 caslat = mode_caslat_table[cas_latency - 1];
1803 } else {
1804 printf("Warning: unknown cas_latency %d\n", cas_latency);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001805 }
York Sun5614e712013-09-30 09:22:09 -07001806#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001807 caslat = cas_latency;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001808#endif
1809 bt = 0;
1810
1811 switch (popts->burst_length) {
Dave Liuc360cea2009-03-14 12:48:30 +08001812 case DDR_BL4:
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001813 bl = 2;
1814 break;
Dave Liuc360cea2009-03-14 12:48:30 +08001815 case DDR_BL8:
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001816 bl = 3;
1817 break;
1818 default:
1819 printf("Error: invalid burst length of %u specified. "
1820 " Defaulting to 4 beats.\n",
1821 popts->burst_length);
1822 bl = 2;
1823 break;
1824 }
1825
1826 sdmode = (0
1827 | ((mr & 0x3) << 14)
1828 | ((pd & 0x1) << 12)
1829 | ((wr & 0x7) << 9)
1830 | ((dll_res & 0x1) << 8)
1831 | ((mode & 0x1) << 7)
1832 | ((caslat & 0x7) << 4)
1833 | ((bt & 0x1) << 3)
1834 | ((bl & 0x7) << 0)
1835 );
1836
1837 ddr->ddr_sdram_mode = (0
1838 | ((esdmode & 0xFFFF) << 16)
1839 | ((sdmode & 0xFFFF) << 0)
1840 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001841 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001842}
Dave Liuc360cea2009-03-14 12:48:30 +08001843#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001844
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001845/*
1846 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1847 * The old controller on the 8540/60 doesn't have this register.
1848 * Hope it's OK to set it (to 0) anyway.
1849 */
1850static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1851 const memctl_options_t *popts)
1852{
Tom Rini98898602021-05-14 21:34:21 -04001853 if (fsl_ddr_get_version(0) >= 0x40701)
Shengzhou Liud8e51632016-05-04 10:20:21 +08001854 /* clk_adjust in 5-bits on T-series and LS-series */
Tom Rini98898602021-05-14 21:34:21 -04001855 ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22;
1856 else
Shengzhou Liud8e51632016-05-04 10:20:21 +08001857 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
Tom Rini98898602021-05-14 21:34:21 -04001858 ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23;
Shengzhou Liud8e51632016-05-04 10:20:21 +08001859
york9490ff42010-07-02 22:25:55 +00001860 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500