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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Kumar Gala05c05a22008-08-26 15:01:30 -05002/*
3 * Copyright 2008 Freescale Semiconductor, Inc.
Kumar Gala05c05a22008-08-26 15:01:30 -05004 */
5
6#include <common.h>
York Sun5614e712013-09-30 09:22:09 -07007#include <fsl_ddr_sdram.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06008#include <log.h>
Simon Glasscd93d622020-05-10 11:40:13 -06009#include <asm/bitops.h>
Kumar Gala05c05a22008-08-26 15:01:30 -050010
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr.h>
Kumar Gala05c05a22008-08-26 15:01:30 -050012
13/*
14 * Calculate the Density of each Physical Rank.
15 * Returned size is in bytes.
16 *
17 * Study these table from Byte 31 of JEDEC SPD Spec.
18 *
19 * DDR I DDR II
20 * Bit Size Size
21 * --- ----- ------
22 * 7 high 512MB 512MB
23 * 6 256MB 256MB
24 * 5 128MB 128MB
25 * 4 64MB 16GB
26 * 3 32MB 8GB
27 * 2 16MB 4GB
28 * 1 2GB 2GB
29 * 0 low 1GB 1GB
30 *
31 * Reorder Table to be linear by stripping the bottom
32 * 2 or 5 bits off and shifting them up to the top.
33 */
34
Kumar Galae7563af2009-06-11 23:42:35 -050035static unsigned long long
Kumar Gala05c05a22008-08-26 15:01:30 -050036compute_ranksize(unsigned int mem_type, unsigned char row_dens)
37{
Kumar Galae7563af2009-06-11 23:42:35 -050038 unsigned long long bsize;
Kumar Gala05c05a22008-08-26 15:01:30 -050039
40 /* Bottom 2 bits up to the top. */
41 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
42 bsize <<= 24ULL;
Marek Vasutcd84b1f2011-10-21 14:17:19 +000043 debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
Kumar Gala05c05a22008-08-26 15:01:30 -050044
45 return bsize;
46}
47
48/*
49 * Convert a two-nibble BCD value into a cycle time.
50 * While the spec calls for nano-seconds, picos are returned.
51 *
52 * This implements the tables for bytes 9, 23 and 25 for both
53 * DDR I and II. No allowance for distinguishing the invalid
54 * fields absent for DDR I yet present in DDR II is made.
55 * (That is, cycle times of .25, .33, .66 and .75 ns are
56 * allowed for both DDR II and I.)
57 */
58static unsigned int
59convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
60{
61 /* Table look up the lower nibble, allow DDR I & II. */
62 unsigned int tenths_ps[16] = {
63 0,
64 100,
65 200,
66 300,
67 400,
68 500,
69 600,
70 700,
71 800,
72 900,
73 250, /* This and the next 3 entries valid ... */
74 330, /* ... only for tCK calculations. */
75 660,
76 750,
77 0, /* undefined */
78 0 /* undefined */
79 };
80
81 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
82 unsigned int tenth_ns = spd_val & 0x0F;
83 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
84
85 return ps;
86}
87
88static unsigned int
89convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
90{
91 unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
92 unsigned int hundredth_ns = spd_val & 0x0F;
93 unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
94
95 return ps;
96}
97
98static unsigned int byte40_table_ps[8] = {
99 0,
100 250,
101 330,
102 500,
103 660,
104 750,
105 0, /* supposed to be RFC, but not sure what that means */
106 0 /* Undefined */
107};
108
109static unsigned int
110compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
111{
Masahiro Yamadaa4ca3792016-09-06 22:17:39 +0900112 return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000
Kumar Gala05c05a22008-08-26 15:01:30 -0500113 + byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
Kumar Gala05c05a22008-08-26 15:01:30 -0500114}
115
116static unsigned int
117compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
118{
Masahiro Yamadaa4ca3792016-09-06 22:17:39 +0900119 return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
Kumar Gala05c05a22008-08-26 15:01:30 -0500120}
121
122/*
123 * tCKmax from DDR I SPD Byte 43
124 *
125 * Bits 7:2 == whole ns
126 * Bits 1:0 == quarter ns
127 * 00 == 0.00 ns
128 * 01 == 0.25 ns
129 * 10 == 0.50 ns
130 * 11 == 0.75 ns
131 *
132 * Returns picoseconds.
133 */
134static unsigned int
135compute_tckmax_from_spd_ps(unsigned int byte43)
136{
137 return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
138}
139
140/*
141 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
142 * Table from SPD Spec, Byte 12, converted to picoseconds and
143 * filled in with "default" normal values.
144 */
145static unsigned int
146determine_refresh_rate_ps(const unsigned int spd_refresh)
147{
148 unsigned int refresh_time_ps[8] = {
149 15625000, /* 0 Normal 1.00x */
150 3900000, /* 1 Reduced .25x */
151 7800000, /* 2 Extended .50x */
152 31300000, /* 3 Extended 2.00x */
153 62500000, /* 4 Extended 4.00x */
154 125000000, /* 5 Extended 8.00x */
155 15625000, /* 6 Normal 1.00x filler */
156 15625000, /* 7 Normal 1.00x filler */
157 };
158
159 return refresh_time_ps[spd_refresh & 0x7];
160}
161
162/*
163 * The purpose of this function is to compute a suitable
164 * CAS latency given the DRAM clock period. The SPD only
165 * defines at most 3 CAS latencies. Typically the slower in
166 * frequency the DIMM runs at, the shorter its CAS latency can be.
167 * If the DIMM is operating at a sufficiently low frequency,
168 * it may be able to run at a CAS latency shorter than the
169 * shortest SPD-defined CAS latency.
170 *
171 * If a CAS latency is not found, 0 is returned.
172 *
173 * Do this by finding in the standard speed bin table the longest
174 * tCKmin that doesn't exceed the value of mclk_ps (tCK).
175 *
176 * An assumption made is that the SDRAM device allows the
177 * CL to be programmed for a value that is lower than those
178 * advertised by the SPD. This is not always the case,
179 * as those modes not defined in the SPD are optional.
180 *
181 * CAS latency de-rating based upon values JEDEC Standard No. 79-E
182 * Table 11.
183 *
184 * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
185 */
186 /* CL2.0 CL2.5 CL3.0 */
187unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
188
189unsigned int
190compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
191{
192 const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
193 unsigned int lowest_tCKmin_found = 0;
194 unsigned int lowest_tCKmin_CL = 0;
195 unsigned int i;
196
197 debug("mclk_ps = %u\n", mclk_ps);
198
199 for (i = 0; i < num_speed_bins; i++) {
200 unsigned int x = ddr1_speed_bins[i];
201 debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
202 i, x, lowest_tCKmin_found);
203 if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
204 lowest_tCKmin_found = x;
205 lowest_tCKmin_CL = i + 1;
206 }
207 }
208
209 debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
210
211 return lowest_tCKmin_CL;
212}
213
214/*
215 * ddr_compute_dimm_parameters for DDR1 SPD
216 *
217 * Compute DIMM parameters based upon the SPD information in spd.
218 * Writes the results to the dimm_params_t structure pointed by pdimm.
219 *
220 * FIXME: use #define for the retvals
221 */
York Sun03e664d2015-01-06 13:18:50 -0800222unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
223 const ddr1_spd_eeprom_t *spd,
224 dimm_params_t *pdimm,
225 unsigned int dimm_number)
Kumar Gala05c05a22008-08-26 15:01:30 -0500226{
227 unsigned int retval;
228
229 if (spd->mem_type) {
230 if (spd->mem_type != SPD_MEMTYPE_DDR) {
231 printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
232 return 1;
233 }
234 } else {
235 memset(pdimm, 0, sizeof(dimm_params_t));
236 return 1;
237 }
238
239 retval = ddr1_spd_check(spd);
240 if (retval) {
241 printf("DIMM %u: failed checksum\n", dimm_number);
242 return 2;
243 }
244
245 /*
246 * The part name in ASCII in the SPD EEPROM is not null terminated.
247 * Guarantee null termination here by presetting all bytes to 0
248 * and copying the part name in ASCII from the SPD onto it
249 */
250 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
251 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
252
253 /* DIMM organization parameters */
254 pdimm->n_ranks = spd->nrows;
255 pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
256 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
257 pdimm->data_width = spd->dataw_lsb;
258 pdimm->primary_sdram_width = spd->primw;
259 pdimm->ec_sdram_width = spd->ecw;
260
261 /*
262 * FIXME: Need to determine registered_dimm status.
263 * 1 == register buffered
264 * 0 == unbuffered
265 */
266 pdimm->registered_dimm = 0; /* unbuffered */
267
268 /* SDRAM device parameters */
269 pdimm->n_row_addr = spd->nrow_addr;
270 pdimm->n_col_addr = spd->ncol_addr;
271 pdimm->n_banks_per_sdram_device = spd->nbanks;
272 pdimm->edc_config = spd->config;
273 pdimm->burst_lengths_bitmask = spd->burstl;
Kumar Gala05c05a22008-08-26 15:01:30 -0500274
275 /*
276 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
277 * The SPD clk_cycle field (tCKmin) is measured in tenths of
278 * nanoseconds and represented as BCD.
279 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530280 pdimm->tckmin_x_ps
Kumar Gala05c05a22008-08-26 15:01:30 -0500281 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530282 pdimm->tckmin_x_minus_1_ps
Kumar Gala05c05a22008-08-26 15:01:30 -0500283 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530284 pdimm->tckmin_x_minus_2_ps
Kumar Gala05c05a22008-08-26 15:01:30 -0500285 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
286
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530287 pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
Kumar Gala05c05a22008-08-26 15:01:30 -0500288
289 /*
290 * Compute CAS latencies defined by SPD
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530291 * The SPD caslat_x should have at least 1 and at most 3 bits set.
Kumar Gala05c05a22008-08-26 15:01:30 -0500292 *
293 * If cas_lat after masking is 0, the __ilog2 function returns
294 * 255 into the variable. This behavior is abused once.
295 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530296 pdimm->caslat_x = __ilog2(spd->cas_lat);
297 pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
298 & ~(1 << pdimm->caslat_x));
299 pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
300 & ~(1 << pdimm->caslat_x)
301 & ~(1 << pdimm->caslat_x_minus_1));
Kumar Gala05c05a22008-08-26 15:01:30 -0500302
303 /* Compute CAS latencies below that defined by SPD */
York Sun03e664d2015-01-06 13:18:50 -0800304 pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
305 get_memory_clk_period_ps(ctrl_num));
Kumar Gala05c05a22008-08-26 15:01:30 -0500306
307 /* Compute timing parameters */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530308 pdimm->trcd_ps = spd->trcd * 250;
309 pdimm->trp_ps = spd->trp * 250;
310 pdimm->tras_ps = spd->tras * 1000;
Kumar Gala05c05a22008-08-26 15:01:30 -0500311
York Sun03e664d2015-01-06 13:18:50 -0800312 pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
313 pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530314 pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
Kumar Gala05c05a22008-08-26 15:01:30 -0500315
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530316 pdimm->trrd_ps = spd->trrd * 250;
317 pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
Kumar Gala05c05a22008-08-26 15:01:30 -0500318
319 pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
320
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530321 pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
322 pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
323 pdimm->tds_ps
Kumar Gala05c05a22008-08-26 15:01:30 -0500324 = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530325 pdimm->tdh_ps
Kumar Gala05c05a22008-08-26 15:01:30 -0500326 = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
327
York Sun03e664d2015-01-06 13:18:50 -0800328 pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530329 pdimm->tdqsq_max_ps = spd->tdqsq * 10;
330 pdimm->tqhs_ps = spd->tqhs * 10;
Kumar Gala05c05a22008-08-26 15:01:30 -0500331
332 return 0;
333}