Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2008 Freescale Semiconductor, Inc. |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 7 | #include <fsl_ddr_sdram.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 9 | #include <asm/bitops.h> |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 10 | |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 11 | #include <fsl_ddr.h> |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 12 | /* |
| 13 | * Calculate the Density of each Physical Rank. |
| 14 | * Returned size is in bytes. |
| 15 | * |
| 16 | * Study these table from Byte 31 of JEDEC SPD Spec. |
| 17 | * |
| 18 | * DDR I DDR II |
| 19 | * Bit Size Size |
| 20 | * --- ----- ------ |
| 21 | * 7 high 512MB 512MB |
| 22 | * 6 256MB 256MB |
| 23 | * 5 128MB 128MB |
| 24 | * 4 64MB 16GB |
| 25 | * 3 32MB 8GB |
| 26 | * 2 16MB 4GB |
| 27 | * 1 2GB 2GB |
| 28 | * 0 low 1GB 1GB |
| 29 | * |
| 30 | * Reorder Table to be linear by stripping the bottom |
| 31 | * 2 or 5 bits off and shifting them up to the top. |
| 32 | * |
| 33 | */ |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 34 | static unsigned long long |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 35 | compute_ranksize(unsigned int mem_type, unsigned char row_dens) |
| 36 | { |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 37 | unsigned long long bsize; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 38 | |
| 39 | /* Bottom 5 bits up to the top. */ |
| 40 | bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)); |
| 41 | bsize <<= 27ULL; |
Marek Vasut | cd84b1f | 2011-10-21 14:17:19 +0000 | [diff] [blame] | 42 | debug("DDR: DDR II rank density = 0x%16llx\n", bsize); |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 43 | |
| 44 | return bsize; |
| 45 | } |
| 46 | |
| 47 | /* |
| 48 | * Convert a two-nibble BCD value into a cycle time. |
| 49 | * While the spec calls for nano-seconds, picos are returned. |
| 50 | * |
| 51 | * This implements the tables for bytes 9, 23 and 25 for both |
| 52 | * DDR I and II. No allowance for distinguishing the invalid |
| 53 | * fields absent for DDR I yet present in DDR II is made. |
| 54 | * (That is, cycle times of .25, .33, .66 and .75 ns are |
| 55 | * allowed for both DDR II and I.) |
| 56 | */ |
| 57 | static unsigned int |
| 58 | convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) |
| 59 | { |
| 60 | /* Table look up the lower nibble, allow DDR I & II. */ |
| 61 | unsigned int tenths_ps[16] = { |
| 62 | 0, |
| 63 | 100, |
| 64 | 200, |
| 65 | 300, |
| 66 | 400, |
| 67 | 500, |
| 68 | 600, |
| 69 | 700, |
| 70 | 800, |
| 71 | 900, |
| 72 | 250, /* This and the next 3 entries valid ... */ |
| 73 | 330, /* ... only for tCK calculations. */ |
| 74 | 660, |
| 75 | 750, |
| 76 | 0, /* undefined */ |
| 77 | 0 /* undefined */ |
| 78 | }; |
| 79 | |
| 80 | unsigned int whole_ns = (spd_val & 0xF0) >> 4; |
| 81 | unsigned int tenth_ns = spd_val & 0x0F; |
| 82 | unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; |
| 83 | |
| 84 | return ps; |
| 85 | } |
| 86 | |
| 87 | static unsigned int |
| 88 | convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) |
| 89 | { |
| 90 | unsigned int tenth_ns = (spd_val & 0xF0) >> 4; |
| 91 | unsigned int hundredth_ns = spd_val & 0x0F; |
| 92 | unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; |
| 93 | |
| 94 | return ps; |
| 95 | } |
| 96 | |
| 97 | static unsigned int byte40_table_ps[8] = { |
| 98 | 0, |
| 99 | 250, |
| 100 | 330, |
| 101 | 500, |
| 102 | 660, |
| 103 | 750, |
| 104 | 0, /* supposed to be RFC, but not sure what that means */ |
| 105 | 0 /* Undefined */ |
| 106 | }; |
| 107 | |
| 108 | static unsigned int |
| 109 | compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) |
| 110 | { |
Masahiro Yamada | a4ca379 | 2016-09-06 22:17:39 +0900 | [diff] [blame] | 111 | return (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 112 | + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | static unsigned int |
| 116 | compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) |
| 117 | { |
Masahiro Yamada | a4ca379 | 2016-09-06 22:17:39 +0900 | [diff] [blame] | 118 | return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | /* |
| 122 | * Determine Refresh Rate. Ignore self refresh bit on DDR I. |
| 123 | * Table from SPD Spec, Byte 12, converted to picoseconds and |
| 124 | * filled in with "default" normal values. |
| 125 | */ |
| 126 | static unsigned int |
| 127 | determine_refresh_rate_ps(const unsigned int spd_refresh) |
| 128 | { |
| 129 | unsigned int refresh_time_ps[8] = { |
| 130 | 15625000, /* 0 Normal 1.00x */ |
| 131 | 3900000, /* 1 Reduced .25x */ |
| 132 | 7800000, /* 2 Extended .50x */ |
| 133 | 31300000, /* 3 Extended 2.00x */ |
| 134 | 62500000, /* 4 Extended 4.00x */ |
| 135 | 125000000, /* 5 Extended 8.00x */ |
| 136 | 15625000, /* 6 Normal 1.00x filler */ |
| 137 | 15625000, /* 7 Normal 1.00x filler */ |
| 138 | }; |
| 139 | |
| 140 | return refresh_time_ps[spd_refresh & 0x7]; |
| 141 | } |
| 142 | |
| 143 | /* |
| 144 | * The purpose of this function is to compute a suitable |
| 145 | * CAS latency given the DRAM clock period. The SPD only |
| 146 | * defines at most 3 CAS latencies. Typically the slower in |
| 147 | * frequency the DIMM runs at, the shorter its CAS latency can. |
| 148 | * be. If the DIMM is operating at a sufficiently low frequency, |
| 149 | * it may be able to run at a CAS latency shorter than the |
| 150 | * shortest SPD-defined CAS latency. |
| 151 | * |
| 152 | * If a CAS latency is not found, 0 is returned. |
| 153 | * |
| 154 | * Do this by finding in the standard speed bin table the longest |
| 155 | * tCKmin that doesn't exceed the value of mclk_ps (tCK). |
| 156 | * |
| 157 | * An assumption made is that the SDRAM device allows the |
| 158 | * CL to be programmed for a value that is lower than those |
| 159 | * advertised by the SPD. This is not always the case, |
| 160 | * as those modes not defined in the SPD are optional. |
| 161 | * |
| 162 | * CAS latency de-rating based upon values JEDEC Standard No. 79-2C |
| 163 | * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS, |
| 164 | * and tRC for corresponding bin" |
| 165 | * |
| 166 | * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 |
| 167 | * Not certain if any good value exists for CL=2 |
| 168 | */ |
York Sun | bcb6c2b | 2010-05-07 09:12:01 -0500 | [diff] [blame] | 169 | /* CL2 CL3 CL4 CL5 CL6 CL7*/ |
| 170 | unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 171 | |
| 172 | unsigned int |
| 173 | compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) |
| 174 | { |
| 175 | const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins); |
| 176 | unsigned int lowest_tCKmin_found = 0; |
| 177 | unsigned int lowest_tCKmin_CL = 0; |
| 178 | unsigned int i; |
| 179 | |
| 180 | debug("mclk_ps = %u\n", mclk_ps); |
| 181 | |
| 182 | for (i = 0; i < num_speed_bins; i++) { |
| 183 | unsigned int x = ddr2_speed_bins[i]; |
| 184 | debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", |
| 185 | i, x, lowest_tCKmin_found); |
| 186 | if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) { |
| 187 | lowest_tCKmin_found = x; |
| 188 | lowest_tCKmin_CL = i + 2; |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); |
| 193 | |
| 194 | return lowest_tCKmin_CL; |
| 195 | } |
| 196 | |
| 197 | /* |
| 198 | * ddr_compute_dimm_parameters for DDR2 SPD |
| 199 | * |
| 200 | * Compute DIMM parameters based upon the SPD information in spd. |
| 201 | * Writes the results to the dimm_params_t structure pointed by pdimm. |
| 202 | * |
| 203 | * FIXME: use #define for the retvals |
| 204 | */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 205 | unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, |
| 206 | const ddr2_spd_eeprom_t *spd, |
| 207 | dimm_params_t *pdimm, |
| 208 | unsigned int dimm_number) |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 209 | { |
| 210 | unsigned int retval; |
| 211 | |
| 212 | if (spd->mem_type) { |
| 213 | if (spd->mem_type != SPD_MEMTYPE_DDR2) { |
| 214 | printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number); |
| 215 | return 1; |
| 216 | } |
| 217 | } else { |
| 218 | memset(pdimm, 0, sizeof(dimm_params_t)); |
| 219 | return 1; |
| 220 | } |
| 221 | |
| 222 | retval = ddr2_spd_check(spd); |
| 223 | if (retval) { |
| 224 | printf("DIMM %u: failed checksum\n", dimm_number); |
| 225 | return 2; |
| 226 | } |
| 227 | |
| 228 | /* |
| 229 | * The part name in ASCII in the SPD EEPROM is not null terminated. |
| 230 | * Guarantee null termination here by presetting all bytes to 0 |
| 231 | * and copying the part name in ASCII from the SPD onto it |
| 232 | */ |
| 233 | memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); |
| 234 | memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); |
| 235 | |
| 236 | /* DIMM organization parameters */ |
| 237 | pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1; |
| 238 | pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens); |
| 239 | pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; |
| 240 | pdimm->data_width = spd->dataw; |
| 241 | pdimm->primary_sdram_width = spd->primw; |
| 242 | pdimm->ec_sdram_width = spd->ecw; |
| 243 | |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 244 | /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 245 | switch (spd->dimm_type) { |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 246 | case DDR2_SPD_DIMMTYPE_RDIMM: |
| 247 | case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: |
| 248 | case DDR2_SPD_DIMMTYPE_MINI_RDIMM: |
| 249 | /* Registered/buffered DIMMs */ |
| 250 | pdimm->registered_dimm = 1; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 251 | break; |
| 252 | |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 253 | case DDR2_SPD_DIMMTYPE_UDIMM: |
| 254 | case DDR2_SPD_DIMMTYPE_SO_DIMM: |
| 255 | case DDR2_SPD_DIMMTYPE_MICRO_DIMM: |
| 256 | case DDR2_SPD_DIMMTYPE_MINI_UDIMM: |
| 257 | /* Unbuffered DIMMs */ |
| 258 | pdimm->registered_dimm = 0; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 259 | break; |
| 260 | |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 261 | case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 262 | default: |
| 263 | printf("unknown dimm_type 0x%02X\n", spd->dimm_type); |
| 264 | return 1; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | /* SDRAM device parameters */ |
| 268 | pdimm->n_row_addr = spd->nrow_addr; |
| 269 | pdimm->n_col_addr = spd->ncol_addr; |
| 270 | pdimm->n_banks_per_sdram_device = spd->nbanks; |
| 271 | pdimm->edc_config = spd->config; |
| 272 | pdimm->burst_lengths_bitmask = spd->burstl; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 273 | |
| 274 | /* |
| 275 | * Calculate the Maximum Data Rate based on the Minimum Cycle time. |
| 276 | * The SPD clk_cycle field (tCKmin) is measured in tenths of |
| 277 | * nanoseconds and represented as BCD. |
| 278 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 279 | pdimm->tckmin_x_ps |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 280 | = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 281 | pdimm->tckmin_x_minus_1_ps |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 282 | = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 283 | pdimm->tckmin_x_minus_2_ps |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 284 | = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); |
| 285 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 286 | pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 287 | |
| 288 | /* |
| 289 | * Compute CAS latencies defined by SPD |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 290 | * The SPD caslat_x should have at least 1 and at most 3 bits set. |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 291 | * |
| 292 | * If cas_lat after masking is 0, the __ilog2 function returns |
| 293 | * 255 into the variable. This behavior is abused once. |
| 294 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 295 | pdimm->caslat_x = __ilog2(spd->cas_lat); |
| 296 | pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat |
| 297 | & ~(1 << pdimm->caslat_x)); |
| 298 | pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat |
| 299 | & ~(1 << pdimm->caslat_x) |
| 300 | & ~(1 << pdimm->caslat_x_minus_1)); |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 301 | |
| 302 | /* Compute CAS latencies below that defined by SPD */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 303 | pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency( |
| 304 | get_memory_clk_period_ps(ctrl_num)); |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 305 | |
| 306 | /* Compute timing parameters */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 307 | pdimm->trcd_ps = spd->trcd * 250; |
| 308 | pdimm->trp_ps = spd->trp * 250; |
| 309 | pdimm->tras_ps = spd->tras * 1000; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 310 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 311 | pdimm->twr_ps = spd->twr * 250; |
| 312 | pdimm->twtr_ps = spd->twtr * 250; |
| 313 | pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 314 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 315 | pdimm->trrd_ps = spd->trrd * 250; |
| 316 | pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 317 | |
| 318 | pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); |
| 319 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 320 | pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); |
| 321 | pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); |
| 322 | pdimm->tds_ps |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 323 | = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 324 | pdimm->tdh_ps |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 325 | = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); |
| 326 | |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 327 | pdimm->trtp_ps = spd->trtp * 250; |
| 328 | pdimm->tdqsq_max_ps = spd->tdqsq * 10; |
| 329 | pdimm->tqhs_ps = spd->tqhs * 10; |
Kumar Gala | 233fdd5 | 2008-08-26 15:01:32 -0500 | [diff] [blame] | 330 | |
| 331 | return 0; |
| 332 | } |