Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2 | /* |
York Sun | 73b5396 | 2012-08-17 08:22:37 +0000 | [diff] [blame] | 3 | * Copyright 2008-2012 Freescale Semiconductor, Inc. |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 4 | * Dave Liu <daveliu@freescale.com> |
| 5 | * |
| 6 | * calculate the organization and timing parameter |
| 7 | * from ddr3 spd, please refer to the spec |
| 8 | * JEDEC standard No.21-C 4_01_02_11R18.pdf |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 12 | #include <fsl_ddr_sdram.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 13 | #include <log.h> |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 14 | |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 15 | #include <fsl_ddr.h> |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * Calculate the Density of each Physical Rank. |
| 19 | * Returned size is in bytes. |
| 20 | * |
| 21 | * each rank size = |
| 22 | * sdram capacity(bit) / 8 * primary bus width / sdram width |
| 23 | * |
| 24 | * where: sdram capacity = spd byte4[3:0] |
| 25 | * primary bus width = spd byte8[2:0] |
| 26 | * sdram width = spd byte7[2:0] |
| 27 | * |
| 28 | * SPD byte4 - sdram density and banks |
| 29 | * bit[3:0] size(bit) size(byte) |
| 30 | * 0000 256Mb 32MB |
| 31 | * 0001 512Mb 64MB |
| 32 | * 0010 1Gb 128MB |
| 33 | * 0011 2Gb 256MB |
| 34 | * 0100 4Gb 512MB |
| 35 | * 0101 8Gb 1GB |
| 36 | * 0110 16Gb 2GB |
| 37 | * |
| 38 | * SPD byte8 - module memory bus width |
Wolfgang Denk | 0cf207e | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 39 | * bit[2:0] primary bus width |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 40 | * 000 8bits |
Wolfgang Denk | 0cf207e | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 41 | * 001 16bits |
| 42 | * 010 32bits |
| 43 | * 011 64bits |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 44 | * |
| 45 | * SPD byte7 - module organiztion |
Wolfgang Denk | 0cf207e | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 46 | * bit[2:0] sdram device width |
| 47 | * 000 4bits |
| 48 | * 001 8bits |
| 49 | * 010 16bits |
| 50 | * 011 32bits |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 51 | * |
| 52 | */ |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 53 | static unsigned long long |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 54 | compute_ranksize(const ddr3_spd_eeprom_t *spd) |
| 55 | { |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 56 | unsigned long long bsize; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 57 | |
| 58 | int nbit_sdram_cap_bsize = 0; |
| 59 | int nbit_primary_bus_width = 0; |
| 60 | int nbit_sdram_width = 0; |
| 61 | |
| 62 | if ((spd->density_banks & 0xf) < 7) |
| 63 | nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; |
| 64 | if ((spd->bus_width & 0x7) < 4) |
| 65 | nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; |
| 66 | if ((spd->organization & 0x7) < 4) |
| 67 | nbit_sdram_width = (spd->organization & 0x7) + 2; |
| 68 | |
Timur Tabi | e66f38d | 2009-07-01 16:51:59 -0500 | [diff] [blame] | 69 | bsize = 1ULL << (nbit_sdram_cap_bsize - 3 |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 70 | + nbit_primary_bus_width - nbit_sdram_width); |
| 71 | |
Marek Vasut | cd84b1f | 2011-10-21 14:17:19 +0000 | [diff] [blame] | 72 | debug("DDR: DDR III rank density = 0x%16llx\n", bsize); |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 73 | |
| 74 | return bsize; |
| 75 | } |
| 76 | |
| 77 | /* |
| 78 | * ddr_compute_dimm_parameters for DDR3 SPD |
| 79 | * |
| 80 | * Compute DIMM parameters based upon the SPD information in spd. |
| 81 | * Writes the results to the dimm_params_t structure pointed by pdimm. |
| 82 | * |
| 83 | */ |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 84 | unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, |
| 85 | const ddr3_spd_eeprom_t *spd, |
| 86 | dimm_params_t *pdimm, |
| 87 | unsigned int dimm_number) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 88 | { |
| 89 | unsigned int retval; |
| 90 | unsigned int mtb_ps; |
York Sun | 73b5396 | 2012-08-17 08:22:37 +0000 | [diff] [blame] | 91 | int ftb_10th_ps; |
york | 9490ff4 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 92 | int i; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 93 | |
| 94 | if (spd->mem_type) { |
| 95 | if (spd->mem_type != SPD_MEMTYPE_DDR3) { |
| 96 | printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number); |
| 97 | return 1; |
| 98 | } |
| 99 | } else { |
| 100 | memset(pdimm, 0, sizeof(dimm_params_t)); |
| 101 | return 1; |
| 102 | } |
| 103 | |
| 104 | retval = ddr3_spd_check(spd); |
| 105 | if (retval) { |
| 106 | printf("DIMM %u: failed checksum\n", dimm_number); |
| 107 | return 2; |
| 108 | } |
| 109 | |
| 110 | /* |
| 111 | * The part name in ASCII in the SPD EEPROM is not null terminated. |
| 112 | * Guarantee null termination here by presetting all bytes to 0 |
| 113 | * and copying the part name in ASCII from the SPD onto it |
| 114 | */ |
| 115 | memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); |
York Sun | d224654 | 2011-05-27 07:25:50 +0800 | [diff] [blame] | 116 | if ((spd->info_size_crc & 0xF) > 1) |
| 117 | memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 118 | |
| 119 | /* DIMM organization parameters */ |
| 120 | pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; |
| 121 | pdimm->rank_density = compute_ranksize(spd); |
| 122 | pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; |
| 123 | pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); |
| 124 | if ((spd->bus_width >> 3) & 0x3) |
| 125 | pdimm->ec_sdram_width = 8; |
| 126 | else |
| 127 | pdimm->ec_sdram_width = 0; |
| 128 | pdimm->data_width = pdimm->primary_sdram_width |
| 129 | + pdimm->ec_sdram_width; |
York Sun | b61e061 | 2013-06-25 11:37:47 -0700 | [diff] [blame] | 130 | pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 131 | |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 132 | /* These are the types defined by the JEDEC DDR3 SPD spec */ |
| 133 | pdimm->mirrored_dimm = 0; |
| 134 | pdimm->registered_dimm = 0; |
| 135 | switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { |
| 136 | case DDR3_SPD_MODULETYPE_RDIMM: |
| 137 | case DDR3_SPD_MODULETYPE_MINI_RDIMM: |
Ira W. Snyder | 2f3a71f | 2011-11-21 13:20:33 -0800 | [diff] [blame] | 138 | case DDR3_SPD_MODULETYPE_72B_SO_RDIMM: |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 139 | /* Registered/buffered DIMMs */ |
| 140 | pdimm->registered_dimm = 1; |
york | 9490ff4 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 141 | for (i = 0; i < 16; i += 2) { |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 142 | u8 rcw = spd->mod_section.registered.rcw[i/2]; |
| 143 | pdimm->rcw[i] = (rcw >> 0) & 0x0F; |
| 144 | pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; |
york | 9490ff4 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 145 | } |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 146 | break; |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 147 | |
| 148 | case DDR3_SPD_MODULETYPE_UDIMM: |
| 149 | case DDR3_SPD_MODULETYPE_SO_DIMM: |
| 150 | case DDR3_SPD_MODULETYPE_MICRO_DIMM: |
| 151 | case DDR3_SPD_MODULETYPE_MINI_UDIMM: |
Ira W. Snyder | 2f3a71f | 2011-11-21 13:20:33 -0800 | [diff] [blame] | 152 | case DDR3_SPD_MODULETYPE_MINI_CDIMM: |
| 153 | case DDR3_SPD_MODULETYPE_72B_SO_UDIMM: |
| 154 | case DDR3_SPD_MODULETYPE_72B_SO_CDIMM: |
| 155 | case DDR3_SPD_MODULETYPE_LRDIMM: |
| 156 | case DDR3_SPD_MODULETYPE_16B_SO_DIMM: |
| 157 | case DDR3_SPD_MODULETYPE_32B_SO_DIMM: |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 158 | /* Unbuffered DIMMs */ |
| 159 | if (spd->mod_section.unbuffered.addr_mapping & 0x1) |
| 160 | pdimm->mirrored_dimm = 1; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 161 | break; |
| 162 | |
| 163 | default: |
Kyle Moffett | c7fd27c | 2011-03-28 11:35:48 -0400 | [diff] [blame] | 164 | printf("unknown module_type 0x%02X\n", spd->module_type); |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 165 | return 1; |
| 166 | } |
| 167 | |
| 168 | /* SDRAM device parameters */ |
| 169 | pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; |
| 170 | pdimm->n_col_addr = (spd->addressing & 0x7) + 9; |
| 171 | pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7); |
| 172 | |
| 173 | /* |
| 174 | * The SPD spec has not the ECC bit, |
| 175 | * We consider the DIMM as ECC capability |
| 176 | * when the extension bus exist |
| 177 | */ |
| 178 | if (pdimm->ec_sdram_width) |
| 179 | pdimm->edc_config = 0x02; |
| 180 | else |
| 181 | pdimm->edc_config = 0x00; |
| 182 | |
| 183 | /* |
| 184 | * The SPD spec has not the burst length byte |
| 185 | * but DDR3 spec has nature BL8 and BC4, |
| 186 | * BL8 -bit3, BC4 -bit2 |
| 187 | */ |
| 188 | pdimm->burst_lengths_bitmask = 0x0c; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 189 | |
| 190 | /* MTB - medium timebase |
| 191 | * The unit in the SPD spec is ns, |
| 192 | * We convert it to ps. |
| 193 | * eg: MTB = 0.125ns (125ps) |
| 194 | */ |
| 195 | mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor; |
| 196 | pdimm->mtb_ps = mtb_ps; |
| 197 | |
| 198 | /* |
York Sun | 73b5396 | 2012-08-17 08:22:37 +0000 | [diff] [blame] | 199 | * FTB - fine timebase |
| 200 | * use 1/10th of ps as our unit to avoid floating point |
| 201 | * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps |
| 202 | */ |
| 203 | ftb_10th_ps = |
| 204 | ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f); |
| 205 | pdimm->ftb_10th_ps = ftb_10th_ps; |
| 206 | /* |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 207 | * sdram minimum cycle time |
| 208 | * we assume the MTB is 0.125ns |
| 209 | * eg: |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 210 | * tck_min=15 MTB (1.875ns) ->DDR3-1066 |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 211 | * =12 MTB (1.5ns) ->DDR3-1333 |
| 212 | * =10 MTB (1.25ns) ->DDR3-1600 |
| 213 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 214 | pdimm->tckmin_x_ps = spd->tck_min * mtb_ps + |
| 215 | (spd->fine_tck_min * ftb_10th_ps) / 10; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 216 | |
| 217 | /* |
| 218 | * CAS latency supported |
| 219 | * bit4 - CL4 |
| 220 | * bit5 - CL5 |
| 221 | * bit18 - CL18 |
| 222 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 223 | pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 224 | |
| 225 | /* |
| 226 | * min CAS latency time |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 227 | * eg: taa_min = |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 228 | * DDR3-800D 100 MTB (12.5ns) |
| 229 | * DDR3-1066F 105 MTB (13.125ns) |
| 230 | * DDR3-1333H 108 MTB (13.5ns) |
| 231 | * DDR3-1600H 90 MTB (11.25ns) |
| 232 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 233 | pdimm->taa_ps = spd->taa_min * mtb_ps + |
| 234 | (spd->fine_taa_min * ftb_10th_ps) / 10; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 235 | |
| 236 | /* |
| 237 | * min write recovery time |
| 238 | * eg: |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 239 | * twr_min = 120 MTB (15ns) -> all speed grades. |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 240 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 241 | pdimm->twr_ps = spd->twr_min * mtb_ps; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 242 | |
| 243 | /* |
| 244 | * min RAS to CAS delay time |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 245 | * eg: trcd_min = |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 246 | * DDR3-800 100 MTB (12.5ns) |
| 247 | * DDR3-1066F 105 MTB (13.125ns) |
| 248 | * DDR3-1333H 108 MTB (13.5ns) |
| 249 | * DDR3-1600H 90 MTB (11.25) |
| 250 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 251 | pdimm->trcd_ps = spd->trcd_min * mtb_ps + |
| 252 | (spd->fine_trcd_min * ftb_10th_ps) / 10; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 253 | |
| 254 | /* |
| 255 | * min row active to row active delay time |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 256 | * eg: trrd_min = |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 257 | * DDR3-800(1KB page) 80 MTB (10ns) |
| 258 | * DDR3-1333(1KB page) 48 MTB (6ns) |
| 259 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 260 | pdimm->trrd_ps = spd->trrd_min * mtb_ps; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 261 | |
| 262 | /* |
| 263 | * min row precharge delay time |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 264 | * eg: trp_min = |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 265 | * DDR3-800D 100 MTB (12.5ns) |
| 266 | * DDR3-1066F 105 MTB (13.125ns) |
| 267 | * DDR3-1333H 108 MTB (13.5ns) |
| 268 | * DDR3-1600H 90 MTB (11.25ns) |
| 269 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 270 | pdimm->trp_ps = spd->trp_min * mtb_ps + |
| 271 | (spd->fine_trp_min * ftb_10th_ps) / 10; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 272 | |
| 273 | /* min active to precharge delay time |
| 274 | * eg: tRAS_min = |
| 275 | * DDR3-800D 300 MTB (37.5ns) |
| 276 | * DDR3-1066F 300 MTB (37.5ns) |
| 277 | * DDR3-1333H 288 MTB (36ns) |
| 278 | * DDR3-1600H 280 MTB (35ns) |
| 279 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 280 | pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 281 | * mtb_ps; |
| 282 | /* |
| 283 | * min active to actice/refresh delay time |
| 284 | * eg: tRC_min = |
| 285 | * DDR3-800D 400 MTB (50ns) |
| 286 | * DDR3-1066F 405 MTB (50.625ns) |
| 287 | * DDR3-1333H 396 MTB (49.5ns) |
| 288 | * DDR3-1600H 370 MTB (46.25ns) |
| 289 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 290 | pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb) |
| 291 | * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 292 | /* |
| 293 | * min refresh recovery delay time |
| 294 | * eg: tRFC_min = |
| 295 | * 512Mb 720 MTB (90ns) |
| 296 | * 1Gb 880 MTB (110ns) |
| 297 | * 2Gb 1280 MTB (160ns) |
| 298 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 299 | pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 300 | * mtb_ps; |
| 301 | /* |
| 302 | * min internal write to read command delay time |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 303 | * eg: twtr_min = 40 MTB (7.5ns) - all speed bins. |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 304 | * tWRT is at least 4 mclk independent of operating freq. |
| 305 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 306 | pdimm->twtr_ps = spd->twtr_min * mtb_ps; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 307 | |
| 308 | /* |
| 309 | * min internal read to precharge command delay time |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 310 | * eg: trtp_min = 40 MTB (7.5ns) - all speed bins. |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 311 | * tRTP is at least 4 mclk independent of operating freq. |
| 312 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 313 | pdimm->trtp_ps = spd->trtp_min * mtb_ps; |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 314 | |
| 315 | /* |
| 316 | * Average periodic refresh interval |
| 317 | * tREFI = 7.8 us at normal temperature range |
| 318 | * = 3.9 us at ext temperature range |
| 319 | */ |
| 320 | pdimm->refresh_rate_ps = 7800000; |
Valentin Longchamp | 7e157b0 | 2013-10-18 11:47:20 +0200 | [diff] [blame] | 321 | if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { |
| 322 | pdimm->refresh_rate_ps = 3900000; |
| 323 | pdimm->extended_op_srt = 1; |
| 324 | } |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 325 | |
| 326 | /* |
| 327 | * min four active window delay time |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 328 | * eg: tfaw_min = |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 329 | * DDR3-800(1KB page) 320 MTB (40ns) |
| 330 | * DDR3-1066(1KB page) 300 MTB (37.5ns) |
| 331 | * DDR3-1333(1KB page) 240 MTB (30ns) |
| 332 | * DDR3-1600(1KB page) 240 MTB (30ns) |
| 333 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 334 | pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 335 | * mtb_ps; |
| 336 | |
Dave Liu | c360cea | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 337 | return 0; |
| 338 | } |