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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Kumar Gala2a6c2d72008-08-26 21:34:55 -05002/*
York Sund29d17d2011-08-26 11:32:44 -07003 * Copyright 2008-2011 Freescale Semiconductor, Inc.
Kumar Gala2a6c2d72008-08-26 21:34:55 -05004 */
5
6#include <common.h>
7#include <asm/io.h>
Kumar Gala5ace2992011-09-16 09:54:30 -05008#include <asm/processor.h>
York Sun5614e712013-09-30 09:22:09 -07009#include <fsl_ddr_sdram.h>
Simon Glassc05ed002020-05-10 11:40:11 -060010#include <linux/delay.h>
Kumar Gala2a6c2d72008-08-26 21:34:55 -050011
12#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
13#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
14#endif
15
16void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
York Sunc63e1372013-06-25 11:37:48 -070017 unsigned int ctrl_num, int step)
Kumar Gala2a6c2d72008-08-26 21:34:55 -050018{
19 unsigned int i;
York Sun9a17eb52013-11-18 10:29:32 -080020 struct ccsr_ddr __iomem *ddr =
Tom Rini6cc04542022-10-28 20:27:13 -040021 (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
Andy Fleminge76cd5d2012-10-23 19:03:46 -050022
23#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
Tom Rini51552072022-10-28 20:27:12 -040024 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala5ace2992011-09-16 09:54:30 -050025 uint svr;
26#endif
Kumar Gala2a6c2d72008-08-26 21:34:55 -050027
28 if (ctrl_num) {
29 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
30 return;
31 }
32
Kumar Gala5ace2992011-09-16 09:54:30 -050033#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
34 /*
35 * Set the DDR IO receiver to an acceptable bias point.
36 * Fixed in Rev 2.1.
37 */
38 svr = get_svr();
39 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
40 if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
41 SDRAM_CFG_SDRAM_TYPE_DDR2)
42 out_be32(&gur->ddrioovcr, 0x90000000);
43 else
44 out_be32(&gur->ddrioovcr, 0xA8000000);
45 }
46#endif
47
Kumar Gala2a6c2d72008-08-26 21:34:55 -050048 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
49 if (i == 0) {
50 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
51 out_be32(&ddr->cs0_config, regs->cs[i].config);
52
53 } else if (i == 1) {
54 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
55 out_be32(&ddr->cs1_config, regs->cs[i].config);
56
57 } else if (i == 2) {
58 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
59 out_be32(&ddr->cs2_config, regs->cs[i].config);
60
61 } else if (i == 3) {
62 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
63 out_be32(&ddr->cs3_config, regs->cs[i].config);
64 }
65 }
66
67 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
68 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
69 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
70 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
71 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
72 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
73 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
74 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
75 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
76 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
77 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
78 out_be32(&ddr->init_addr, regs->ddr_init_addr);
79 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
80
81 /*
82 * 200 painful micro-seconds must elapse between
83 * the DDR clock setup and the DDR config enable.
84 */
85 udelay(200);
86 asm volatile("sync;isync");
87
88 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
89
90 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
91 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
92 udelay(10000); /* throttle polling rate */
93 }
94}