NSA — Normalization Shift Amount

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
NSA 010000001110 0000
t 3210
s 3210

Assembler Syntax

NSA at, as

C Syntax

#include <xtensa/tie/xt_misc.h>

extern int XT_NSA(int s);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

NSA calculates the left shift amount that will normalize the twos complement contents of address register as and writes this amount (in the range 0 to 31) to address register at. If as contains 0 or -1, NSA returns 31. Using SSL and SLL to shift as left by the NSA result yields the smallest value for which bits 31 and 30 differ unless as contains 0.

Operation

sign ← AR[s]31
if AR[s]30..0 = sign31 then
	AR[t] ← 31
else
	b4 ← AR[s]30..16 = sign15
	t3 ← if b4 then AR[s]15..0 else AR[s]31..16
	b3 ← t315..8 = sign8
	t2 ← if b3 then t37..0 else t315..8
	b2 ← t37..4 = sign4
	t1 ← if b2 then t23..0 else t27..4
	b1 ← t33..2 = sign2
	b0 ← if b1 then t11 = sign	 else t13 = sign
	AR[t] ← 027||((b4||b3||b2||b1||b0) − 1)
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
ars Estage art Estage

Protos that use NSA

proto NSA { out int32 t, in int32 s }{}{
NSA t, s;
}