Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PDTLB | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||
t | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 |
PDTLB a
t
, as
extern unsigned XT_PDTLB(unsigned ars);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
PDTLB
searches the data TLB for an entry that translates the virtual address in address register as
and writes the way and index of that entry to address register at
. If no entry matches, zero is written to the hit bit of at
. The value written to at
is implementation-specific, but in all implementations a value with the hit bit set is suitable as an input to the IDTLB
or WDTLB
instructions. See for information on the result register formats for specific memory protection and translation options.
PDTLB
is a privileged instruction.
if CRING != 0 then Exception (PrivilegedCause) else (match, vpn, ei, wi) ← ProbeDataTLB(AR[s]) if match > 1 then EXCVADDR ← AR[s] Exception (LoadStoreTLBMultiHit) else AR[t] ← PackDataTLBEntrySpec(match, vpn, ei, wi) endif endif