RFDD — Return from Debug and Dispatch

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
RFDD 111100011110 00010000

Assembler Syntax

RFDD

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

This instruction is used only in On-Chip Debug Mode and exists only in some implementations. It is an illegal instruction when the processor is not in On-Chip Debug Mode. See the Xtensa Debug Guide for a description of its operation.

Exceptions

EveryInst Group (see EveryInst Group:)GenExcep(IllegalInstructionCause) if Exception Option

Implementation Pipeline

In Out
InOCDMode Estage InOCDMode Estage