Memory | Size | Address | Inbound PIF | Busy |
---|---|---|---|---|
Instruction RAM 0 | 32K | 0xe8080000 | Selected | Not Selected |
Instruction RAM 1 | 16K | 0xe8088000 | Selected | Not Selected |
Data RAM 0 | 32K | 0xe8058000 | Selected | Not Selected |
Data RAM 1 | 128K | 0xe8060000 | Selected | Not Selected |
Note that the "normal" L32R instruction which is used to load literals has a range of 256K bytes preceding the current PC, so the default positioning of instruction / data puts data memories before instruction memories so the data memory can be used for literal storage. If there is no data memory within range, the editor warns because the compiler may have problems generating literals if compiling code into that memory.
Attributes that can be selected for local memory interfaces (inbound PIF, busy and memory error) must be consistent for each memory type. E.g. if you configure 2 data RAMs then either both must have inbound PIF configured, or neither.
Selecting Inbound PIF allows an external PIF master to read/write to Xtensa's internal memories. When the inbound-PIF request option is enabled, an inbound-PIF request buffer is added to the processor.
Selecting Busy will create an external interface to the processor that the processor will check before writing to the memory.
Banks: Data RAM and Data ROM can optionally be configured in 2 or 4 banks. If multiple banks are configured, then the data RAM is divided into banks so that successive data memory width sized accesses go to different banks. At most one load or store can go to any one bank in a cycle.
Split Read-Write port: For multiple load-store configurations, this brings out the interfaces for all load-store units so you can handle the multiplexing and banking ouside of the core. The alternative is to select CBOX which handles the multiplexing inside the core.
See the appropriate Data Book for more detailed information.