Interrupt Configuration

Count of interrupts
32
Count of interrupt levels
5
Count of timers
2
Debug level
5
EXCM level
3
Table 1. Interrupts Details
Interrupt Type Level BInterrupt Pin
0 nmi nmi 0
1 sw 3  
2 level 3 1
3 level 3 2
4 level 3 3
5 timer.0 3  
6 timer.1 4  
7 level 3 4
8 level 2 5
9 level 2 6
10 level 2 7
11 level 2 8
12 level 1 9
13 level 1 10
14 level 1 11
15 level 1 12
16 level 1 13
17 level 1 14
18 level 1 15
19 profiling 3  
20 level 1 16
21 level 1 17
22 level 1 18
23 level 1 19
24 level 1 20
25 level 1 21
26 level 1 22
27 level 1 23
28 level 1 24
29 writeerr 3  
30 level 1 25
31 level 1 26

Interrupt Information

The following sections contain basic information for using the processor interrupts. Setting interrupts requires detailed understanding of the SOC design and the related devices. Refer to the Xtensa Microprocessor Programmer's Guide and the appropriate Xtensa Microprocessor Data Book for more information on the behavior and support of different levels of interrupts.

Interrupt Types

Interrupt types can be any of the values listed in the table below. The column labeled "Priority" shows the possible range of priorities for the interrupt type. The column labeled "Pin" indicates whether there is an Xtensa core pin associated with the interrupt, while the column labeled "Bit" indicates whether or not there is a bit in the INTERRUPT and INTENABLE Special Registers corresponding to the interrupt. The last two columns indicate how the interrupt may be set and how it may be cleared.

Table 2. Interrupt Types
Type Priority Pin? Bit? How Interrupt is Set How Interrupt is Cleared
Level 1 to N Yes Yes Signal level from device At device
Edge 1 to N Yes Yes Signal rising edge WSR.INTCLEAR '1'
NMI N+1 Yes No Signal rising edge Automatically cleared by HW
Software 1 to N No Yes WSR.INTSET '1' WSR.INTCLEAR '1'
Timer 1 to N No Yes CCOUNT=CCOMPAREn WSR.CCOMPAREn
Debug 2 to N No No Debug hardware Automatically cleared by HW
WriteErr 1 to N No Yes Bus error on write WSR.INTCLEAR '1'
Profile 1 to N No Yes Profiling interrupt Clear in profiling logic

Interrupt Levels

Low-Level Interrupts

Level 1 interrupts are intended for non real-time interrupts. These interrupts are slower at interrupt handling due to sharing of general dispatch handlers. Level 1 interrupts will go to either the UserExceptionVector or the KernelExceptionVector. The EXCCAUSE register will identify the exception as a level-one interrupt, and software handlers can respond accordingly.

Mid-Level Interrupts

Mid-level interrupts are faster than Level 1 interrupts because they have a dedicated handler (Level<N>InterruptVector). Also, because they are C-callable, they are easy to program. Note: To program a mid-level interrupt you need to save/restore the state when entering/exiting the handler. Mid-level interrupts go to a dedicated vector. For example:
Level2InterruptVector
Level3InterruptVector
...
High-Level Interrupts

High-level interrupts, which are written in assembly, are the fastest interrupts (with the lowest latency) because they have a dedicated handler. Supporting Interrupts Service Routines (ISRs) in assembly only requires that the handler saves/restores the registers that it uses and issues RFE/RFI when done. Also, because latency of high-level interrupt is very important, designers should understand the latency of the execution of the handler (including memory latency).

Sometimes, it is possible to have a high-level interrupt trigger a lower level interrupt in which the handler is written in C.