RITLB0 — Read Instruction TLB Entry Virtual

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
RITLB0 010100000011 0000
t 3210
s 3210

Assembler Syntax

RITLB0 at, as

C Syntax

#include <xtensa/tie/xt_mmu.h>

extern unsigned XT_RITLB0(unsigned ars);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

RITLB0 reads the instruction TLB entry specified by the contents of address register as and writes the Virtual Page Number (VPN) and address space ID (ASID) to address register at. See for information on the address and result register formats for specific memory protection and translation options.

RITLB0 is a privileged instruction.

Operation

AR[t] ← RITLB0(AR[s])

Exceptions

EveryInstR Group (see EveryInstR Group:)GenExcep(PrivilegedCause) if Exception Option

Protos that use RITLB0

proto RITLB0 { out uint32 art, in uint32 ars }{}{
RITLB0 art, ars;
}