AE_SRAA32S — 2-way shift right (arithmetic sign-extending) by AR register

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_SRAA32S 1000000000011001 0010
ae_fld_shift_d 3210
ae_fld_shift_d0 3210
s 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_SRAA32S 10000010 0100
ae_fld_shift_d 3210
ae_fld_shift_d0 3210
s 3210

Slot
ae_minislot2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_mini0 - 64 bit(s)01000000000000000000000 1110
AE_SRAA32S 1101001
ae_fld_shift_d 3210
ae_fld_shift_d0 3210
s 3210

Assembler Syntax

AE_SRAA32S aed0..15(ae_shift_d), aed0..15(ae_shift_d0), a0..15(ars)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_f32x2 AE_SRAA32S(ae_f32x2 d0, int sa);

Description

AE_SRAA32S is a two-way arithmetic (sign-extending) right shift of AE_DR register d0 by AR register a, with result placed in d. The result is matches the semantics of the ITU intrinsic L_shr.

d.L = d0.L >>s a

d.H = d0.H >>s a

Implementation Pipeline

In Out
AE_OVERFLOW Wstage, ae_shift_d0 Mstage, ars Estage AE_OVERFLOW Wstage, ae_shift_d Mstage

Protos that use AE_SRAA32S

proto AE_SRAA32S { out ae_f32x2 d, in ae_f32x2 d0, in int32 sa }{}{
AE_SRAA32S d, d0, sa;
}
proto AE_SRAA32S_scalar { out ae_int32 d, in ae_int32 d0, in int32 sa }{}{
AE_SRAA32S d, d0, sa;
}
proto AE_SRAA32S_vector { out ae_int32x4 d, in ae_int32x4 d0, in int32 sa }{}{
AE_SRAA32S d->d0, d0->d0, sa;
AE_SRAA32S d->d1, d0->d1, sa;
}