L16SI — Load 16-bit Signed

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
L16SI 1001 0010
t 3210
s 3210
imm8 76543210

Assembler Syntax

L16SI at, as, 0..510

C Syntax

#include <xtensa/tie/xt_core.h>

extern short XT_L16SI(const short * p, immediate i);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

L16SI is a 16-bit signed load from memory. It forms a virtual address by adding the contents of address register as and an 8-bit zero-extended constant value encoded in the instruction word shifted left by 1. Therefore, the offset can specify multiples of two from zero to 510. Sixteen bits (two bytes) are read from the physical address. This data is then sign-extended and written to address register at.

If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation or memory reference encounters an error (for example, protection violation, non-existent memory), the processor raises one of several exceptions .

Without the Unaligned Exception Option , the least significant address bit is ignored; a reference to an odd address produces the same result as a reference to the address minus one. With the Unaligned Exception Option, such an access raises an exception.

Operation

vAddr ← AR[s] + (023||imm8||0)
(mem16, error) ← Load16(vAddr)
if error then
	EXCVADDR ← vAddr
	Exception (LoadStoreErrorCause)
else
	AR[t] ← mem161516||mem16
endif

Exceptions

Memory Load Group (see Memory Load Group:)

Protos that use L16SI

proto L16SI { out int16 r, in const int16 * p, in immediate i }{}{
L16SI r, p, i + 0;
}