AE_ADD16S — 4-way 16-bit signed, saturating addition

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_ADD16S 1000000000010010 1100
ae_fld_arth_v 3210
ae_fld_arth_v0 3210
ae_fld_arth_v1 3210

Slot
ae2_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_ADD16S 1101 0100 0000
ae_fld_arth_v 3210
ae_fld_arth_v0 3210
ae_fld_arth_v1 3210

Slot
ae_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_ADD16S 11100101
ae_fld_arth_v 3210
ae_fld_arth_v0 3210
ae_fld_arth_v1 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_ADD16S 00110011 0100
ae_fld_arth_v 3210
ae_fld_arth_v0 3210
ae_fld_arth_v1 3210

Slot
ae_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_ADD16S 11100101
ae_fld_arth_v 3210
ae_fld_arth_v0 3210
ae_fld_arth_v1 3210

Slot
ae_slot2_1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_ADD16S 0010001
ae_fld_arth_v 3210
ae_fld_arth_v0 3210
ae_fld_arth_v1 3210

Assembler Syntax

AE_ADD16S aed0..15(ae_arth_v), aed0..15(ae_arth_v0), aed0..15(ae_arth_v1)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_f16x4 AE_ADD16S(ae_f16x4 d0, ae_f16x4 d1);

Description

AE_ADD16S is an element-wise, signed, saturating 16-bit addition of two AE_DR registers d0 and d1. The result placed in d is { sat(d0[63:48] + d1[63:48]) , sat(d0[47:32] + d1[47:32]) , sat(d0[31:16] + d1[31:16]) , sat(d0[15:0] + d1[15:0]) }.

In case of saturation, state AE_OVERFLOW is set to 1.

Implementation Pipeline

In Out
AE_OVERFLOW Wstage, ae_arth_v0 Mstage, ae_arth_v1 Mstage AE_OVERFLOW Wstage, ae_arth_v Mstage

Protos that use AE_ADD16S

proto AE_ADD16S { out ae_f16x4 d, in ae_f16x4 d0, in ae_f16x4 d1 }{}{
AE_ADD16S d, d0, d1;
}
proto AE_ADD16S_scalar { out ae_int16 p, in ae_int16 d0, in ae_int16 d1 }{}{
AE_ADD16S p, d0, d1;
}
proto AE_ADD16S_vector { out ae_int16x4 p, in ae_int16x4 d0, in ae_int16x4 d1 }{}{
AE_ADD16S p, d0, d1;
}
proto AE_F16X4_ADDS_F16 { out ae_f16x4 d, in ae_f16x4 d0, in ae_f16 d1 }{}{
AE_ADD16S d, d0, d1;
}
proto AE_F16X4_ADDS_F16X4 { out ae_f16x4 d, in ae_f16x4 d0, in ae_f16x4 d1 }{}{
AE_ADD16S d, d0, d1;
}
proto AE_F16_ADDS_F16 { out ae_f16 d, in ae_f16 d0, in ae_f16 d1 }{}{
AE_ADD16S d, d0, d1;
}
proto AE_F16_ADDS_F16X4 { out ae_f16x4 d, in ae_f16 d0, in ae_f16x4 d1 }{}{
AE_ADD16S d, d0, d1;
}