Slot Inst16a | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x16a - 16 bit(s) | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
ADDI.N | 1 | 0 | 1 | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
r | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
t | 3 | 2 | 1 | 0 |
ADDI.N ar, as, imm
extern int XT_ADDI_N(int s, immediate i);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
ADDI.N
is similar to ADDI
, but has a 16-bit encoding and supports a smaller range of immediate operand values encoded in the instruction word.
ADDI.N
calculates the two's complement 32-bit sum of address register as
and an operand encoded in the t
field. The low 32 bits of the sum are written to address register ar
. Arithmetic overflow is not detected.
The operand encoded in the instruction can be -1 or one to 15. If t
is zero, then a value of -1 is used, otherwise the value is the zero-extension of t
.
AR[r] ← AR[s] + (if t = 04 then 132 else 028||t)
In | Out |
---|---|
ars Estage
|
arr Estage
|