Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CALLX4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 |
CALLX4 as
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
CALLX4
calls subroutines using the register windows mechanism, requesting the callee rotate the window by four registers. The CALLX4
instruction does not rotate the window itself, but instead stores the window increment for later use by the ENTRY
instruction. The return address and window increment are placed in the caller's a4
(the callee's a0
), and the processor then branches to the target address. The return address is the address of the next instruction (the address of the CALLX4
instruction plus three). The window increment is also stored in the CALLINC
field of the PS
register, where it is accessed by the ENTRY
instruction.
The target instruction address of the call is given by the contents of address register as
. The target instruction must be an ENTRY
instruction.
See the CALL4
instruction for calling routines where the target address is given by a PC-relative offset in the instruction.
The RETW
and RETW.N
instructions return from a subroutine called by CALLX4
.
The window increment stored with the return address register in a4
occupies the two most significant bits of the register, and therefore those bits must be filled in by the subroutine return. The RETW
and RETW.N
instructions fill in these bits from the two most significant bits of their own address. This prevents register-window calls from being used to call a routine in a different 1GB region of the address space.
See the CALLX0
instruction for calling routines using the non-windowed subroutine protocol.
The caller's a4
..a15
are the same registers as the callee's a0
..a11
after the callee executes the ENTRY
instruction. You can use these registers for parameter passing. The caller's a0
..a3
are hidden by CALLX4
, and therefore you may use them to keep values that are live across the call.
WindowCheck (00, 00, 01) PS.CALLINC ← 01 tmp ← nextPC nextPC ← AR[s] AR[01||00] ← 01||(tmp)29..0
In | Out |
---|---|
ars Estage
|
PSCALLINC Estage
|