AE_MULF32S.LL — 32x32-bit signed fractional (1.31) multiplication with 64-bit (1.63) result, with saturation.

Instruction Word

Slot
ae2_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_MULF32S.LL 1100 0111 0011
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Slot
ae_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_MULF32S.LL 01100010
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Slot
ae_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_MULF32S.LL 01100010
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Assembler Syntax

AE_MULF32S.LL aed0..15(ae_mul_q0), aed0..15(ae_mul_d0), aed0..15(ae_mul_d1)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_f64 AE_MULF32S_LL(ae_f32x2 d0, ae_f32x2 d1);

Description

AE_MULF32S.LL is a 32x32-bit signed fractional (1.31) multiplication with 64-bit (1.63) result, with 64-bit saturation. The extension LL indicates that the multiplication result is the product of the two AE_DR operands' L elements.

Implementation Pipeline

In Out
AE_OVERFLOW Wstage, ae_mul_d0 Mstage, ae_mul_d1 Mstage AE_OVERFLOW Wstage, ae_mul_q0 Wstage

Protos that use AE_MULF32S.LL

proto AE_MULF24S.LL { out ae_f64 d, in ae_f24x2 d0, in ae_f24x2 d1 }{}{
AE_MULF32S.LL d, d0, d1;
}
proto AE_MULF32S.LL { out ae_f64 d, in ae_f32x2 d0, in ae_f32x2 d1 }{}{
AE_MULF32S.LL d, d0, d1;
}
proto AE_MULFP24S.LL { out ae_q56s d, in ae_p24x2s d0, in ae_p24x2s d1 }{}{
AE_MULF32S.LL d, d0, d1;
}
proto AE_P24F_MULF_P24F { out ae_q56s d, in ae_p24f d0, in ae_p24f d1 }{}{
AE_MULF32S.LL d, d0, d1;
}
proto AE_P24F_MULF_P24S { out ae_q56s d, in ae_p24f d0, in ae_p24s d1 }{}{
AE_MULF32S.LL d, d0, d1;
}
proto AE_P24S_MULF_P24F { out ae_q56s d, in ae_p24s d0, in ae_p24f d1 }{}{
AE_MULF32S.LL d, d0, d1;
}
proto AE_P24S_MULF_P24S { out ae_q56s d, in ae_p24s d0, in ae_p24s d1 }{}{
AE_MULF32S.LL d, d0, d1;
}