Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
LDDEC | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||
w | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 |
LDDEC mw, as
extern void XT_LDDEC(immediate w, const short * p /*inout*/);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
LDDEC
loads MAC16 register mw
from memory using auto-decrement addressing. It forms a virtual address by subtracting 4 from the contents of address register as
. 32 bits (four bytes) are read from the physical address. This data is then written to MAC16 register mw
, and the virtual address is written back to address register as
.
If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation or memory reference encounters an error (for example, protection violation or non-existent memory), the processor raises one of several exceptions .
Without the Unaligned Exception Option , the two least significant bits of the address are ignored. A reference to an address that is not 0 mod 4 produces the same result as a reference to the address with the least significant bits cleared. With the Unaligned Exception Option, such an access raises an exception.
vAddr ← AR[s] − 4 (mem32, error) ← Load32(vAddr) if error then EXCVADDR ← vAddr Exception (LoadStoreErrorCause) else MR[w] ← mem32 AR[s] ← vAddr endif
Memory Load Group (see Memory Load Group:)
In | Out |
---|---|
ars Estage
|
mw Mstage , ars Estage
|