RER — Read ExternalRegister

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
RER 010000000110 0000
t 3210
s 3210

Assembler Syntax

RER at, as

C Syntax

#include <xtensa/tie/xt_externalregisters.h>

extern unsigned XT_RER(unsigned ars);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

RER reads one of a set of "External Registers". It is in some ways similar to the RSR.* instruction except that the registers being read are not defined by the Xtensa ISA and are conceptually outside the processor core. They are read through processor ports.

Address register as is used to determine which register is to be read and the result is placed in address register at. When no External Register is addressed by the value in address register as, the result in address register at is undefined. The entire address space is reserved for use by Cadence. RER and WER are managed by the processor core so that the requests appear on the processor ports in program order. External logic is responsible for extending that order to the registers themselves.

RER is a privileged instruction.

Operation

if CRING != 0 then
	Exception (PrivilegedCause)
else
	Read External Register as defined outside the processor.
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)GenExcep(PrivilegedCause) if Exception Option

Protos that use RER

proto RER { out uint32 art, in uint32 ars }{}{
RER art, ars;
}