BEQ — Branch if Equal

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
BEQ 0001 0111
s 3210
t 3210
imm8 76543210

Assembler Syntax

BEQ as, at, label

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

BEQ branches if address registers as and at are equal.

The target instruction address of the branch is given by the address of the BEQ instruction plus the sign-extended 8-bit imm8 field of the instruction plus four. If the registers are not equal, execution continues with the next sequential instruction.

The inverse of BEQ is BNE.

Operation

if AR[s] = AR[t] then
	nextPC ← PC + (imm8724||imm8) + 4
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)