SSA8L — Set Shift Amount for LE Byte Shift

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
SSA8L 010000000010 00000000
s 3210

Assembler Syntax

SSA8L as

C Syntax

#include <xtensa/tie/xt_core.h>

extern void XT_SSA8L(int s);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

SSA8L sets the shift amount register (SAR) for a right shift by multiples of eight (for example, for little-endian (LE) byte alignment). The right shift amount is the two least significant bits of address register as multiplied by eight, and is written to SAR. SSA8L is similar to SSR, except the shift amount is multiplied by eight.

SSA8L is typically used to set up for an SRC instruction to shift bytes. It may be used with little-endian byte ordering to extract a 32-bit value from a non-aligned byte address.

Operation

SAR ← 0||AR[s]1..0||03

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
ars Estage SAR Estage

Protos that use SSA8L

proto SSA8L { in int32 s }{}{
SSA8L s;
}