• Processor Configuration Overview
    • Summary
  • Processor Configuration Options
    • Processor Selections
      • HiFi 3 Audio Engine option
    • Software Configuration Options
      • C and Math Libraries
      • Application Binary Interfaces
      • Build with Reset Handler at Alternate Reset Base
      • RTOS Compatibility Option
    • Implementation Options
      • Global Clock Gating
      • Functional Unit Clock Gating
      • Asynchronous Reset
      • Full Scan option
      • Size of L0 Loop Buffer option
      • Semantic Data Gating option
      • Memory Data Gating option
    • Instruction / ISA Options
      • Memory Management Selection
      • Arithmetic Instruction Options
        • MUL32 Option
        • MUL16 Option
        • MAC16 DSP Instruction Family
        • CLAMPS Option
        • 32-Bit Integer Divider
      • Miscellaneous ISA Instruction Options
        • NSA/NSAU Option
        • MinMax Option
        • SEXT (Sign Extend To 32-bits) Option
        • Density Instructions
        • Boolean Registers option
        • Processor ID Option
        • TIE Arbitrary Byte Enables Option
        • Zero-Overhead Loops Option
        • Synchronize Instruction
        • Conditional Store Sync option
        • Number of Coprocessors option
        • Misc Special registers option
      • ISA Configuration Options
        • AR Registers Count
        • Byte Ordering Option
        • Unaligned Load / Store Action Selection
        • Max Instruction Width Option
        • L32R Hardware Support Option
        • Pipeline Options
    • Interface Options
      • Bus and Bridge Selections
        • PIF / Bus Selection
        • AXI Bridge Options
          • AXI Slave Request Control Depth option
          • AXI Slave Request Data Depth option
          • AXI Slave Response Depth option
      • PIF Options
        • Count of PIF Write Buffer Entries
        • Inbound PIF Request Buffer Depth
        • PIF Write Responses option
        • PIF Critical Word First option
        • PIF Arbitrary Byte Enable option
        • Early Restart option
      • Prefetch Options
        • Cache Prefetch Entries
      • Interface Width Options
        • Width of Instruction Fetch Interface
        • Width of Data Memory/Cache Interface
        • Width of Instruction Cache Interface
        • Width of PIF Interface
      • Port / Queue Options
        • GPIO32 Option
      • Caches and Local Memories
        • Instruction Cache Details
        • Data Cache Details
        • Local Memories
        • Automatically Select Memory Addresses
        • Load/Store Units
    • Debug and Trace Options
      • Debug option
        • Count of HW Instruction Traps
        • Count of HW Data Traps
        • On-Chip Debug option
        • APB Debug Access option
        • Break-in Break-out option
        • Performance Counters Option
      • Trace option
        • TRAX Memory Size
    • Interrupt Options
      • Interrupt Configuration
    • Vector and System Memory Options
      • System Memories
      • Automatically Position Vectors
      • Vector Layout Style
      • Relocatable Vectors option
      • Alternate Static Vector Base Address
      • External Reset Vector
      • Default Dynamic Vector Group Vector Base
      • Static Vectors
      • Dynamic Vectors