DPFL — Data Cache Prefetch and Lock

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
DPFL 00000111 10000010
s 3210
op2 3210

Assembler Syntax

DPFL as, 0..240

C Syntax

#include <xtensa/tie/xt_datacache.h>

extern void XT_DPFL(const int * s, immediate i);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

DPFL performs a data cache prefetch and lock. The purpose of DPFL is to improve performance, and not to affect state defined by the ISA. Xtensa ISA implementations that do not implement cache locking must raise an illegal instruction exception when this opcode is executed. In general, the performance improvement from using this instruction is implementation-dependent.

DPFL checks if the line containing the specified address is present in the data cache, and if not, it begins the transfer of the line from memory to the cache. The line is placed in the data cache and the line marked as locked, that is not replaceable by ordinary data cache misses. To unlock the line, use DHU or DIU. To prefetch without locking, use the DPFR, DPFW, DPFRO, or DPFWO instructions.

DPFL forms a virtual address by adding the contents of address register as and a 4-bit zero-extended constant value encoded in the instruction word shifted left by four. Therefore, the offset can specify multiples of 16 from zero to 240. If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. The translation is done as if the address were for a load.

Because the organization of caches is implementation-specific, the operation section below specifies only a call to the implementation's dprefetch function.

DPFL is a privileged instruction.

Operation

if CRING != 0 then
	Exception (PrivilegedCause)
else
	vAddr ← AR[s] + (024||imm4||04)
	(pAddr, attributes, cause) ← ltranslate(vAddr, CRING)
	if invalid(attributes) then
		EXCVADDR ← vAddr
		Exception (cause)
	else
		dprefetch(vAddr, pAddr, 0, 0, 1)
	endif
endif

Exceptions

Memory Group (see Memory Group:)GenExcep(LoadProhibitedCause) if Region Protection Option or MMU OptionGenExcep(PrivilegedCause) if Exception Option

Protos that use DPFL

proto DPFL { in const int32 * s, in immediate i }{}{
DPFL s, i + 0;
}