Group | Signal Names | Bit-index | Direction |
---|---|---|---|
AXI Master | |||
ARADDR | [32-1:0] | output | |
ARBURST | [2-1:0] | output | |
ARCACHE | [4-1:0] | output | |
ARID | [4-1:0] | output | |
ARLEN | [4-1:0] | output | |
ARLOCK | [2-1:0] | output | |
ARPROT | [3-1:0] | output | |
ARREADY | input | ||
ARSIZE | [3-1:0] | output | |
ARVALID | output | ||
AWADDR | [32-1:0] | output | |
AWBURST | [2-1:0] | output | |
AWCACHE | [4-1:0] | output | |
AWID | [4-1:0] | output | |
AWLEN | [4-1:0] | output | |
AWLOCK | [2-1:0] | output | |
AWPROT | [3-1:0] | output | |
AWREADY | input | ||
AWSIZE | [3-1:0] | output | |
AWVALID | output | ||
BID | [4-1:0] | input | |
BREADY | output | ||
BRESP | [2-1:0] | input | |
BVALID | input | ||
RDATA | [axiwidth-1:0] | input | |
RID | [4-1:0] | input | |
RLAST | input | ||
RREADY | output | ||
RRESP | [2-1:0] | input | |
RVALID | input | ||
WDATA | [axiwidth-1:0] | output | |
WID | [4-1:0] | output | |
WLAST | output | ||
WREADY | input | ||
WSTRB | [axiwidth/8-1:0] | output | |
WVALID | output | ||
AXI Slave | |||
ARADDR_S | [32-1:0] | input | |
ARBURST_S | [2-1:0] | input | |
ARCACHE_S | [4-1:0] | input | |
ARID_S | [16-1:0] | input | |
ARLEN_S | [4-1:0] | input | |
ARLOCK_S | [2-1:0] | input | |
ARPROT_S | [3-1:0] | input | |
ARREADY_S | output | ||
ARSIZE_S | [3-1:0] | input | |
ARVALID_S | input | ||
AWADDR_S | [32-1:0] | input | |
AWBURST_S | [2-1:0] | input | |
AWCACHE_S | [4-1:0] | input | |
AWID_S | [16-1:0] | input | |
AWLEN_S | [4-1:0] | input | |
AWLOCK_S | [2-1:0] | input | |
AWPROT_S | [3-1:0] | input | |
AWREADY_S | output | ||
AWSIZE_S | [3-1:0] | input | |
AWVALID_S | input | ||
BID_S | [16-1:0] | output | |
BREADY_S | input | ||
BRESP_S | [2-1:0] | output | |
BVALID_S | output | ||
RDATA_S | [axiwidth-1:0] | output | |
RID_S | [16-1:0] | output | |
RLAST_S | output | ||
RREADY_S | input | ||
RRESP_S | [2-1:0] | output | |
RVALID_S | output | ||
WDATA_S | [axiwidth-1:0] | input | |
WID_S | [16-1:0] | input | |
WLAST_S | input | ||
WREADY_S | output | ||
WSTRB_S | [axiwidth/8-1:0] | input | |
WVALID_S | input | ||
Access Port | |||
DBGEN | input | ||
JTCK | input | ||
JTDI | input | ||
JTDO | output | ||
JTDOEn | output | ||
JTMS | input | ||
JTRST | input | ||
NIDEN | input | ||
PADDR | [32-1:0] | input | |
PBCLK | input | ||
PBCLKEN | input | ||
PENABLE | input | ||
PRDATA | [32-1:0] | output | |
PREADY | output | ||
PRESETn | input | ||
PSEL | input | ||
PSLVERR | output | ||
PWDATA | [32-1:0] | input | |
PWRITE | input | ||
SPIDEN | input | ||
SPNIDEN | input | ||
DRam0 | |||
DRam0Lock0 | output | ||
DRam1 | |||
DRam1Lock0 | output | ||
Debug | |||
BreakIn | input | ||
BreakInAck | output | ||
BreakOut | output | ||
BreakOutAck | input | ||
CrossTriggerIn | input | ||
CrossTriggerInAck | output | ||
CrossTriggerOut | output | ||
CrossTriggerOutAck | input | ||
OCDHaltOnReset | input | ||
XOCDMode | output | ||
EXPSTATE | |||
TIE_EXPSTATE | [31:0] | output | |
Fault Handling | |||
DoubleExceptionError | output | ||
PFatalError | output | ||
PFaultInfo | [32-1:0] | output | |
PFaultInfoValid | output | ||
IMPWIRE | |||
TIE_IMPWIRE | [31:0] | input | |
IRam0 | |||
IRam0LoadStore | output | ||
IRam1 | |||
IRam1LoadStore | output | ||
Interrupt | |||
BInterrupt | [26:0] | input | |
PWaitMode | output | ||
System Signals | |||
BReset | input | ||
CLK | input | ||
DReset | input | ||
PRID | [15:0] | input | |
RunStall | input | ||
StatVectorSel | input | ||
Strobe | input | ||
TMode | input | ||
TModeClkGateOverride | input | ||
TracePort | |||
PDebugData | [31:0] | output | |
PDebugEnable | input | ||
PDebugInbPif | [7:0] | output | |
PDebugInst | [31:0] | output | |
PDebugLS0Stat | [31:0] | output | |
PDebugOutPif | [7:0] | output | |
PDebugPC | [31:0] | output | |
PDebugPrefetchL1Fill | [3:0] | output | |
PDebugPrefetchLookup | [7:0] | output | |
PDebugStatus | [7:0] | output |