S32I.N — Narrow Store 32-bit

Instruction Word

Slot
Inst16a
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x16a - 16 bit(s) 10
S32I.N 1001
t 3210
s 3210
r 3210

Assembler Syntax

S32I.N at, as, 0..60

C Syntax

#include <xtensa/tie/xt_density.h>

extern void XT_S32I_N(int t, int * p, immediate i);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

S32I.N is similar to S32I, but has a 16-bit encoding and supports a smaller range of offset values encoded in the instruction word.

S32I.N is a 32-bit store to memory. It forms a virtual address by adding the contents of address register as and an 4-bit zero-extended constant value encoded in the instruction word shifted left by two. Therefore, the offset can specify multiples of four from zero to 60. The data to be stored is taken from the contents of address register at and written to memory at the physical address.

If the Instruction Memory Access Option is configured, S32I.N is one of only a few memory reference instructions that can access instruction RAM.

If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation or memory reference encounters an error (for example, protection violation or non-existent memory), the processor raises one of several exceptions .

Without the Unaligned Exception Option , the two least significant bits of the address are ignored. A reference to an address that is not 0 mod 4 produces the same result as a reference to the address with the least significant bits cleared. With the Unaligned Exception Options, such an access raises an exception.

Operation

vAddr  AR[s] + (026||imm4||02)
Store32 (vAddr, AR[t])

Exceptions

Memory Store Group (see Memory Store Group:)

Implementation Pipeline

In Out
art Mstage, ars Estage

Protos that use S32I.N

proto S32I.N { in int32 t, in int32 * p, in immediate i }{}{
S32I.N t, p, i + 0;
}