DHWBI — Data Cache Hit Writeback Invalidate

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
DHWBI 0111 01010010
s 3210
imm8 76543210

Assembler Syntax

DHWBI as, 0..1020

C Syntax

#include <xtensa/tie/xt_datacache.h>

extern void XT_DHWBI(const int * s, immediate i);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

DHWBI forces dirty data in the data cache to be written back to memory. If the specified address is not in the data cache, then this instruction has no effect. If the specified address is present and modified in the data cache, the line containing it is written back. After the write-back, if any, the line containing the specified address is invalidated if present. If the specified line has been locked by a DPFL instruction, then no invalidation is done and no exception is raised because of the lock. The line is written back but remains in the cache unmodified and must be unlocked by a DHU or DIU instruction before it can be invalidated. This instruction is useful in the same circumstances as DHWB and before a DMA write to memory or write from another processor to memory. If the line is certain to be completely overwritten by the write, you can use a DHI (as it is faster), but otherwise use a DHWBI.

DHWBI forms a virtual address by adding the contents of address register as and an
8-bit zero-extended constant value encoded in the instruction word shifted left by two. Therefore, the offset can specify multiples of four from zero to 1020. If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation encounters an error (for example, protection violation), the processor raises an exception as if it were loading from the virtual address.

Because the organization of caches is implementation-specific, the operation section below specifies only a call to the implementation's dhitwritebackinval function.

Operation

vAddr ← AR[s] + (022||imm8||02)
(pAddr, attributes, cause) ← ltranslate(vAddr, CRING)
if invalid(attributes) then
	EXCVADDR ← vAddr
	Exception (cause)
else
	dhitwritebackinval(vAddr, pAddr)
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)Memory Group (see Memory Group:)GenExcep(LoadProhibitedCause) if Region Protection Option or MMU Option

Protos that use DHWBI

proto DHWBI { in const int32 * s, in immediate i }{}{
DHWBI s, i + 0;
}