AE_MULSQ32SP16U.L — 32-bit signed x 16-bit unsigned integer
multiply-subtract to 64-bit result without saturation.
Instruction Word
Assembler Syntax
AE_MULSQ32SP16U.L
aed0..15(ae_mul_q0)
,
aed0..15(ae_mul_d0)
,
aed0..15(ae_mul_d1)
C Syntax
#include <xtensa/tie/xt_hifi2.h>extern void AE_MULSQ32SP16U_L(ae_q56s d /*inout*/, ae_q56s d0, ae_p24x2s d1);
Description
AE_MULSQ32SP16U.L is a 32-bit signed x 16-bit unsigned integer multiply-subtract without saturation.
The 32-bit input is from d0[47:16] and the 16-bit unsigned input is from d1[23:8].
The result is accumulated (subtraction) into an AE_DR register, without saturation.
This instruction is provided mainly for compatibility with HiFi 2.
Implementation Pipeline
In
|
Out
|
ae_mul_q0 Wstage , ae_mul_d0 Mstage ,
ae_mul_d1 Mstage
|
ae_mul_q0 Wstage
|
Protos that use AE_MULSQ32SP16U.L
proto
AE_MULSQ32SP16U.H { inout
ae_q56s d, in ae_q56s d0, in ae_p24x2s d1 }{ae_int32x2 tp}{
}
proto
AE_MULZASQ32SP16U.HH { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3,
1;
}
proto
AE_MULZASQ32SP16U.HH_S2
{ out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in
ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1,
1;
AE_SEL16I td3,
d3, d3, 1;
}
proto
AE_MULZASQ32SP16U.LH { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{ae_int32x2 td3}{
AE_SEL16I td3, d3, d3, 1;
}
proto
AE_MULZASQ32SP16U.LL { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{}{
}
proto
AE_MULZASQ32SP16U.LL_S2
{ out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in
ae_int24x2 d3 }{}{
}
proto
AE_MULZSAQ32SP16U.HH { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3,
1;
}
proto
AE_MULZSAQ32SP16U.HH_S2
{ out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in
ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1,
1;
AE_SEL16I td3,
d3, d3, 1;
}
proto
AE_MULZSAQ32SP16U.LH { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{ae_int32x2 td3}{
AE_SEL16I td3, d3, d3, 1;
}
proto
AE_MULZSAQ32SP16U.LL { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{}{
}
proto
AE_MULZSAQ32SP16U.LL_S2
{ out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in
ae_int24x2 d3 }{}{
}
proto
AE_MULZSSQ32SP16U.HH { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3,
1;
}
proto
AE_MULZSSQ32SP16U.HH_S2
{ out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in
ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1,
1;
AE_SEL16I td3,
d3, d3, 1;
}
proto
AE_MULZSSQ32SP16U.LH { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{ae_int32x2 td3}{
AE_SEL16I td3, d3, d3, 1;
}
proto
AE_MULZSSQ32SP16U.LL { out
ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2
d3 }{}{
}
proto
AE_MULZSSQ32SP16U.LL_S2
{ out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in
ae_int24x2 d3 }{}{
}