AE_MULFP16X4RAS — Four-way SIMD 16x16-bit signed fractional (1.15) multiply with 16-bit (1.15) result, asymmetric rounding and saturation.

Instruction Word

Slot
ae2_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_MULFP16X4RAS 1100 0111 1010
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Assembler Syntax

AE_MULFP16X4RAS aed0..15(ae_mul_q0), aed0..15(ae_mul_d0), aed0..15(ae_mul_d1)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_f16x4 AE_MULFP16X4RAS(ae_f16x4 d0, ae_f16x4 d1);

Description

AE_MULFP16X4RAS is a four-way SIMD, 16x16-bit fractional (1.15) multiplication with 16-bit (1.15) result with asymmetric rounding and saturation. This operation is bit exact with the ITU-T mult_r basic operation.

Implementation Pipeline

In Out
AE_OVERFLOW Wstage, ae_mul_d0 Mstage, ae_mul_d1 Mstage AE_OVERFLOW Wstage, ae_mul_q0 Wstage

Protos that use AE_MULFP16X4RAS

proto AE_MULFP16X4RAS { out ae_f16x4 d, in ae_f16x4 d0, in ae_f16x4 d1 }{}{
AE_MULFP16X4RAS d, d0, d1;
}
proto AE_MULFP16X4RAS_scalar { out ae_int16 p, in ae_int16 d0, in ae_int16 d1 }{}{
AE_MULFP16X4RAS p, d0, d1;
}
proto AE_MULFP16X4RAS_vector { out ae_int16x4 p, in ae_int16x4 d0, in ae_int16x4 d1 }{}{
AE_MULFP16X4RAS p, d0, d1;
}