On-chip debug module with JTAG compatible interface
- On-Chip Debug option
- Selected
Cadence recommends that OCD is selected; it is required in
most debugging scenarions on hardware.
OCD support provides access to and control of the software-visible state of the processor
through an IEEE 1149.1 Test Access Port (TAP), also known as JTAG (from the Joint Test
Action Group that originated the standard). Through this TAP, an external debug agent
can:
- Generate an interrupt to put the processor in the debug mode.
- Gain control of the processor upon any debug exception.
- Read and write any software visible register and/or memory location.
- Resume normal mode of operation.
- Communicate with a running system via the DDR register.
The OCD support feature requires an external TAP controller, and
Cadence provides an example TAP controller that implements
OCD support. See the
Xtensa Debug Guide for more information.
Note: Starting with LX5/X10, the OCD option includes two new instructions
LDDR32.P and SDDR32.P to speed up memory download/upload through the Debug Module. This
is a replacement for the Debug Instruction Register Array option of LX4/X9 and earlier
processors.