AE_MULSQ32SP16U.L — 32-bit signed x 16-bit unsigned integer multiply-subtract to 64-bit result without saturation.

Instruction Word

Slot
ae2_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_MULSQ32SP16U.L 1101 0010 0011
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Slot
ae_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_MULSQ32SP16U.L 10101101
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Slot
ae_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_MULSQ32SP16U.L 10101101
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Assembler Syntax

AE_MULSQ32SP16U.L aed0..15(ae_mul_q0), aed0..15(ae_mul_d0), aed0..15(ae_mul_d1)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_MULSQ32SP16U_L(ae_q56s d /*inout*/, ae_q56s d0, ae_p24x2s d1);

Description

AE_MULSQ32SP16U.L is a 32-bit signed x 16-bit unsigned integer multiply-subtract without saturation. The 32-bit input is from d0[47:16] and the 16-bit unsigned input is from d1[23:8]. The result is accumulated (subtraction) into an AE_DR register, without saturation. This instruction is provided mainly for compatibility with HiFi 2.

Implementation Pipeline

In Out
ae_mul_q0 Wstage, ae_mul_d0 Mstage, ae_mul_d1 Mstage ae_mul_q0 Wstage

Protos that use AE_MULSQ32SP16U.L

proto AE_MULSQ32SP16U.H { inout ae_q56s d, in ae_q56s d0, in ae_p24x2s d1 }{ae_int32x2 tp}{
AE_SEL16I tp, d1, d1, 1;
AE_MULSQ32SP16U.L d, d0, tp;
}
proto AE_MULSQ32SP16U.L { inout ae_q56s d, in ae_q56s d0, in ae_p24x2s d1 }{}{
AE_MULSQ32SP16U.L d, d0, d1;
}
proto AE_MULZASQ32SP16U.HH { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3, 1;
AE_MULQ32SP16U.L d, d0, td1;
AE_MULSQ32SP16U.L d, d2, td3;
}
proto AE_MULZASQ32SP16U.HH_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3, 1;
AE_MULQ32SP16U.L d, d0, td1;
AE_MULSQ32SP16U.L d, d2, td3;
}
proto AE_MULZASQ32SP16U.LH { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td3}{
AE_SEL16I td3, d3, d3, 1;
AE_MULQ32SP16U.L d, d0, d1;
AE_MULSQ32SP16U.L d, d2, td3;
}
proto AE_MULZASQ32SP16U.LH_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td3}{
AE_SEL16I td3, d3, d3, 1;
AE_MULQ32SP16U.L d, d0, d1;
AE_MULSQ32SP16U.L d, d2, td3;
}
proto AE_MULZASQ32SP16U.LL { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{}{
AE_MULQ32SP16U.L d, d0, d1;
AE_MULSQ32SP16U.L d, d2, d3;
}
proto AE_MULZASQ32SP16U.LL_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{}{
AE_MULQ32SP16U.L d, d0, d1;
AE_MULSQ32SP16U.L d, d2, d3;
}
proto AE_MULZSAQ32SP16U.HH { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3, 1;
AE_MULQ32SP16U.L d, d2, td3;
AE_MULSQ32SP16U.L d, d0, td1;
}
proto AE_MULZSAQ32SP16U.HH_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3, 1;
AE_MULQ32SP16U.L d, d2, td3;
AE_MULSQ32SP16U.L d, d0, td1;
}
proto AE_MULZSAQ32SP16U.LH { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td3}{
AE_SEL16I td3, d3, d3, 1;
AE_MULQ32SP16U.L d, d2, td3;
AE_MULSQ32SP16U.L d, d0, d1;
}
proto AE_MULZSAQ32SP16U.LH_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td3}{
AE_SEL16I td3, d3, d3, 1;
AE_MULQ32SP16U.L d, d2, td3;
AE_MULSQ32SP16U.L d, d0, d1;
}
proto AE_MULZSAQ32SP16U.LL { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{}{
AE_MULQ32SP16U.L d, d2, d3;
AE_MULSQ32SP16U.L d, d0, d1;
}
proto AE_MULZSAQ32SP16U.LL_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{}{
AE_MULQ32SP16U.L d, d2, d3;
AE_MULSQ32SP16U.L d, d0, d1;
}
proto AE_MULZSSQ32SP16U.HH { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_MOVI d, 0;
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3, 1;
AE_MULSQ32SP16U.L d, d0, td1;
AE_MULSQ32SP16U.L d, d2, td3;
}
proto AE_MULZSSQ32SP16U.HH_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td1, ae_int32x2 td3}{
AE_MOVI d, 0;
AE_SEL16I td1, d1, d1, 1;
AE_SEL16I td3, d3, d3, 1;
AE_MULSQ32SP16U.L d, d0, td1;
AE_MULSQ32SP16U.L d, d2, td3;
}
proto AE_MULZSSQ32SP16U.LH { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td3}{
AE_MOVI d, 0;
AE_SEL16I td3, d3, d3, 1;
AE_MULSQ32SP16U.L d, d0, d1;
AE_MULSQ32SP16U.L d, d2, td3;
}
proto AE_MULZSSQ32SP16U.LH_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{ae_int32x2 td3}{
AE_MOVI d, 0;
AE_SEL16I td3, d3, d3, 1;
AE_MULSQ32SP16U.L d, d0, d1;
AE_MULSQ32SP16U.L d, d2, td3;
}
proto AE_MULZSSQ32SP16U.LL { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{}{
AE_MOVI d, 0;
AE_MULSQ32SP16U.L d, d0, d1;
AE_MULSQ32SP16U.L d, d2, d3;
}
proto AE_MULZSSQ32SP16U.LL_S2 { out ae_q56s d, in ae_q56s d0, in ae_int24x2 d1, in ae_q56s d2, in ae_int24x2 d3 }{}{
AE_MOVI d, 0;
AE_MULSQ32SP16U.L d, d0, d1;
AE_MULSQ32SP16U.L d, d2, d3;
}