AE_MULARFQ32SP24S.L — 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation.

Instruction Word

Slot
ae2_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_MULARFQ32SP24S.L 1100 0110 0100
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Assembler Syntax

AE_MULARFQ32SP24S.L aed0..15(ae_mul_q0), aed0..15(ae_mul_d0), aed0..15(ae_mul_d1)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_MULARFQ32SP24S_L(ae_q56s d /*inout*/, ae_q56s d0, ae_p24x2s d1);

Description

AE_MULARFQ32SP24S.L is a 32-bit signed x 24-bit signed fraction (1.31 x 1.23) multiply to 34-bit (3.31) output without saturation. Fixed-point values represent the range [-1.0 ... 1.0). The 32-bit input is from d0[47:16], and the 24-bit input is from d1[23:0]. The 56-bit (2.54) product is asymmetrically rounded toward +infinity, truncated, and sign-extended to 34-bits (3.31). The resulting product is then added to q[49:16], i.e. the 17.47 fraction in q is truncated to a 3.31 fraction. The final 34-bit (3.31) result is sign-extended and padded with zeros to a 64-bit (17.47) fraction. This instruction is provided mainly for compatibility with HiFi EP.

Implementation Pipeline

In Out
ae_mul_q0 Wstage, ae_mul_d0 Mstage, ae_mul_d1 Mstage ae_mul_q0 Wstage

Protos that use AE_MULARFQ32SP24S.L

proto AE_MULARFQ32SP24S.L { inout ae_q56s d, in ae_q56s d0, in ae_p24x2s d1 }{}{
AE_MULARFQ32SP24S.L d, d0, d1;
}