AE_S24RA64S.XP — Round asymmetrically a 17.47-bit fraction to 1.23-bits and store

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_S24RA64S.XP 1000000000010001 0011
ae_fld_ls_v1 3210
s 3210
t 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_S24RA64S.XP 10001110
ae_fld_ls_v1 3210
s 3210
t 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_S24RA64S.XP 11011101 0100
ae_fld_ls_v1 3210
s 3210
t 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_S24RA64S.XP 10001110
ae_fld_ls_v1 3210
s 3210
t 3210

Assembler Syntax

AE_S24RA64S.XP aed0..15(ae_ls_v1), a0..15(ars), a0..15(art)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_S24RA64S_XP(ae_f64 d, ae_f24 * a /*inout*/, int off);

Description

AE_S24RA64S.XP round asymmetrically, saturate the 17.47-bit value from AE_DR register d to a 1.23-bit value and store the result to memory in the high 24-bits of a 32-bit bundle. In case of saturation, state AE_OVERFLOW is set to 1. This operation is equivalent to an AE_ROUNDSP24Q48ASYM followed by a store.

The store forms a virtual address using the address register.

This instruction also post-increments the address register by the contents of the index register.

Implementation Pipeline

In Out
AE_OVERFLOW Wstage, ae_ls_v1 Mstage, ars Estage, art Estage AE_OVERFLOW Wstage, ars Estage

Protos that use AE_S24RA64S.XP

proto AE_S24RA64S.XP { in ae_f64 d, inout ae_f24 * a, in int32 off }{}{
AE_S24RA64S.XP d, a, off;
}