Cadence supports the use of one or two load/store units. Dual load/store units potentially allow your application to issue two load/stores every cycle. The processor will only take advantage of the second load/store unit if you have custom FLIX TIE instructions with loads or stores in multiple slots, or if you utilize the dual load/store variant of a ConnX processor, which come pre-built with two load/store units.
Data caches on dual load/store configurations must be at least 2-way set associative and must have at least two banks. The memory is banked so that successive data memory access width size references go to different banks. The processor can not issue multiple memory references to the same bank in the same cycle. The compiler will try to compile code to avoid bank conflicts.
Local data memory can be optionally banked. In addition, the user can select the connection box option. With this option, if two memory references go to different local data memories, the processor will not stall. If two memory references go to the same bank of the same local data memory, the connection box will stall the processor for one cycle. With no banking and no connection box, dual load/store configurations require the use of dual-ported memory.