ADDI — Add Immediate

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
ADDI 1000000000000100
t 3210
s 3210
imm8 7654 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
ADDI 0010
t 3210
s 3210
imm8 7654 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
ADDI 1100 0010
t 3210
s 3210
imm8 76543210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
ADDI 0010
t 3210
s 3210
imm8 7654 3210

Slot
ae_minislot2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_mini0 - 64 bit(s)01000000000000000000000 1110
ADDI 0 00
t 3210
s 3210
imm8 3210 7654

Assembler Syntax

ADDI at, as, -128..127

C Syntax

#include <xtensa/tie/xt_core.h>

extern int XT_ADDI(int s, immediate i);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

ADDI calculates the two's complement 32-bit sum of address register as and a constant encoded in the imm8 field. The low 32 bits of the sum are written to address register at. Arithmetic overflow is not detected.

The immediate operand encoded in the instruction can range from -128 to 127. It is decoded by sign-extending imm8.

ADDI is a 24-bit instruction. The ADDI.N density-option instruction performs a similar operation (the immediate operand has less range) in a 16-bit encoding.

Operation

AR[t] ← AR[s] + (imm8724||imm8)

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
ars Estage art Estage

Protos that use ADDI

proto ADDI { out int32 r, in int32 s, in immediate i }{}{
ADDI r, s, i + 0;
}
proto AE_LP24.IU { out ae_p24x2s d, inout const ae_p24s * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_L32.I d, a, 0;
}
proto AE_LP24F.IU { out ae_p24x2s d, inout const ae_p24f * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_L32F24.I d, a, 0;
}
proto AE_LP24X2.IU { out ae_p24x2s d, inout const ae_p24x2s * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_L32X2.I d, a, 0;
}
proto AE_LP24X2F.IU { out ae_p24x2s d, inout const ae_p24x2f * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_L32X2F24.I d, a, 0;
}
proto AE_LQ56.IU { out ae_q56s d, inout const ae_q56s * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_L64.I d, a, 0;
}
proto AE_NSAQ56S { out int32 a, in ae_q56s d0 }{int32 t}{
AE_NSA64 t, d0;
ADDI a, t, -8;
}
proto AE_SP24F.L.IU { in ae_p24x2s d, inout ae_p24f * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_S32F24.L.I d, a, 0;
}
proto AE_SP24S.L.IU { in ae_p24x2s d, inout ae_p24s * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_S32.L.I d, a, 0;
}
proto AE_SP24X2F.IU { in ae_p24x2s d, inout ae_p24x2f * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_S32X2F24.I d, a, 0;
}
proto AE_SP24X2S.IU { in ae_p24x2s d, inout ae_p24x2s * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_S32X2.I d, a, 0;
}
proto AE_SQ56S.IU { in ae_q56s d, inout ae_q56s * a, in immediate off }{}{
ADDI a, a, off + 0;
AE_S64.I d, a, 0;
}
proto ae_int32x4_load_post_update_negative { out ae_int32x4 v, inout const ae_int32x4 * a }{}{
AE_L64.I v->d1, a, 8;
AE_L64.I v->d0, a, 0;
ADDI a, a, -16;
}
proto ae_int32x4_load_post_update_positive { out ae_int32x4 v, inout const ae_int32x4 * a, in immediate off }{}{
AE_L32X2.I v->d1, a, 0;
AE_L32X2.I v->d0, a, 8;
ADDI a, a, off + 0;
}
proto ae_int32x4_store_post_update_negative { in ae_int32x4 v, inout ae_int32x4 * a }{}{
AE_S64.I v->d1, a, 8;
AE_S64.I v->d0, a, 0;
ADDI a, a, -16;
}
proto ae_int32x4_store_post_update_positive { in ae_int32x4 v, inout ae_int32x4 * a, in immediate off }{}{
AE_S32X2.I v->d1, a, 0;
AE_S32X2.I v->d0, a, 8;
ADDI a, a, off + 0;
}