Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
WDTLB | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||
t | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 |
WDTLB a
t
, as
extern void XT_WDTLB(unsigned art, unsigned ars);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
WDTLB
uses the contents of address register as
to specify a data TLB entry and writes the contents of address register at
into that entry. See for information on the address and result register formats for specific memory protection and translation options. The point at which the data TLB write is effected is implementation-specific. Any translation that would be affected by this write before the execution of a DSYNC
instruction is therefore undefined.
WDTLB
is a privileged instruction.
if CRING != 0 then Exception (PrivilegedCause) else (vpn, ei, wi) ← SplitDataTLBEntrySpec(AR[s]) (ppn, sr, ring, ca) ← SplitDataEntry(wi, AR[t]) DataTLB[wi][ei].ASID ← ASID(ring) DataTLB[wi][ei].VPN ← vpn DataTLB[wi][ei].PPN ← ppn DataTLB[wi][ei].SR ← sr DataTLB[wi][ei].CA ← ca endif
In | Out |
---|---|
art Wstage , ars Estage
|