MULA.DD.LL — Signed Multiply/Accumulate

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
MULA.DD.LL 001010000 0000000 000100
x 0
y 0

Assembler Syntax

MULA.DD.* mx, my Where * expands as follows:

MULA.DD.LL - for (half=0)

MULA.DD.HL - for (half=1)

MULA.DD.LH - for (half=2)

MULA.DD.HH - for (half=3)


C Syntax

#include <xtensa/tie/xt_MAC16.h>

extern void XT_MULA_DD_LL(immediate mx, immediate my);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

MULA.DD.* performs a two's complement multiply of half of each of the MAC16 registers mx and my, producing a 32-bit result. The result is sign-extended to 40 bits and added to the contents of the MAC16 accumulator. The mx operand can designate either MAC16 register m0 or m1. The my operand can designate either MAC16 register m2 or m3.

Operation

m1 ← if half0 then MR[0||x]31..16 else MR[0||x]15..0
m2 ← if half1 then MR[1||y]31..16 else MR[1||y]15..0
ACC ← ACC + (m11524||m1) \* (m21524||m2)

Exceptions

EveryInst Group (see EveryInst Group:)

Implementation Pipeline

In Out
ACC Mstage, mx Estage, my Estage ACC Mstage

Protos that use MULA.DD.LL

proto MULA.DD.LL { in immediate mx, in immediate my }{}{
MULA.DD.LL mx + 0, my + 0;
}