LICT — Load Instruction Cache Tag

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
LICT 111100010000 0000
t 3210
s 3210

Assembler Syntax

LICT at, as

C Syntax

#include <xtensa/tie/xt_instcache.h>

extern int XT_LICT(int s);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

LICT is not part of the Xtensa Instruction Set Architecture, but is instead specific to an implementation. That is, it may not exist in all implementations of the Xtensa ISA and its exact method of addressing the cache may depend on the implementation.

LICT is intended for reading the RAM array that implements the instruction cache tags as part of manufacturing test.

LICT uses the contents of address register as to select a line in the instruction cache, reads the tag associated with this line, and writes the result to address register at. The value written to at is described under Cache Tag Format in .

LICT is a privileged instruction.

Operation

if CRING != 0 then
	Exception (PrivilegedCause)
else
	index ← AR[s]x-1..z-2
	AR[t] ← InstCacheTag[index] // see Implementation Notes below
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)GenExcep(PrivilegedCause) if Exception Option

Protos that use LICT

proto LICT { out int32 t, in int32 s }{}{
LICT t, s;
}