AE_ROUNDSP16F24SYM — Round symmetrically and saturate two 9.23-bit fractions to 1.15-bits

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_ROUNDSP16F24SYM 1000000000011000 1111 0010
ae_fld_arth_v 3210
ae_fld_arth_v0 3210

Slot
ae_slot2_1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_ROUNDSP16F24SYM 1001001 0001
ae_fld_arth_v 3210
ae_fld_arth_v0 3210

Assembler Syntax

AE_ROUNDSP16F24SYM aed0..15(ae_arth_v), aed0..15(ae_arth_v0)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_f32x2 AE_ROUNDSP16F24SYM(ae_f32x2 d0);

Description

AE_ROUNDSP16F24SYM Round symmetrically (away from 0), saturate each 9.23-bit element of AE_DR register d0 to a 1.15-bit value, sign-extend it and store the results as 9.23-bit values in the two elements of AE_DR register d. In case of saturation, state AE_OVERFLOW is set to 1.

Implementation Pipeline

In Out
AE_OVERFLOW Wstage, ae_arth_v0 Mstage AE_OVERFLOW Wstage, ae_arth_v Mstage

Protos that use AE_ROUNDSP16F24SYM

proto AE_ROUNDSP16F24SYM { out ae_f32x2 d, in ae_f32x2 d0 }{}{
AE_ROUNDSP16F24SYM d, d0;
}
proto AE_ROUNDSP16SYM { out ae_p24x2s d, in ae_p24x2s d0 }{}{
AE_ROUNDSP16F24SYM d, d0;
}