PDTLB — Probe Data TLB

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
PDTLB 010100001101 0000
t 3210
s 3210

Assembler Syntax

PDTLB at, as

C Syntax

#include <xtensa/tie/xt_mmu.h>

extern unsigned XT_PDTLB(unsigned ars);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

PDTLB searches the data TLB for an entry that translates the virtual address in address register as and writes the way and index of that entry to address register at. If no entry matches, zero is written to the hit bit of at. The value written to at is implementation-specific, but in all implementations a value with the hit bit set is suitable as an input to the IDTLB or WDTLB instructions. See for information on the result register formats for specific memory protection and translation options.

PDTLB is a privileged instruction.

Operation

if CRING != 0 then
	Exception (PrivilegedCause)
else
	(match, vpn, ei, wi) ← ProbeDataTLB(AR[s])
	if match > 1 then
		EXCVADDR ← AR[s]
		Exception (LoadStoreTLBMultiHit)
	else
		AR[t] ← PackDataTLBEntrySpec(match, vpn, ei, wi)
	endif
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)GenExcep(LoadStoreTLBMultiHitCause) if Region Protection Option or MMU OptionGenExcep(PrivilegedCause) if Exception Option

Protos that use PDTLB

proto PDTLB { out uint32 art, in uint32 ars }{}{
PDTLB art, ars;
}