Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CALL0 | 0 | 0 | 0 | 1 | 0 | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
offset | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CALL0 label
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
CALL0
calls subroutines without using register windows. The return address is placed in a0
, and the processor then branches to the target address. The return address is the address of the CALL0
instruction plus three.
The target instruction address must be 32-bit aligned. This allows CALL0
to have a larger effective range (-524284 to 524288 bytes). The target instruction address of the call is given by the address of the CALL0
instruction with the least significant two bits set to zero plus the sign-extended 18-bit offset
field of the instruction shifted by two, plus four.
The RET
and RET.N
instructions are used to return from a subroutine called by CALL0
.
See the CALLX0
instruction CALLX0 as for calling routines where the target address is given by the contents of a register.
To call using the register window mechanism, see the CALL4
, CALL8
, and CALL12
instructions.
AR[0] ← nextPC nextPC ← (PC31..2 + (offset1712||offset) + 1)||00