AE_LA24NEG.PC — Priming load alignment register

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_LA24NEG.PC 1000000000011010 0011 0001 1 0
ae_fld_ls_uu 10
s 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_LA24NEG.PC 11011100 0010 1 0
ae_fld_ls_uu 10
s 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_LA24NEG.PC 11011100 0010 1 0
ae_fld_ls_uu 10
s 3210

Assembler Syntax

AE_LA24NEG.PC u0..3(ae_ls_uu), a0..15(ars)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_LA24NEG_PC(ae_valign uu /*out*/, const void * a /*inout*/);

Description

AE_LA24NEG.PC loads the alignment register with data from the address register. This instruction is used to prime unaligned access streams for the AE_LA24.RIC instruction.

Implementation Pipeline

In Out
AE_CBEGIN0 Estage, AE_CEND0 Estage, ars Estage ae_ls_uu Wstage, ars Estage

Protos that use AE_LA24NEG.PC

proto AE_LA24NEG.PC { out ae_valign uu, inout const void * a }{}{
AE_LA24NEG.PC uu, a;
}