AND — Bitwise Logical And

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AND 00010000 0000
r 3210
s 3210
t 3210

Assembler Syntax

AND ar, as, at

C Syntax

#include <xtensa/tie/xt_core.h>

extern int XT_AND(int s, int t);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

AND calculates the bitwise logical and of address registers as and at. The result is written to address register ar.

Operation

AR[r] ← AR[s] and AR[t]

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
ars Estage, art Estage arr Estage

Protos that use AND

proto AE_INT32X2_AND_rfini { out int32 a, in ae_int32x2 d }{int32 lo, int32 hi}{
AE_MOVAD32.L lo, d;
AE_MOVAD32.H hi, d;
AND a, hi, lo;
}
proto AND { out int32 r, in int32 s, in int32 t }{}{
AND r, s, t;
}