Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
XSR.EPC1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||
t | 3 | 2 | 1 | 0 |
XSR.EPC1
a0..15(art)
extern void XT_XSR_EPC1(unsigned t /*inout*/);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
XSR.*
simultaneously reads and writes the special registers that are described in Processor Control Instructions
. See Special Registers for more detailed information on the operation of this instruction for each Special Register.
The contents of address register at
and the Special Register designated by the immediate in the 8-bit sr
field of the instruction word are both read. The read address register value is then written to the Special Register, and the read Special Register value is written to at
. The name of the Special Register is used in place of the '*' in the assembler syntax above and the translation is made to the 8-bit sr
field by the assembler.
XSR
is an assembler macro for XSR.*
, which provides compatibility with the older versions of the instruction containing either the name or the number of the Special Register.
The point at which XSR.*
to certain registers affects subsequent instructions is not always defined (SAR
and ACC
are exceptions). In these cases, the Special Register Tables in Special Registers explain how to ensure the effects are seen by a particular point in the instruction stream (typically involving the use of one of the ISYNC
, RSYNC
, ESYNC
, or DSYNC
instructions). An XSR.*
followed by an RSR.*
to the same register should be separated with an ESYNC
to guarantee the value written is read back. An XSR.PS
followed by RSIL
also requires an ESYNC
. In general, the restrictions on XSR.*
include the union of the restrictions of the corresponding RSR.*
and WSR.*
.
XSR.*
with Special Register numbers >=
64 is privileged. An XSR.*
for an unconfigured register generally will raise an illegal instruction exception.
sr ← if msbFirst then s||r else r||s if sr >= 64 and CRING != 0 then Exception (PrivilegedCause) else t0 ← AR[t] t1 ← see RSR frame of the Tables in Special Registers see WSR frame of the Tables in Special Registers ← t0 AR[t] ← t1 endif
1.WindowOverflow4
, WindowOverflow8
, or WindowOverflow12
.
2.WindowUnderflow4
, WindowUnderflow8
, or WindowUnderflow12
.