Group Signal Names Bit-index Direction
AXI Master
ARADDR[32-1:0]output
ARBURST[2-1:0]output
ARCACHE[4-1:0]output
ARID[4-1:0]output
ARLEN[4-1:0]output
ARLOCK[2-1:0]output
ARPROT[3-1:0]output
ARREADYinput
ARSIZE[3-1:0]output
ARVALIDoutput
AWADDR[32-1:0]output
AWBURST[2-1:0]output
AWCACHE[4-1:0]output
AWID[4-1:0]output
AWLEN[4-1:0]output
AWLOCK[2-1:0]output
AWPROT[3-1:0]output
AWREADYinput
AWSIZE[3-1:0]output
AWVALIDoutput
BID[4-1:0]input
BREADYoutput
BRESP[2-1:0]input
BVALIDinput
RDATA[axiwidth-1:0]input
RID[4-1:0]input
RLASTinput
RREADYoutput
RRESP[2-1:0]input
RVALIDinput
WDATA[axiwidth-1:0]output
WID[4-1:0]output
WLASToutput
WREADYinput
WSTRB[axiwidth/8-1:0]output
WVALIDoutput
AXI Slave
ARADDR_S[32-1:0]input
ARBURST_S[2-1:0]input
ARCACHE_S[4-1:0]input
ARID_S[16-1:0]input
ARLEN_S[4-1:0]input
ARLOCK_S[2-1:0]input
ARPROT_S[3-1:0]input
ARREADY_Soutput
ARSIZE_S[3-1:0]input
ARVALID_Sinput
AWADDR_S[32-1:0]input
AWBURST_S[2-1:0]input
AWCACHE_S[4-1:0]input
AWID_S[16-1:0]input
AWLEN_S[4-1:0]input
AWLOCK_S[2-1:0]input
AWPROT_S[3-1:0]input
AWREADY_Soutput
AWSIZE_S[3-1:0]input
AWVALID_Sinput
BID_S[16-1:0]output
BREADY_Sinput
BRESP_S[2-1:0]output
BVALID_Soutput
RDATA_S[axiwidth-1:0]output
RID_S[16-1:0]output
RLAST_Soutput
RREADY_Sinput
RRESP_S[2-1:0]output
RVALID_Soutput
WDATA_S[axiwidth-1:0]input
WID_S[16-1:0]input
WLAST_Sinput
WREADY_Soutput
WSTRB_S[axiwidth/8-1:0]input
WVALID_Sinput
Access Port
DBGENinput
JTCKinput
JTDIinput
JTDOoutput
JTDOEnoutput
JTMSinput
JTRSTinput
NIDENinput
PADDR[32-1:0]input
PBCLKinput
PBCLKENinput
PENABLEinput
PRDATA[32-1:0]output
PREADYoutput
PRESETninput
PSELinput
PSLVERRoutput
PWDATA[32-1:0]input
PWRITEinput
SPIDENinput
SPNIDENinput
DRam0
DRam0Lock0output
DRam1
DRam1Lock0output
Debug
BreakIninput
BreakInAckoutput
BreakOutoutput
BreakOutAckinput
CrossTriggerIninput
CrossTriggerInAckoutput
CrossTriggerOutoutput
CrossTriggerOutAckinput
OCDHaltOnResetinput
XOCDModeoutput
EXPSTATE
TIE_EXPSTATE[31:0]output
Fault Handling
DoubleExceptionErroroutput
PFatalErroroutput
PFaultInfo[32-1:0]output
PFaultInfoValidoutput
IMPWIRE
TIE_IMPWIRE[31:0]input
IRam0
IRam0LoadStoreoutput
IRam1
IRam1LoadStoreoutput
Interrupt
BInterrupt[26:0]input
PWaitModeoutput
System Signals
BResetinput
CLKinput
DResetinput
PRID[15:0]input
RunStallinput
StatVectorSelinput
Strobeinput
TModeinput
TModeClkGateOverrideinput
TracePort
PDebugData[31:0]output
PDebugEnableinput
PDebugInbPif[7:0]output
PDebugInst[31:0]output
PDebugLS0Stat[31:0]output
PDebugOutPif[7:0]output
PDebugPC[31:0]output
PDebugPrefetchL1Fill[3:0]output
PDebugPrefetchLookup[7:0]output
PDebugStatus[7:0]output