Creates a scan-enabled design that supports scan insertion
- Full Scan option
- Selected
When a core is configured with "Full scan" option, a TMode pin and a TModeClkGateOverride
pin are added to the RTL at top-level.
TMode is expected to be asserted during entire scan testing and it enables testability in
4 areas:
- It enables async. reset pin to bypass synchronization logic so tester can directly
control the reset of flops during entire scan test.
- It inverts the clock(the JTAG clk) of the falling-edge triggered flip-flop in JTAG
logic during testing so that there are only rising-edge triggered flops (i.e no
falling-edge edge triggered flops) in the design during entire scan test.
- It overrides the enable pin of latches in latch-based register files so that latches
are transparent (only applicable to older Xtensa cores with latch-based register
file) during capture phase of scan test.
- It bypasses the reset that is generated by test-logic-reset state of the TAP, to use
JTRST instead, if JTAG TAP is configured. This allows direct control (instead of
going through sequential logic) of the reset pin of flops that uses FSM-generated
reset.
The TModeClkGateOverride is typically only asserted during shift phase of scan test and
it enables testability as follows: It overrides the clock-gating enable pin of
clock-gating cell. I.e. it disables clock-gating so clock is always turned on during
shift phase of scan test.