AE_SLAS24 — 2-way bidirectional 24-bit shift left arithmetic by shift amount register

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_SLAS24 1000000000011001 10110000
ae_fld_shift_d 3210
ae_fld_shift_d0 3210

Slot
ae_slot2_0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_SLAS2411101010 0000
ae_fld_shift_d 3210
ae_fld_shift_d0 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_SLAS24 00100100 1011 0100
ae_fld_shift_d 3210
ae_fld_shift_d0 3210

Assembler Syntax

AE_SLAS24 aed0..15(ae_shift_d), aed0..15(ae_shift_d0)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_int24x2 AE_SLAS24(ae_int24x2 d0);

Description

AE_SLAS24 is a two-way bidirectional arithmetic left shift of bits [23:0] of AE_DR register d0 by shift amount register AE_SAR, with result signed extended to 32-bits and placed in d.

Implementation Pipeline

In Out
AE_SAR Estage, ae_shift_d0 Mstage ae_shift_d Mstage

Protos that use AE_SLAS24

proto AE_SLAS24 { out ae_int24x2 d, in ae_int24x2 d0 }{}{
AE_SLAS24 d, d0;
}
proto AE_SLLSP24 { out ae_p24x2s d, in ae_p24x2s d0 }{}{
AE_SLAS24 d, d0;
}