AE_MULFP24X2RA — Two-way SIMD 24x24-bit signed fractional (1.23) multiply with asymmetric rounding down to 9.23-bits.

Instruction Word

Slot
ae2_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_MULFP24X2RA 1100 1111 1011
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Slot
ae_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_MULFP24X2RA 01110001
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Slot
ae_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_MULFP24X2RA 01110001
ae_fld_mul_q0 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210

Assembler Syntax

AE_MULFP24X2RA aed0..15(ae_mul_q0), aed0..15(ae_mul_d0), aed0..15(ae_mul_d1)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_f32x2 AE_MULFP24X2RA(ae_f24x2 d0, ae_f24x2 d1);

Description

AE_MULFP24X2RA is a two-way SIMD, 24x24-bit fractional (1.23) multiplication rounded down asymmetrically to 9.23-bits with no saturation.

Implementation Pipeline

In Out
ae_mul_d0 Mstage, ae_mul_d1 Mstage ae_mul_q0 Wstage

Protos that use AE_MULFP24X2RA

proto AE_F24X2_MULF_F24X2 { out ae_f32x2 d, in ae_f24x2 d0, in ae_f24x2 d1 }{}{
AE_MULFP24X2RA d, d0, d1;
}
proto AE_F24_MULF_F24 { out ae_f32 d, in ae_f24 d0, in ae_f24 d1 }{}{
AE_MULFP24X2RA d, d0, d1;
}
proto AE_MULFP24X2RA { out ae_f32x2 d, in ae_f24x2 d0, in ae_f24x2 d1 }{}{
AE_MULFP24X2RA d, d0, d1;
}