All Instructions

Alphabetic by mnemonic

Mnemonic Synopsis
ABS Absolute Value
ADD Add
ADD.N Narrow Add
ADDI Add Immediate
ADDI.N Narrow Add Immediate
ADDMI Add Immediate with Shift by 8
ADDX2 Add with Shift by 1
ADDX4 Add with Shift by 2
ADDX8 Add with Shift by 3
AE_ABS16S 4-way 16-bit absolute value with saturation
AE_ABS24S 2-way 24-bit absolute value with saturation
AE_ABS32 2-way 32-bit absolute value
AE_ABS32S 2-way 32-bit absolute value with saturation
AE_ABS64 64-bit absolute value
AE_ABS64S 64-bit absolute value with saturation
AE_ABSSQ56S 56-bit absolute value with saturation
AE_ADD16 4-way 16-bit addition
AE_ADD16S 4-way 16-bit signed, saturating addition
AE_ADD24S 2-way 24-bit signed, saturating addition
AE_ADD32 2-way 32-bit addition
AE_ADD32S 2-way 32-bit signed, saturating addition
AE_ADD32_HL_LH Generalized Reduction Add
AE_ADD64 64-bit addition
AE_ADD64S 64-bit signed addition with saturation
AE_ADDBRBA32 32-bit add to a bit-reversed base
AE_ADDSQ56S 56-bit signed addition with saturation
AE_ADDSUB32 2-way 32-bit addition/subtraction
AE_ADDSUB32S 2-way 32-bit signed, saturating addition/subtraction
AE_AND bitwise AND on two AE_DR register inputs
AE_CVT32X2F16.10 ITU intrinsic L_deposit_h
AE_CVT32X2F16.32 ITU intrinsic L_deposit_h
AE_CVT48A32 Convert a 1.31-bit fraction to 17.47-bits
AE_CVT64A32 Convert a 1.31-bit fraction to 1.63-bits
AE_CVT64F32.H Convert a 1.31-bit fraction to 1.63-bits
AE_CVTA32F24S.H Convert a 9.23-bit fraction to 1.31-bits
AE_CVTA32F24S.L Convert a 9.23-bit fraction to 1.31-bits
AE_CVTP24A16X2.HH Convert 16-bits to 24-bits
AE_CVTP24A16X2.HL Convert 16-bits to 24-bits
AE_CVTP24A16X2.LH Convert 16-bits to 24-bits
AE_CVTP24A16X2.LL Convert 16-bits to 24-bits
AE_CVTQ56A32S Convert a 1.31-bit fraction to 9.55-bits
AE_CVTQ56P32S.H Convert a 1.31-bit fraction to 9.55-bits
AE_CVTQ56P32S.L Convert a 1.31-bit fraction to 9.55-bits
AE_DB discard bits from the head of the input bit stream (count in AR register)
AE_DB.IC discard bits from the head of the input bit stream (count in AR register)
AE_DB.IP discard bits from the head of the input bit stream (count in AR register)
AE_DBI discard bits from the head of the input bit stream (count in immediate)
AE_DBI.IC discard bits from the head of the input bit stream (count in immediate)
AE_DBI.IP discard bits from the head of the input bit stream (count in immediate)
AE_DIV64D32.H 1-bit divide-step operation
AE_DIV64D32.L 1-bit divide-step operation
AE_EQ16 4-way 16-bit equality comparison
AE_EQ32 2-way 32-bit equality comparison
AE_EQ64 64-bit signed equality
AE_L16.I Load a 16-bit value and replicates into the AE_DR register
AE_L16.IP Load a 16-bit value and replicates into the AE_DR register
AE_L16.X Load a 16-bit value and replicates into the AE_DR register
AE_L16.XC Load a 16-bit value and replicates into the AE_DR register
AE_L16.XP Load a 16-bit value and replicates into the AE_DR register
AE_L16M.I Load a 16-bit fractional values and place into the middle of each half of an AE_DR register
AE_L16M.IU Load a 16-bit fractional values and place into the middle of each half of an AE_DR register
AE_L16M.X Load a 16-bit fractional values and place into the middle of each half of an AE_DR register
AE_L16M.XC Load a 16-bit fractional values and place into the middle of each half of an AE_DR register
AE_L16M.XU Load a 16-bit fractional values and place into the middle of each half of an AE_DR register
AE_L16X2M.I Load a pair of 16-bit fractional values and place into the middle of two havles of an AE_DR register
AE_L16X2M.IU Load a pair of 16-bit fractional values and place into the middle of two havles of an AE_DR register
AE_L16X2M.X Load a pair of 16-bit fractional values and place into the middle of two havles of an AE_DR register
AE_L16X2M.XC Load a pair of 16-bit fractional values and place into the middle of two havles of an AE_DR register
AE_L16X2M.XU Load a pair of 16-bit fractional values and place into the middle of two havles of an AE_DR register
AE_L16X4.I Load four 16-bit values into the AE_DR register
AE_L16X4.IP Load four 16-bit values into the AE_DR register
AE_L16X4.RIC Load four 16-bit values into the AE_DR register
AE_L16X4.RIP Load four 16-bit values into the AE_DR register
AE_L16X4.X Load four 16-bit values into the AE_DR register
AE_L16X4.XC Load four 16-bit values into the AE_DR register
AE_L16X4.XP Load four 16-bit values into the AE_DR register
AE_L32.I Load a 32-bit value and replicate into the AE_DR register
AE_L32.IP Load a 32-bit value and replicate into the AE_DR register
AE_L32.X Load a 32-bit value and replicate into the AE_DR register
AE_L32.XC Load a 32-bit value and replicate into the AE_DR register
AE_L32.XP Load a 32-bit value and replicate into the AE_DR register
AE_L32F24.I Load a 24-bit fractional value and replicate into the AE_DR register
AE_L32F24.IP Load a 24-bit fractional value and replicate into the AE_DR register
AE_L32F24.X Load a 24-bit fractional value and replicate into the AE_DR register
AE_L32F24.XC Load a 24-bit fractional value and replicate into the AE_DR register
AE_L32F24.XP Load a 24-bit fractional value and replicate into the AE_DR register
AE_L32M.I Load a 32-bit fractional values and place into the middle of an AE_DR register
AE_L32M.IU Load a 32-bit fractional values and place into the middle of an AE_DR register
AE_L32M.X Load a 32-bit fractional values and place into the middle of an AE_DR register
AE_L32M.XC Load a 32-bit fractional values and place into the middle of an AE_DR register
AE_L32M.XU Load a 32-bit fractional values and place into the middle of an AE_DR register
AE_L32X2.I Load two 32-bit values into the AE_DR register
AE_L32X2.IP Load two 32-bit values into the AE_DR register
AE_L32X2.RIC Load two 32-bit values into the AE_DR register
AE_L32X2.RIP Load two 32-bit values into the AE_DR register
AE_L32X2.X Load two 32-bit values into the AE_DR register
AE_L32X2.XC Load two 32-bit values into the AE_DR register
AE_L32X2.XP Load two 32-bit values into the AE_DR register
AE_L32X2F24.I Load two 24-bit fractional values into the AE_DR register
AE_L32X2F24.IP Load two 24-bit fractional values into the AE_DR register
AE_L32X2F24.RIC Load two 24-bit fractional values into the AE_DR register
AE_L32X2F24.RIP Load two 24-bit fractional values into the AE_DR register
AE_L32X2F24.X Load two 24-bit fractional values into the AE_DR register
AE_L32X2F24.XC Load two 24-bit fractional values into the AE_DR register
AE_L32X2F24.XP Load two 24-bit fractional values into the AE_DR register
AE_L64.I Load a 64-bit value into the AE_DR register
AE_L64.IP Load a 64-bit value into the AE_DR register
AE_L64.X Load a 64-bit value into the AE_DR register
AE_L64.XC Load a 64-bit value into the AE_DR register
AE_L64.XP Load a 64-bit value into the AE_DR register
AE_LA16X4.IC Load four 16-bit values into the AE_DR register
AE_LA16X4.IP Load four 16-bit values into the AE_DR register
AE_LA16X4.RIC Load four 16-bit values into the AE_DR register
AE_LA16X4.RIP Load four 16-bit values into the AE_DR register
AE_LA16X4NEG.PC Priming load alignment register
AE_LA16X4POS.PC Priming load alignment register
AE_LA24.IC Loads a packed 24-bit value and replicates into the AE_DR register
AE_LA24.IP Loads a packed 24-bit value and replicates into the AE_DR register
AE_LA24.RIC Loads a packed 24-bit value and replicates into the AE_DR register
AE_LA24.RIP Loads a packed 24-bit value and replicates into the AE_DR register
AE_LA24NEG.PC Priming load alignment register
AE_LA24POS.PC Priming load alignment register
AE_LA24X2.IC Loads two packed 24-bit values into the AE_DR register
AE_LA24X2.IP Loads two packed 24-bit values into the AE_DR register
AE_LA24X2.RIC Loads two packed 24-bit values into the AE_DR register
AE_LA24X2.RIP Loads two packed 24-bit values into the AE_DR register
AE_LA24X2NEG.PC Priming load alignment register
AE_LA24X2POS.PC Priming load alignment register
AE_LA32X2.IC Load two 32-bit values into the AE_DR register
AE_LA32X2.IP Load two 32-bit values into the AE_DR register
AE_LA32X2.RIC Load two 32-bit values into the AE_DR register
AE_LA32X2.RIP Load two 32-bit values into the AE_DR register
AE_LA32X2F24.IC Load two 24-bit fractional values into the AE_DR register
AE_LA32X2F24.IP Load two 24-bit fractional values into the AE_DR register
AE_LA32X2F24.RIC Load two 24-bit fractional values into the AE_DR register
AE_LA32X2F24.RIP Load two 24-bit fractional values into the AE_DR register
AE_LA32X2NEG.PC Priming load alignment register
AE_LA32X2POS.PC Priming load alignment register
AE_LA64.PP Priming load alignment register
AE_LALIGN64.I Load a 64-bit value into the alignment register
AE_LB bitstream lookahead, returning 1 to 16 bits based on AR register
AE_LBI bitstream lookahead, returning 1 to 16 bits based on immediate
AE_LBK bitstream lookahead, return bits based on AR register (keeping low bits of another AR)
AE_LBKI bitstream lookahead, return bits based on immediate (keeping low bits of an AR register)
AE_LBS signed bitstream lookahead, returning 1 to 16 bits based on AR register
AE_LBSI signed bitstream lookahead, returning 1 to 16 bits based on immediate
AE_LE16 4-way 16-bit signed less-than-or-equal comparison
AE_LE32 2-way 32-bit signed less-than-or-equal comparison
AE_LE64 64-bit signed less than or equal
AE_LT16 4-way 16-bit signed less-than comparison
AE_LT32 2-way 32-bit signed less-than comparison
AE_LT64 64-bit signed less than
AE_MAX32 2-way 32-bit maximum
AE_MAX64 64-bit signed maximum
AE_MAXABS32S 2-way saturating maximum of absolute value
AE_MAXABS64S 64-bit signed maximum of absolute value with saturation
AE_MIN32 2-way 32-bit minimum
AE_MIN64 64-bit signed minimum
AE_MINABS32S 2-way saturating minimum of absolute value
AE_MINABS64S 64-bit signed minimum of absolute value with saturation
AE_MOV Copy AE_DR register
AE_MOVAD16.0 Move and sign-extend 16-bits from AE_DR to AR
AE_MOVAD16.1 Move and sign-extend 16-bits from AE_DR to AR
AE_MOVAD16.2 Move and sign-extend 16-bits from AE_DR to AR
AE_MOVAD16.3 Move and sign-extend 16-bits from AE_DR to AR
AE_MOVAD32.H Move 32-bits from AE_DR to AR
AE_MOVAD32.L Move 32-bits from AE_DR to AR
AE_MOVALIGN Copy of an AE_VALIGN register
AE_MOVDA16 Move 16-bits from an AR register into each quarter of AE_DR
AE_MOVDA16X2 Move 16-bits from each of two AR registers and copy into each half of AE_DR
AE_MOVDA32 Move an AR register into each half of AE_DR
AE_MOVDA32X2 Move two AR register into AE_DR
AE_MOVF16X4 4-way 16-bit conditional copy of an AE_DR register (if clear)
AE_MOVF32X2 32-bit dual conditional copy of an AE_DR register (if clear)
AE_MOVF64 64-bit conditional copy of an AE_DR register (if clear)
AE_MOVI Move immediate into each half of AE_DR
AE_MOVT16X4 4-way 16-bit conditional copy of an AE_DR register (if set)
AE_MOVT32X2 32-bit dual conditional copy of an AE_DR register (if set)
AE_MOVT64 64-bit conditional copy of an AE_DR register (if set)
AE_MUL16X4 Four-way SIMD 16x16-bit signed integer multiply with 32-bit result.
AE_MUL32.HH 32x32-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32.LH 32x32-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32.LL 32x32-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32.LL_S2 32x32-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MUL32U.LL 32x32-bit unsigned integer multiplication with 64-bit result
AE_MUL32X16.H0 32x16-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32X16.H0_S2 32x16-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MUL32X16.H1 32x16-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32X16.H1_S2 32x16-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MUL32X16.H2 32x16-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32X16.H2_S2 32x16-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MUL32X16.H3 32x16-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32X16.H3_S2 32x16-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MUL32X16.L0 32x16-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32X16.L0_S2 32x16-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MUL32X16.L1 32x16-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32X16.L1_S2 32x16-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MUL32X16.L2 32x16-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32X16.L2_S2 32x16-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MUL32X16.L3 32x16-bit signed integer multiplication with 64-bit result, with no saturation.
AE_MUL32X16.L3_S2 32x16-bit signed integer multiplication with 64-bit result, with no saturation: slot 2 version.
AE_MULA16X4 Four-way SIMD 16x16-bit signed integer MAC with 32-bit result.
AE_MULA32.HH 32x32-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32.LH 32x32-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32.LL 32x32-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32.LL_S2 32x32-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULA32U.LL 32x32-bit unsigned integer MAC with 64-bit result
AE_MULA32X16.H0 32x16-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32X16.H0_S2 32x16-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULA32X16.H1 32x16-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32X16.H1_S2 32x16-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULA32X16.H2 32x16-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32X16.H2_S2 32x16-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULA32X16.H3 32x16-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32X16.H3_S2 32x16-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULA32X16.L0 32x16-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32X16.L0_S2 32x16-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULA32X16.L1 32x16-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32X16.L1_S2 32x16-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULA32X16.L2 32x16-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32X16.L2_S2 32x16-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULA32X16.L3 32x16-bit signed integer MAC with 64-bit result, with no saturation.
AE_MULA32X16.L3_S2 32x16-bit signed integer MAC with 64-bit result, with no saturation: slot 2 version.
AE_MULAAD24.HH.LL 24x24-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation
AE_MULAAD24.HH.LL_S2 24x24-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation: slot 2 version
AE_MULAAD24.HL.LH 24x24-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation
AE_MULAAD24.HL.LH_S2 24x24-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation: slot 2 version
AE_MULAAD32X16.H0.L1 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result without saturation.
AE_MULAAD32X16.H0.L1_S2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result without saturation: slot 2 version.
AE_MULAAD32X16.H1.L0 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation.
AE_MULAAD32X16.H1.L0_S2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation: slot 2 version.
AE_MULAAD32X16.H2.L3 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result without saturation.
AE_MULAAD32X16.H2.L3_S2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result without saturation: slot 2 version.
AE_MULAAD32X16.H3.L2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation.
AE_MULAAD32X16.H3.L2_S2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation: slot 2 version.
AE_MULAAFD16SS.11_00 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step..
AE_MULAAFD16SS.11_00_S2 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step.: slot 2 version.
AE_MULAAFD16SS.13_02 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step..
AE_MULAAFD16SS.13_02_S2 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step.: slot 2 version.
AE_MULAAFD16SS.33_22 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step..
AE_MULAAFD16SS.33_22_S2 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step.: slot 2 version.
AE_MULAAFD24.HH.LL 24x24-bit signed fraction (1.23) dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation
AE_MULAAFD24.HH.LL_S2 24x24-bit signed fraction (1.23) dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation: slot 2 version
AE_MULAAFD24.HL.LH 24x24-bit signed fraction (1.23) dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation
AE_MULAAFD24.HL.LH_S2 24x24-bit signed fraction (1.23) dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation: slot 2 version
AE_MULAAFD32X16.H0.L1 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation.
AE_MULAAFD32X16.H0.L1_S2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULAAFD32X16.H1.L0 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation.
AE_MULAAFD32X16.H1.L0_S2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULAAFD32X16.H2.L3 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation.
AE_MULAAFD32X16.H2.L3_S2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULAAFD32X16.H3.L2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation.
AE_MULAAFD32X16.H3.L2_S2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULAC24 Complex 24x24-bit signed integer quad MAC with 32-bit accumulation.
AE_MULAC32X16.H Complex 32x16-bit signed integer quad MAC with 32-bit accumulation.
AE_MULAC32X16.L Complex 32x16-bit signed integer quad MAC with 32-bit accumulation.
AE_MULAF16SS.00 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.00_S2 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation: slot 2 version.
AE_MULAF16SS.10 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.11 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.20 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.21 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.22 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.30 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.31 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.32 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16SS.33 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULAF16X4SS Four-way SIMD 16x16-bit signed fractional (1.15) MAC with 32-bit (1.31) result with intermediate product and accumulator saturation.
AE_MULAF32R.HH 32x32-bit signed fractional (1.31) MAC with symmetric rounding down to 17.47-bits.
AE_MULAF32R.LH 32x32-bit signed fractional (1.31) MAC with symmetric rounding down to 17.47-bits.
AE_MULAF32R.LL 32x32-bit signed fractional (1.31) MAC with symmetric rounding down to 17.47-bits.
AE_MULAF32R.LL_S2 32x32-bit signed fractional (1.31) MAC with symmetric rounding down to 17.47-bits: slot 2 version.
AE_MULAF32S.HH 32x32-bit signed fractional (1.31) MAC with 64-bit (1.63) result, with saturation.
AE_MULAF32S.LH 32x32-bit signed fractional (1.31) MAC with 64-bit (1.63) result, with saturation.
AE_MULAF32S.LL 32x32-bit signed fractional (1.31) MAC with 64-bit (1.63) result, with saturation.
AE_MULAF32S.LL_S2 32x32-bit signed fractional (1.31) MAC with 64-bit (1.63) result, with saturation: slot 2 version.
AE_MULAF32X16.H0 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation.
AE_MULAF32X16.H0_S2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULAF32X16.H1 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation.
AE_MULAF32X16.H1_S2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULAF32X16.H2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation.
AE_MULAF32X16.H2_S2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULAF32X16.H3 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation.
AE_MULAF32X16.H3_S2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULAF32X16.L0 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation.
AE_MULAF32X16.L0_S2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULAF32X16.L1 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation.
AE_MULAF32X16.L1_S2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULAF32X16.L2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation.
AE_MULAF32X16.L2_S2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULAF32X16.L3 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation.
AE_MULAF32X16.L3_S2 32x16-bit signed fractional MAC with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULAF48Q32SP16S.L Legacy HiFi 2 32x16-bit signed fraction (1.31 x 1.15) multiply-add to 64-bit (9.47) result without saturation.
AE_MULAF48Q32SP16S.L_S2 Legacy HiFi 2 32x16-bit signed fraction (1.31 x 1.15) multiply-add to 64-bit (9.47) result without saturation: slot 2 version.
AE_MULAF48Q32SP16U.L 32-bit signed x 16-bit unsigned fraction (1.31 x 1.15) multiply-add to 64-bit (9.47) result without saturation.
AE_MULAF48Q32SP16U.L_S2 32-bit signed x 16-bit unsigned fraction (1.31 x 1.15) multiply-add to 64-bit (9.47) result without saturation: slot 2 version.
AE_MULAFC24RA Complex 24x24-bit signed fractional (1.23) quad MAC with asymmetric rounding down to 9.23-bits.
AE_MULAFC32X16RAS.H Complex 32x16-bit signed fractional quad MAC with asymmetric rounding down to 1.31-bits.
AE_MULAFC32X16RAS.L Complex 32x16-bit signed fractional quad MAC with asymmetric rounding down to 1.31-bits.
AE_MULAFD24X2.FIR.H Quad 24x24-bit signed fractional (1.23) MAC into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULAFD24X2.FIR.L Quad 24x24-bit signed fractional (1.23) MAC into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULAFD32X16X2.FIR.HH Quad 32x16-bit signed fractional MAC into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULAFD32X16X2.FIR.HL Quad 32x16-bit signed fractional MAC into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULAFD32X16X2.FIR.LH Quad 32x16-bit signed fractional MAC into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULAFD32X16X2.FIR.LL Quad 32x16-bit signed fractional MAC into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULAFP24X2R Two-way SIMD 24x24-bit signed fractional (1.23) MAC with symmetric rounding down to 9.23-bits.
AE_MULAFP24X2RA Two-way SIMD 24x24-bit signed fractional (1.23) MAC with asymmetric rounding down to 9.23-bits.
AE_MULAFP24X2RA_S2 Two-way SIMD 24x24-bit signed fractional (1.23) MAC with asymmetric rounding down to 9.23-bits: slot 2 version.
AE_MULAFP24X2R_S2 Two-way SIMD 24x24-bit signed fractional (1.23) MAC with symmetric rounding down to 9.23-bits: slot 2 version.
AE_MULAFP32X16X2RAS.H Two-way SIMD 32x16-bit signed fractional MAC with asymmetric rounding down to 1.31-bits.
AE_MULAFP32X16X2RAS.H_S2 Two-way SIMD 32x16-bit signed fractional MAC with asymmetric rounding down to 1.31-bits: slot 2 version.
AE_MULAFP32X16X2RAS.L Two-way SIMD 32x16-bit signed fractional MAC with asymmetric rounding down to 1.31-bits.
AE_MULAFP32X16X2RAS.L_S2 Two-way SIMD 32x16-bit signed fractional MAC with asymmetric rounding down to 1.31-bits: slot 2 version.
AE_MULAFP32X16X2RS.H Two-way SIMD 32x16-bit signed fractional MAC with symmetric rounding down to 1.31-bits.
AE_MULAFP32X16X2RS.H_S2 Two-way SIMD 32x16-bit signed fractional MAC with symmetric rounding down to 1.31-bits: slot 2 version.
AE_MULAFP32X16X2RS.L Two-way SIMD 32x16-bit signed fractional MAC with symmetric rounding down to 1.31-bits.
AE_MULAFP32X16X2RS.L_S2 Two-way SIMD 32x16-bit signed fractional MAC with symmetric rounding down to 1.31-bits: slot 2 version.
AE_MULAFP32X2RAS Two-way SIMD 32x32-bit signed fractional (1.31) MAC with asymmetric rounding down to 1.31-bits.
AE_MULAFP32X2RS Two-way SIMD 32x32-bit signed fractional (1.31) MAC with symmetric rounding down to 1.31-bits.
AE_MULAFQ32SP24S.H 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 50-bit (3.47) output without saturation.
AE_MULAFQ32SP24S.H_S2 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 50-bit (3.47) output without saturation: slot 2 version.
AE_MULAFQ32SP24S.L 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 50-bit (3.47) output without saturation.
AE_MULAFQ32SP24S.L_S2 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 50-bit (3.47) output without saturation: slot 2 version.
AE_MULAP24X2 Two-way SIMD 24x24-bit signed integer MAC with 32-bit accumulation.
AE_MULAP24X2_S2 Two-way SIMD 24x24-bit signed integer MAC with 32-bit accumulation: slot 2 version.
AE_MULAP32X16X2.H Two-way SIMD 32x16-bit signed integer MAC with 32-bit accumulation.
AE_MULAP32X16X2.L Two-way SIMD 32x16-bit signed integer MAC with 32-bit accumulation.
AE_MULAP32X2 Two-way SIMD 32x32-bit signed integer MAC with 32-bit accumulation.
AE_MULAQ32SP16S.L Legacy HiFi 2 32x16-bit signed integer multiply-add (MAC) to 64-bit result without saturation.
AE_MULAQ32SP16S.L_S2 Legacy HiFi 2 32x16-bit signed integer multiply-add (MAC) to 64-bit result without saturation: slot 2 version.
AE_MULAQ32SP16U.L 32-bit signed x 16-bit unsigned integer multiply-add (MAC) to 64-bit result without saturation.
AE_MULAQ32SP16U.L_S2 32-bit signed x 16-bit unsigned integer multiply-add (MAC) to 64-bit result without saturation: slot 2 version.
AE_MULARFQ32SP24S.H 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation.
AE_MULARFQ32SP24S.H_S2 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation: slot 2 version.
AE_MULARFQ32SP24S.L 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation.
AE_MULARFQ32SP24S.L_S2 32x24-bit signed fraction multiply-add (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation: slot 2 version.
AE_MULAS32F48P16S.HH Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-add (MAC) with 32-bit saturation.
AE_MULAS32F48P16S.HH_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-add (MAC) with 32-bit saturation: slot 2 version.
AE_MULAS32F48P16S.LH Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-add (MAC) with 32-bit saturation.
AE_MULAS32F48P16S.LH_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-add (MAC) with 32-bit saturation: slot 2 version.
AE_MULAS32F48P16S.LL Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-add (MAC) with 32-bit saturation.
AE_MULAS32F48P16S.LL_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-add (MAC) with 32-bit saturation: slot 2 version.
AE_MULASD24.HH.LL 24x24-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation
AE_MULASD24.HH.LL_S2 24x24-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation: slot 2 version
AE_MULASD24.HL.LH 24x24-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation
AE_MULASD24.HL.LH_S2 24x24-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation: slot 2 version
AE_MULASD32X16.H1.L0 32x16-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation.
AE_MULASD32X16.H1.L0_S2 32x16-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation: slot 2 version.
AE_MULASD32X16.H3.L2 32x16-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation.
AE_MULASD32X16.H3.L2_S2 32x16-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation: slot 2 version.
AE_MULASFD24.HH.LL 24x24-bit signed fraction (1.23) dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation
AE_MULASFD24.HH.LL_S2 24x24-bit signed fraction (1.23) dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation: slot 2 version
AE_MULASFD24.HL.LH 24x24-bit signed fraction (1.23) dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation
AE_MULASFD24.HL.LH_S2 24x24-bit signed fraction (1.23) dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation: slot 2 version
AE_MULASFD32X16.H1.L0 32x16-bit signed fraction dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation.
AE_MULASFD32X16.H1.L0_S2 32x16-bit signed fraction dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULASFD32X16.H3.L2 32x16-bit signed fraction dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation.
AE_MULASFD32X16.H3.L2_S2 32x16-bit signed fraction dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULC24 Complex 24x24-bit signed integer quad multiply into 32-bits.
AE_MULC32X16.H Complex 32x16-bit signed integer quad multiply into 32-bits.
AE_MULC32X16.L Complex 32x16-bit signed integer quad multiply into 32-bits.
AE_MULF16SS.00 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.00_S2 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation: slot 2 version.
AE_MULF16SS.10 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.11 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.20 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.21 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.22 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.30 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.31 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.32 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16SS.33 16x16-bit signed fractional (1.15) multiplication with 32-bit (1.31) results, with intermediate product saturation.
AE_MULF16X4SS Four-way SIMD 16x16-bit signed fractional (1.15) multiply with 32-bit (1.31) result and saturation.
AE_MULF32R.HH 32x32-bit signed fractional (1.31) multiplication with symmetric rounding down to 17.47-bits.
AE_MULF32R.LH 32x32-bit signed fractional (1.31) multiplication with symmetric rounding down to 17.47-bits.
AE_MULF32R.LL 32x32-bit signed fractional (1.31) multiplication with symmetric rounding down to 17.47-bits.
AE_MULF32R.LL_S2 32x32-bit signed fractional (1.31) multiplication with symmetric rounding down to 17.47-bits: slot 2 version.
AE_MULF32S.HH 32x32-bit signed fractional (1.31) multiplication with 64-bit (1.63) result, with saturation.
AE_MULF32S.LH 32x32-bit signed fractional (1.31) multiplication with 64-bit (1.63) result, with saturation.
AE_MULF32S.LL 32x32-bit signed fractional (1.31) multiplication with 64-bit (1.63) result, with saturation.
AE_MULF32S.LL_S2 32x32-bit signed fractional (1.31) multiplication with 64-bit (1.63) result, with saturation: slot 2 version.
AE_MULF32X16.H0 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation.
AE_MULF32X16.H0_S2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULF32X16.H1 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation.
AE_MULF32X16.H1_S2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULF32X16.H2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation.
AE_MULF32X16.H2_S2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULF32X16.H3 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation.
AE_MULF32X16.H3_S2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULF32X16.L0 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation.
AE_MULF32X16.L0_S2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULF32X16.L1 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation.
AE_MULF32X16.L1_S2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULF32X16.L2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation.
AE_MULF32X16.L2_S2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULF32X16.L3 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation.
AE_MULF32X16.L3_S2 32x16-bit signed fractional multiplication with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULF48Q32SP16S.L Legacy HiFi 2 32x16-bit signed fraction (1.31 x 1.15) multiply to 64-bit (9.47) result without saturation.
AE_MULF48Q32SP16S.L_S2 Legacy HiFi 2 32x16-bit signed fraction (1.31 x 1.15) multiply to 64-bit (9.47) result without saturation: slot 2 version.
AE_MULF48Q32SP16U.L 32-bit signed x 16-bit unsigned fraction (1.31 x 1.15) multiply to 64-bit (9.47) result without saturation.
AE_MULF48Q32SP16U.L_S2 32-bit signed x 16-bit unsigned fraction (1.31 x 1.15) multiply to 64-bit (9.47) result without saturation: slot 2 version.
AE_MULFC24RA Complex 24x24-bit signed fractional (1.23) quad multiply with asymmetric rounding down to 9.23-bits.
AE_MULFC32X16RAS.H Complex 32x16-bit signed fractional quad multiply with asymmetric rounding down to 1.31-bits.
AE_MULFC32X16RAS.L Complex 32x16-bit signed fractional quad multiply with asymmetric rounding down to 1.31-bits.
AE_MULFD24X2.FIR.H Quad 24x24-bit signed fractional (1.23) multiply into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULFD24X2.FIR.L Quad 24x24-bit signed fractional (1.23) multiply into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULFD32X16X2.FIR.HH Quad 32x16-bit signed fractional multiply into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULFD32X16X2.FIR.HL Quad 32x16-bit signed fractional multiply into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULFD32X16X2.FIR.LH Quad 32x16-bit signed fractional multiply into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULFD32X16X2.FIR.LL Quad 32x16-bit signed fractional multiply into two 64-bit (17.47) results, with operands selected for FIR computations.
AE_MULFP16X4RAS Four-way SIMD 16x16-bit signed fractional (1.15) multiply with 16-bit (1.15) result, asymmetric rounding and saturation.
AE_MULFP16X4S Four-way SIMD 16x16-bit signed fractional (1.15) multiply with 16-bit (1.15) result and saturation.
AE_MULFP24X2R Two-way SIMD 24x24-bit signed fractional (1.23) multiply with symmetric rounding down to 9.23-bits.
AE_MULFP24X2RA Two-way SIMD 24x24-bit signed fractional (1.23) multiply with asymmetric rounding down to 9.23-bits.
AE_MULFP24X2RA_S2 Two-way SIMD 24x24-bit signed fractional (1.23) multiply with asymmetric rounding down to 9.23-bits: slot 2 version.
AE_MULFP24X2R_S2 Two-way SIMD 24x24-bit signed fractional (1.23) multiply with symmetric rounding down to 9.23-bits: slot 2 version.
AE_MULFP32X16X2RAS.H Two-way SIMD 32x16-bit signed fractional multiply with asymmetric rounding down to 1.31-bits.
AE_MULFP32X16X2RAS.H_S2 Two-way SIMD 32x16-bit signed fractional multiply with asymmetric rounding down to 1.31-bits: slot 2 version.
AE_MULFP32X16X2RAS.L Two-way SIMD 32x16-bit signed fractional multiply with asymmetric rounding down to 1.31-bits.
AE_MULFP32X16X2RAS.L_S2 Two-way SIMD 32x16-bit signed fractional multiply with asymmetric rounding down to 1.31-bits: slot 2 version.
AE_MULFP32X16X2RS.H Two-way SIMD 32x16-bit signed fractional multiply with symmetric rounding down to 1.31-bits.
AE_MULFP32X16X2RS.H_S2 Two-way SIMD 32x16-bit signed fractional multiply with symmetric rounding down to 1.31-bits: slot 2 version.
AE_MULFP32X16X2RS.L Two-way SIMD 32x16-bit signed fractional multiply with symmetric rounding down to 1.31-bits.
AE_MULFP32X16X2RS.L_S2 Two-way SIMD 32x16-bit signed fractional multiply with symmetric rounding down to 1.31-bits: slot 2 version.
AE_MULFP32X2RAS Two-way SIMD 32x32-bit signed fractional (1.31) multiply with asymmetric rounding down to 1.31-bits.
AE_MULFP32X2RS Two-way SIMD 32x32-bit signed fractional (1.31) multiply with symmetric rounding down to 1.31-bits.
AE_MULFQ32SP24S.H 32x24-bit signed fraction multiply (1.31 x 1.23) to 50-bit (3.47) output without saturation.
AE_MULFQ32SP24S.H_S2 32x24-bit signed fraction multiply (1.31 x 1.23) to 50-bit (3.47) output without saturation: slot 2 version.
AE_MULFQ32SP24S.L 32x24-bit signed fraction multiply (1.31 x 1.23) to 50-bit (3.47) output without saturation.
AE_MULFQ32SP24S.L_S2 32x24-bit signed fraction multiply (1.31 x 1.23) to 50-bit (3.47) output without saturation: slot 2 version.
AE_MULP24X2 Two-way SIMD 24x24-bit signed integer multiply.
AE_MULP24X2_S2 Two-way SIMD 24x24-bit signed integer multiply: slot 2 version.
AE_MULP32X16X2.H Two-way SIMD 32x16-bit signed integer multiply.
AE_MULP32X16X2.L Two-way SIMD 32x16-bit signed integer multiply.
AE_MULP32X2 Two-way SIMD 32x32-bit signed integer multiply.
AE_MULQ32SP16S.L Legacy HiFi 2 32x16-bit signed integer multiply to 64-bit result without saturation.
AE_MULQ32SP16S.L_S2 Legacy HiFi 2 32x16-bit signed integer multiply to 64-bit result without saturation: slot 2 version.
AE_MULQ32SP16U.L 32-bit signed x 16-bit unsigned integer multiply to 64-bit result without saturation.
AE_MULQ32SP16U.L_S2 32-bit signed x 16-bit unsigned integer multiply to 64-bit result without saturation: slot 2 version.
AE_MULRFQ32SP24S.H 32x24-bit signed fraction multiply (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation.
AE_MULRFQ32SP24S.H_S2 32x24-bit signed fraction multiply (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation: slot 2 version.
AE_MULRFQ32SP24S.L 32x24-bit signed fraction multiply (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation.
AE_MULRFQ32SP24S.L_S2 32x24-bit signed fraction multiply (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation: slot 2 version.
AE_MULS16X4 Four-way SIMD 16x16-bit signed integer multiply-subtract with 32-bit result.
AE_MULS32.HH 32x32-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32.LH 32x32-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32.LL 32x32-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32F48P16S.HH Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply with 32-bit saturation.
AE_MULS32F48P16S.HH_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply with 32-bit saturation: slot 2 version.
AE_MULS32F48P16S.LH Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply with 32-bit saturation.
AE_MULS32F48P16S.LH_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply with 32-bit saturation: slot 2 version.
AE_MULS32F48P16S.LL Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply with 32-bit saturation.
AE_MULS32F48P16S.LL_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply with 32-bit saturation: slot 2 version.
AE_MULS32U.LL 32x32-bit unsigned integer multiply-subtract with 64-bit result
AE_MULS32X16.H0 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32X16.H0_S2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation: slot 2 version.
AE_MULS32X16.H1 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32X16.H1_S2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation: slot 2 version.
AE_MULS32X16.H2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32X16.H2_S2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation: slot 2 version.
AE_MULS32X16.H3 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32X16.H3_S2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation: slot 2 version.
AE_MULS32X16.L0 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32X16.L0_S2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation: slot 2 version.
AE_MULS32X16.L1 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32X16.L1_S2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation: slot 2 version.
AE_MULS32X16.L2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32X16.L2_S2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation: slot 2 version.
AE_MULS32X16.L3 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation.
AE_MULS32X16.L3_S2 32x16-bit signed integer multiply-subtract with 64-bit result, with no saturation: slot 2 version.
AE_MULSAD24.HH.LL 24x24-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation
AE_MULSAD24.HH.LL_S2 24x24-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation: slot 2 version
AE_MULSAD32X16.H1.L0 32x16-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation.
AE_MULSAD32X16.H1.L0_S2 32x16-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation: slot 2 version.
AE_MULSAD32X16.H3.L2 32x16-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation.
AE_MULSAD32X16.H3.L2_S2 32x16-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation: slot 2 version.
AE_MULSAFD24.HH.LL 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation
AE_MULSAFD24.HH.LL_S2 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation: slot 2 version
AE_MULSAFD32X16.H1.L0 32x16-bit signed fraction dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation.
AE_MULSAFD32X16.H1.L0_S2 32x16-bit signed fraction dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULSAFD32X16.H3.L2 32x16-bit signed fraction dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation.
AE_MULSAFD32X16.H3.L2_S2 32x16-bit signed fraction dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULSF16SS.00 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.00_S2 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation: slot 2 version.
AE_MULSF16SS.10 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.11 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.20 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.21 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.22 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.30 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.31 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.32 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16SS.33 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) results, with intermediate product and accumulator saturation.
AE_MULSF16X4SS Four-way SIMD 16x16-bit signed fractional (1.15) multiply-subtract with 32-bit (1.31) result with intermediate product and accumulator saturation.
AE_MULSF32R.HH 32x32-bit signed fractional (1.31) multiply-subtract with symmetric rounding down to 17.47-bits.
AE_MULSF32R.LH 32x32-bit signed fractional (1.31) multiply-subtract with symmetric rounding down to 17.47-bits.
AE_MULSF32R.LL 32x32-bit signed fractional (1.31) multiply-subtract with symmetric rounding down to 17.47-bits.
AE_MULSF32R.LL_S2 32x32-bit signed fractional (1.31) multiply-subtract with symmetric rounding down to 17.47-bits: slot 2 version.
AE_MULSF32S.HH 32x32-bit signed fractional (1.31) multiply-subtract with 64-bit (1.63) result, with saturation.
AE_MULSF32S.LH 32x32-bit signed fractional (1.31) multiply-subtract with 64-bit (1.63) result, with saturation.
AE_MULSF32S.LL 32x32-bit signed fractional (1.31) multiply-subtract with 64-bit (1.63) result, with saturation.
AE_MULSF32X16.H0 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation.
AE_MULSF32X16.H0_S2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULSF32X16.H1 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation.
AE_MULSF32X16.H1_S2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULSF32X16.H2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation.
AE_MULSF32X16.H2_S2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULSF32X16.H3 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation.
AE_MULSF32X16.H3_S2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULSF32X16.L0 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation.
AE_MULSF32X16.L0_S2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULSF32X16.L1 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation.
AE_MULSF32X16.L1_S2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULSF32X16.L2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation.
AE_MULSF32X16.L2_S2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULSF32X16.L3 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation.
AE_MULSF32X16.L3_S2 32x16-bit signed fractional multiply-subtract with 64-bit (17.47) result, with no saturation: slot 2 version.
AE_MULSF48Q32SP16S.L Legacy HiFi 2 32x16-bit signed fraction (1.31 x 1.15) multiply-subtract to 64-bit (9.47) result without saturation.
AE_MULSF48Q32SP16S.L_S2 Legacy HiFi 2 32x16-bit signed fraction (1.31 x 1.15) multiply-subtract to 64-bit (9.47) result without saturation: slot 2 version.
AE_MULSF48Q32SP16U.L 32-bit signed x 16-bit unsigned fraction (1.31 x 1.15) multiply-subtract to 64-bit (9.47) result without saturation.
AE_MULSF48Q32SP16U.L_S2 32-bit signed x 16-bit unsigned fraction (1.31 x 1.15) multiply-subtract to 64-bit (9.47) result without saturation: slot 2 version.
AE_MULSFP24X2R Two-way SIMD 24x24-bit signed fractional (1.23) multiply-subtract with symmetric rounding down to 9.23-bits.
AE_MULSFP24X2RA Two-way SIMD 24x24-bit signed fractional (1.23) multiply-subtract with asymmetric rounding down to 9.23-bits.
AE_MULSFP24X2RA_S2 Two-way SIMD 24x24-bit signed fractional (1.23) multiply-subtract with asymmetric rounding down to 9.23-bits: slot 2 version.
AE_MULSFP24X2R_S2 Two-way SIMD 24x24-bit signed fractional (1.23) multiply-subtract with symmetric rounding down to 9.23-bits: slot 2 version.
AE_MULSFP32X16X2RAS.H Two-way SIMD 32x16-bit signed fractional multiply-subtract with asymmetric rounding down to 1.31-bits.
AE_MULSFP32X16X2RAS.H_S2 Two-way SIMD 32x16-bit signed fractional multiply-subtract with asymmetric rounding down to 1.31-bits: slot 2 version.
AE_MULSFP32X16X2RAS.L Two-way SIMD 32x16-bit signed fractional multiply-subtract with asymmetric rounding down to 1.31-bits.
AE_MULSFP32X16X2RAS.L_S2 Two-way SIMD 32x16-bit signed fractional multiply-subtract with asymmetric rounding down to 1.31-bits: slot 2 version.
AE_MULSFP32X16X2RS.H Two-way SIMD 32x16-bit signed fractional multiply-subtract with symmetric rounding down to 1.31-bits.
AE_MULSFP32X16X2RS.H_S2 Two-way SIMD 32x16-bit signed fractional multiply-subtract with symmetric rounding down to 1.31-bits: slot 2 version.
AE_MULSFP32X16X2RS.L Two-way SIMD 32x16-bit signed fractional multiply-subtract with symmetric rounding down to 1.31-bits.
AE_MULSFP32X16X2RS.L_S2 Two-way SIMD 32x16-bit signed fractional multiply-subtract with symmetric rounding down to 1.31-bits: slot 2 version.
AE_MULSFP32X2RAS Two-way SIMD 32x32-bit signed fractional (1.31) multiply-subtract with asymmetric rounding down to 1.31-bits.
AE_MULSFP32X2RS Two-way SIMD 32x32-bit signed fractional (1.31) multiply-subtract with symmetric rounding down to 1.31-bits.
AE_MULSFQ32SP24S.H 32x24-bit signed fraction multiply-subtract (1.31 x 1.23) to 50-bit (3.47) output without saturation.
AE_MULSFQ32SP24S.H_S2 32x24-bit signed fraction multiply-subtract (1.31 x 1.23) to 50-bit (3.47) output without saturation: slot 2 version.
AE_MULSFQ32SP24S.L 32x24-bit signed fraction multiply-subtract (1.31 x 1.23) to 50-bit (3.47) output without saturation.
AE_MULSFQ32SP24S.L_S2 32x24-bit signed fraction multiply-subtract (1.31 x 1.23) to 50-bit (3.47) output without saturation: slot 2 version.
AE_MULSP24X2 Two-way SIMD 24x24-bit signed integer multiply-subtract with 32-bit accumulation.
AE_MULSP24X2_S2 Two-way SIMD 24x24-bit signed integer multiply-subtract with 32-bit accumulation: slot 2 version.
AE_MULSP32X16X2.H Two-way SIMD 32x16-bit signed integer multiply-subtract with 32-bit accumulation.
AE_MULSP32X16X2.L Two-way SIMD 32x16-bit signed integer multiply-subtract with 32-bit accumulation.
AE_MULSP32X2 Two-way SIMD 32x32-bit signed integer multiply-subtract with 32-bit accumulation.
AE_MULSQ32SP16S.L Legacy HiFi 2 32x16-bit signed integer multiply-subtract to 64-bit result without saturation.
AE_MULSQ32SP16S.L_S2 Legacy HiFi 2 32x16-bit signed integer multiply-subtract to 64-bit result without saturation: slot 2 version.
AE_MULSQ32SP16U.L 32-bit signed x 16-bit unsigned integer multiply-subtract to 64-bit result without saturation.
AE_MULSQ32SP16U.L_S2 32-bit signed x 16-bit unsigned integer multiply-subtract to 64-bit result without saturation: slot 2 version.
AE_MULSRFQ32SP24S.H 32x24-bit signed fraction multiply-subtract (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation.
AE_MULSRFQ32SP24S.H_S2 32x24-bit signed fraction multiply-subtract (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation: slot 2 version.
AE_MULSRFQ32SP24S.L 32x24-bit signed fraction multiply-subtract (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation.
AE_MULSRFQ32SP24S.L_S2 32x24-bit signed fraction multiply-subtract (1.31 x 1.23) to 34-bit (3.31) output with rounding and no saturation: slot 2 version.
AE_MULSS32F48P16S.HH Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-sub (MAC) with 32-bit saturation.
AE_MULSS32F48P16S.HH_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-sub (MAC) with 32-bit saturation: slot 2 version.
AE_MULSS32F48P16S.LH Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-sub (MAC) with 32-bit saturation.
AE_MULSS32F48P16S.LH_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-sub (MAC) with 32-bit saturation: slot 2 version.
AE_MULSS32F48P16S.LL Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-sub (MAC) with 32-bit saturation.
AE_MULSS32F48P16S.LL_S2 Legacy HiFi 2 16x16-bit signed fraction (1.15) to 32-bit (1.31) multiply-sub (MAC) with 32-bit saturation: slot 2 version.
AE_MULSSD24.HH.LL 24x24-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation
AE_MULSSD24.HH.LL_S2 24x24-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation: slot 2 version
AE_MULSSD24.HL.LH 24x24-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation
AE_MULSSD24.HL.LH_S2 24x24-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation: slot 2 version
AE_MULSSD32X16.H1.L0 32x16-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation.
AE_MULSSD32X16.H1.L0_S2 32x16-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation: slot 2 version.
AE_MULSSD32X16.H3.L2 32x16-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation.
AE_MULSSD32X16.H3.L2_S2 32x16-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation: slot 2 version.
AE_MULSSFD16SS.11_00 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step..
AE_MULSSFD16SS.11_00_S2 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step.: slot 2 version.
AE_MULSSFD16SS.13_02 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step..
AE_MULSSFD16SS.13_02_S2 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step.: slot 2 version.
AE_MULSSFD16SS.33_22 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step..
AE_MULSSFD16SS.33_22_S2 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step.: slot 2 version.
AE_MULSSFD24.HH.LL 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation
AE_MULSSFD24.HH.LL_S2 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation: slot 2 version
AE_MULSSFD24.HL.LH 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation
AE_MULSSFD24.HL.LH_S2 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation: slot 2 version
AE_MULSSFD32X16.H1.L0 32x16-bit signed fraction dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation.
AE_MULSSFD32X16.H1.L0_S2 32x16-bit signed fraction dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULSSFD32X16.H3.L2 32x16-bit signed fraction dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation.
AE_MULSSFD32X16.H3.L2_S2 32x16-bit signed fraction dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation: slot 2 version.
AE_MULZAAD24.HH.LL 24x24-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation, zeroed accumulator.
AE_MULZAAD24.HH.LL_S2 24x24-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZAAD24.HL.LH 24x24-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation, zeroed accumulator.
AE_MULZAAD24.HL.LH_S2 24x24-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZAAD32X16.H0.L1 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result without saturation, zeroed accumulator.
AE_MULZAAD32X16.H0.L1_S2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result without saturation, zeroed accumulator: slot 2 version.
AE_MULZAAD32X16.H1.L0 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation, zeroed accumulator..
AE_MULZAAD32X16.H1.L0_S2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZAAD32X16.H2.L3 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result without saturation, zeroed accumulator.
AE_MULZAAD32X16.H2.L3_S2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result without saturation, zeroed accumulator: slot 2 version.
AE_MULZAAD32X16.H3.L2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation, zeroed accumulator..
AE_MULZAAD32X16.H3.L2_S2 32x16-bit signed integer dual MAC with Addition/Addition and 64-bit result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZAAFD16SS.11_00 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step, zeroed accumulator..
AE_MULZAAFD16SS.11_00_S2 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step, zeroed accumulator.: slot 2 version.
AE_MULZAAFD16SS.13_02 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step, zeroed accumulator..
AE_MULZAAFD16SS.13_02_S2 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step, zeroed accumulator.: slot 2 version.
AE_MULZAAFD16SS.33_22 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step, zeroed accumulator..
AE_MULZAAFD16SS.33_22_S2 16x16-bit signed fraction dual MAC with Addition/Addition and 32-bit (1.31) result, with saturation after every step, zeroed accumulator.: slot 2 version.
AE_MULZAAFD24.HH.LL 24x24-bit signed fraction (1.23) dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZAAFD24.HH.LL_S2 24x24-bit signed fraction (1.23) dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZAAFD24.HL.LH 24x24-bit signed fraction (1.23) dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZAAFD24.HL.LH_S2 24x24-bit signed fraction (1.23) dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZAAFD32X16.H0.L1 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZAAFD32X16.H0.L1_S2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator: slot 2 version.
AE_MULZAAFD32X16.H1.L0 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator..
AE_MULZAAFD32X16.H1.L0_S2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZAAFD32X16.H2.L3 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZAAFD32X16.H2.L3_S2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator: slot 2 version.
AE_MULZAAFD32X16.H3.L2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator..
AE_MULZAAFD32X16.H3.L2_S2 32x16-bit signed fraction dual MAC with Addition/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZASD24.HH.LL 24x24-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation, zeroed accumulator.
AE_MULZASD24.HH.LL_S2 24x24-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZASD24.HL.LH 24x24-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation, zeroed accumulator.
AE_MULZASD24.HL.LH_S2 24x24-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZASD32X16.H1.L0 32x16-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation, zeroed accumulator..
AE_MULZASD32X16.H1.L0_S2 32x16-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZASD32X16.H3.L2 32x16-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation, zeroed accumulator..
AE_MULZASD32X16.H3.L2_S2 32x16-bit signed integer dual MAC with Addition/Subtraction and 64-bit result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZASFD24.HH.LL 24x24-bit signed fraction (1.23) dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZASFD24.HH.LL_S2 24x24-bit signed fraction (1.23) dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZASFD24.HL.LH 24x24-bit signed fraction (1.23) dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZASFD24.HL.LH_S2 24x24-bit signed fraction (1.23) dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZASFD32X16.H1.L0 32x16-bit signed fraction dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator..
AE_MULZASFD32X16.H1.L0_S2 32x16-bit signed fraction dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZASFD32X16.H3.L2 32x16-bit signed fraction dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator..
AE_MULZASFD32X16.H3.L2_S2 32x16-bit signed fraction dual MAC with Addition/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZSAD24.HH.LL 24x24-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation, zeroed accumulator.
AE_MULZSAD24.HH.LL_S2 24x24-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZSAD32X16.H1.L0 32x16-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation, zeroed accumulator..
AE_MULZSAD32X16.H1.L0_S2 32x16-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZSAD32X16.H3.L2 32x16-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation, zeroed accumulator..
AE_MULZSAD32X16.H3.L2_S2 32x16-bit signed integer dual MAC with Subtraction/Addition and 64-bit result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZSAFD24.HH.LL 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZSAFD24.HH.LL_S2 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZSAFD32X16.H1.L0 32x16-bit signed fraction dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator..
AE_MULZSAFD32X16.H1.L0_S2 32x16-bit signed fraction dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZSAFD32X16.H3.L2 32x16-bit signed fraction dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator..
AE_MULZSAFD32X16.H3.L2_S2 32x16-bit signed fraction dual MAC with Subtraction/Addition and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZSSD24.HH.LL 24x24-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation, zeroed accumulator.
AE_MULZSSD24.HH.LL_S2 24x24-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZSSD24.HL.LH 24x24-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation, zeroed accumulator.
AE_MULZSSD24.HL.LH_S2 24x24-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZSSD32X16.H1.L0 32x16-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation, zeroed accumulator..
AE_MULZSSD32X16.H1.L0_S2 32x16-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZSSD32X16.H3.L2 32x16-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation, zeroed accumulator..
AE_MULZSSD32X16.H3.L2_S2 32x16-bit signed integer dual MAC with Subtraction/Subtraction and 64-bit result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZSSFD16SS.11_00 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step, zeroed accumulator..
AE_MULZSSFD16SS.11_00_S2 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step, zeroed accumulator.: slot 2 version.
AE_MULZSSFD16SS.13_02 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step, zeroed accumulator..
AE_MULZSSFD16SS.13_02_S2 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step, zeroed accumulator.: slot 2 version.
AE_MULZSSFD16SS.33_22 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step, zeroed accumulator..
AE_MULZSSFD16SS.33_22_S2 16x16-bit signed fraction dual MAC with Subtraction/Subtraction and 32-bit (1.31) result, with saturation after every step, zeroed accumulator.: slot 2 version.
AE_MULZSSFD24.HH.LL 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZSSFD24.HH.LL_S2 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZSSFD24.HL.LH 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.
AE_MULZSSFD24.HL.LH_S2 24x24-bit signed fraction (1.23) dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version
AE_MULZSSFD32X16.H1.L0 32x16-bit signed fraction dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator..
AE_MULZSSFD32X16.H1.L0_S2 32x16-bit signed fraction dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version.
AE_MULZSSFD32X16.H3.L2 32x16-bit signed fraction dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator..
AE_MULZSSFD32X16.H3.L2_S2 32x16-bit signed fraction dual MAC with Subtraction/Subtraction and 64-bit (17.47) result, without saturation, zeroed accumulator.: slot 2 version.
AE_NAND bitwise NAND on two AE_DR register inputs
AE_NEG16S 4-way 16-bit negation with saturation
AE_NEG24S 2-way 24-bit negation with saturation
AE_NEG32 2-way 32-bit negation
AE_NEG32S 2-way 32-bit negation with saturation
AE_NEG64 64-bit negation
AE_NEG64S 64-bit negation with saturation
AE_NEGSQ56S 56-bit negation with saturation
AE_NSA64 compute left shift amount to normalize AE_DR register, write to AR register
AE_NSAZ16.0 compute left shift amount to normalize the lowest 16-bits of an AE_DR register
AE_NSAZ32.L compute left shift amount to normalize the lowest 32-bits of an AE_DR register
AE_OR bitwise OR on two AE_DR register inputs
AE_PKSR24 24-bit biquad acceleration
AE_PKSR32 32-bit biquad acceleration
AE_ROUND16X4F32SASYM Round asymmetrically and saturate two 1.31-bit fractions to 1.15-bits
AE_ROUND16X4F32SSYM Round symmetrically and saturate two 1.31-bit fractions to 1.15-bits
AE_ROUND24X2F48SASYM Round asymmetrically and saturate two 17.47-bit fractions to 1.23-bits
AE_ROUND24X2F48SSYM Round symmetrically and saturate two 17.47-bit fractions to 1.23-bits
AE_ROUND32X2F48SASYM Round asymmetrically and saturate two 17.47-bit fractions to 1.31-bits
AE_ROUND32X2F48SSYM Round symmetrically and saturate two 17.47-bit fractions to 1.31-bits
AE_ROUND32X2F64SASYM Round asymmetrically and saturate the 1.63-bit fraction to 1.31-bits
AE_ROUND32X2F64SSYM Round symmetrically and saturate the 1.63-bit fraction to 1.31-bits
AE_ROUNDSP16F24ASYM Round asymmetrically and saturate two 9.23-bit fractions to 1.15-bits
AE_ROUNDSP16F24SYM Round symmetrically and saturate two 9.23-bit fractions to 1.15-bits
AE_ROUNDSP16Q48X2ASYM Round asymmetrically and saturate two 17.47-bit fractions to 1.15-bits
AE_ROUNDSP16Q48X2SYM Round symmetrically and saturate two 17.47-bit fractions to 1.15-bits
AE_ROUNDSQ32F48ASYM Round asymmetrically and saturate a 17.47-bit fractions to 1.31-bits
AE_ROUNDSQ32F48SYM Round symmetrically and saturate a 17.47-bit fractions to 1.31-bits
AE_S16.0.I Store a 16-bit value from the lowest entry of the AE_DR register
AE_S16.0.IP Store a 16-bit value from the lowest entry of the AE_DR register
AE_S16.0.X Store a 16-bit value from the lowest entry of the AE_DR register
AE_S16.0.XC Store a 16-bit value from the lowest entry of the AE_DR register
AE_S16.0.XP Store a 16-bit value from the lowest entry of the AE_DR register
AE_S16M.L.I Store a 16-bit fractional values from the middle of the low entry of an AE_DR register
AE_S16M.L.IU Store a 16-bit fractional values from the middle of the low entry of an AE_DR register
AE_S16M.L.X Store a 16-bit fractional values from the middle of the low entry of an AE_DR register
AE_S16M.L.XC Store a 16-bit fractional values from the middle of the low entry of an AE_DR register
AE_S16M.L.XU Store a 16-bit fractional values from the middle of the low entry of an AE_DR register
AE_S16X2M.I Store a pair of 16-bit fractional values from the middle of each half of an AE_DR register
AE_S16X2M.IU Store a pair of 16-bit fractional values from the middle of each half of an AE_DR register
AE_S16X2M.X Store a pair of 16-bit fractional values from the middle of each half of an AE_DR register
AE_S16X2M.XC Store a pair of 16-bit fractional values from the middle of each half of an AE_DR register
AE_S16X2M.XU Store a pair of 16-bit fractional values from the middle of each half of an AE_DR register
AE_S16X4.I Store four 16-bit values from the AE_DR register
AE_S16X4.IP Store four 16-bit values from the AE_DR register
AE_S16X4.RIC Store four 16-bit values from the AE_DR register
AE_S16X4.RIP Store four 16-bit values from the AE_DR register
AE_S16X4.X Store four 16-bit values from the AE_DR register
AE_S16X4.XC Store four 16-bit values from the AE_DR register
AE_S16X4.XP Store four 16-bit values from the AE_DR register
AE_S24RA64S.I Round asymmetrically a 17.47-bit fraction to 1.23-bits and store
AE_S24RA64S.IP Round asymmetrically a 17.47-bit fraction to 1.23-bits and store
AE_S24RA64S.X Round asymmetrically a 17.47-bit fraction to 1.23-bits and store
AE_S24RA64S.XC Round asymmetrically a 17.47-bit fraction to 1.23-bits and store
AE_S24RA64S.XP Round asymmetrically a 17.47-bit fraction to 1.23-bits and store
AE_S24X2RA64S.IP Round asymmetrically two 17.47-bit fractions to 1.23-bits and store
AE_S32.L.I Store a 32-bit value from the L entry of the AE_DR register
AE_S32.L.IP Store a 32-bit value from the L entry of the AE_DR register
AE_S32.L.X Store a 32-bit value from the L entry of the AE_DR register
AE_S32.L.XC Store a 32-bit value from the L entry of the AE_DR register
AE_S32.L.XP Store a 32-bit value from the L entry of the AE_DR register
AE_S32F24.L.I Store a 24-bit fractional value from the L entry of the AE_DR register
AE_S32F24.L.IP Store a 24-bit fractional value from the L entry of the AE_DR register
AE_S32F24.L.X Store a 24-bit fractional value from the L entry of the AE_DR register
AE_S32F24.L.XC Store a 24-bit fractional value from the L entry of the AE_DR register
AE_S32F24.L.XP Store a 24-bit fractional value from the L entry of the AE_DR register
AE_S32M.I Store a 32-bit fractional values from the middle of an AE_DR register
AE_S32M.IU Store a 32-bit fractional values from the middle of an AE_DR register
AE_S32M.X Store a 32-bit fractional values from the middle of an AE_DR register
AE_S32M.XC Store a 32-bit fractional values from the middle of an AE_DR register
AE_S32M.XU Store a 32-bit fractional values from the middle of an AE_DR register
AE_S32RA64S.I Round asymmetrically a 17.47-bit fraction to 1.31-bits and store
AE_S32RA64S.IP Round asymmetrically a 17.47-bit fraction to 1.31-bits and store
AE_S32RA64S.X Round asymmetrically a 17.47-bit fraction to 1.31-bits and store
AE_S32RA64S.XC Round asymmetrically a 17.47-bit fraction to 1.31-bits and store
AE_S32RA64S.XP Round asymmetrically a 17.47-bit fraction to 1.31-bits and store
AE_S32X2.I Store two 32-bit values from the AE_DR register
AE_S32X2.IP Store two 32-bit values from the AE_DR register
AE_S32X2.RIC Store two 32-bit values from the AE_DR register
AE_S32X2.RIP Store two 32-bit values from the AE_DR register
AE_S32X2.X Store two 32-bit values from the AE_DR register
AE_S32X2.XC Store two 32-bit values from the AE_DR register
AE_S32X2.XP Store two 32-bit values from the AE_DR register
AE_S32X2F24.I Store two 24-bit fractional values from the AE_DR register
AE_S32X2F24.IP Store two 24-bit fractional values from the AE_DR register
AE_S32X2F24.RIC Store two 24-bit fractional values from the AE_DR register
AE_S32X2F24.RIP Store two 24-bit fractional values from the AE_DR register
AE_S32X2F24.X Store two 24-bit fractional values from the AE_DR register
AE_S32X2F24.XC Store two 24-bit fractional values from the AE_DR register
AE_S32X2F24.XP Store two 24-bit fractional values from the AE_DR register
AE_S32X2RA64S.IP Round asymmetrically two 17.47-bit fractions to 1.31-bits and store
AE_S64.I Stores a 64-bit value from the AE_DR register
AE_S64.IP Stores a 64-bit value from the AE_DR register
AE_S64.X Stores a 64-bit value from the AE_DR register
AE_S64.XC Stores a 64-bit value from the AE_DR register
AE_S64.XP Stores a 64-bit value from the AE_DR register
AE_SA16X4.IC Store four 16-bit values from the AE_DR register
AE_SA16X4.IP Store four 16-bit values from the AE_DR register
AE_SA16X4.RIC Store four 16-bit values from the AE_DR register
AE_SA16X4.RIP Store four 16-bit values from the AE_DR register
AE_SA24.L.IC Stores the low 24-bits from the L entry of the AE_DR register
AE_SA24.L.IP Stores the low 24-bits from the L entry of the AE_DR register
AE_SA24.L.RIC Stores the low 24-bits from the L entry of the AE_DR register
AE_SA24.L.RIP Stores the low 24-bits from the L entry of the AE_DR register
AE_SA24X2.IC Stores the low 24-bits from each half of the AE_DR register
AE_SA24X2.IP Stores the low 24-bits from each half of the AE_DR register
AE_SA24X2.RIC Stores the low 24-bits from each half of the AE_DR register
AE_SA24X2.RIP Stores the low 24-bits from each half of the AE_DR register
AE_SA32X2.IC Store two 32-bit values from the AE_DR register
AE_SA32X2.IP Store two 32-bit values from the AE_DR register
AE_SA32X2.RIC Store two 32-bit values from the AE_DR register
AE_SA32X2.RIP Store two 32-bit values from the AE_DR register
AE_SA32X2F24.IC Store two 24-bit fractional values from the AE_DR register
AE_SA32X2F24.IP Store two 24-bit fractional values from the AE_DR register
AE_SA32X2F24.RIC Store two 24-bit fractional values from the AE_DR register
AE_SA32X2F24.RIP Store two 24-bit fractional values from the AE_DR register
AE_SA64NEG.FP Flush alignment register
AE_SA64POS.FP Flush alignment register
AE_SALIGN64.I Store a 64-bit value from the alignment register
AE_SAT16X4 Saturate four 32-bit integers to 16-bits
AE_SAT24S Saturate two 17.23-bit fractions to 1.23-bits
AE_SAT48S Saturate a 17.47-bit fraction to 1.47-bits
AE_SATQ56S Saturate a 9.55-bit fraction to 1.55-bits
AE_SB store low bits of AR register to bit stream, count in state register, with AR register update in case of memory store
AE_SB.IC store low bits of AR register to bit stream, count in state register, with AR register update in case of memory store
AE_SB.IP store low bits of AR register to bit stream, count in state register, with AR register update in case of memory store
AE_SBF flush remaining bits from state register to the stream in memory
AE_SBF.IC flush remaining bits from state register to the stream in memory
AE_SBF.IP flush remaining bits from state register to the stream in memory
AE_SBI store low bits of AR register to bit stream, count in immediate, with AR register update in case of memory store
AE_SBI.IC store low bits of AR register to bit stream, count in immediate, with AR register update in case of memory store
AE_SBI.IP store low bits of AR register to bit stream, count in immediate, with AR register update in case of memory store
AE_SEL16I Combine elements from two input registers into the output register
AE_SEL16I.N Restricted version of AE_SEL16I
AE_SEXT32 Sign extend based on immediate
AE_SEXT32X2D16.10 ITU intrinsic L_deposit_l
AE_SEXT32X2D16.32 ITU intrinsic L_deposit_l
AE_SHA32 swaps bytes in each halfword of 32-bit AR register
AE_SHORTSWAP Reverse the order of the four, 16-bit elements in the register
AE_SLAA16S 4-way bidirectional shift, saturating left (arithmetic sign-extending) by AR register
AE_SLAA32 2-way bidirectional shift, left (arithmetic sign-extending) by AR register
AE_SLAA32S 2-way bidirectional shift, saturating left (arithmetic sign-extending) by AR register
AE_SLAA64 64-bit bidirectional shift left by AR register
AE_SLAA64S 64-bit saturating bidirectional arithmetic shift left by AR register
AE_SLAAQ56 56-bit arithmetic bidirectional shift left by AR register
AE_SLAASQ56S 56-bit arithmetic bidirectional signed shift left by AR register, with saturation
AE_SLAI16S 4-way saturating shift left (arithmetic) by immediate
AE_SLAI24 2-way 24-bit shift left by immediate
AE_SLAI24S 2-way 24-bit signed shift left by immediate, with saturation
AE_SLAI32 2-way shift left by immediate
AE_SLAI32S 2-way saturating shift left (arithmetic) by immediate
AE_SLAI64 64-bit shift left by immediate
AE_SLAI64S 64-bit saturating arithmetic shift left by immediate
AE_SLAISQ56S 56-bit arithmetic signed shift left by immediate, with saturation
AE_SLAS24 2-way bidirectional 24-bit shift left arithmetic by shift amount register
AE_SLAS24S 2-way bidirectional 24-bit signed arithmetic shift left by shift amount register, with saturation
AE_SLAS32 2-way bidirectional shift, left (arithmetic sign-extending) by shift amount register
AE_SLAS32S 2-way saturating bidirectional shift, left (arithmetic sign-extending) by shift amount register
AE_SLAS64 64-bit bidirectional shift, left (arithmetic sign-extending) by shift amount register
AE_SLAS64S saturating 64-bit bidirectional shift, left (arithmetic sign-extending) by shift amount register
AE_SLASQ56 56-bit arithmetic bidirectional shift left by shift amount register
AE_SLASSQ56S 56-bit signed bidirectional arithmetic shift left by shift amount register, with saturation
AE_SRA64_32 Convert a 1.31 into a 17.47 and shift right
AE_SRAA16RS 4-way bidirectional saturating right shift (arithmetic sign-extending) by AR register with rounding
AE_SRAA16S 4-way bidirectional shift, saturating right (arithmetic sign-extending) by AR register
AE_SRAA32 2-way bidirectional shift, right (logical zero-extending) by AR register
AE_SRAA32RS 2-way shift right (arithmetic sign-extending) by AR register with rounding
AE_SRAA32S 2-way shift right (arithmetic sign-extending) by AR register
AE_SRAA64 64-bit arithmetic bidirectional shift right by AR register
AE_SRAAQ56 56-bit arithmetic bidirectional shift right by AR register
AE_SRAI16 4-way shift right (arithmetic sign-extending) by immediate
AE_SRAI16R 4-way shift right (arithmetic sign-extending) by immediate with rounding
AE_SRAI24 2-way shift 24-bit right (arithmetic sign-extending) by immediate
AE_SRAI32 2-way shift right (arithmetic sign-extending) by immediate
AE_SRAI32R 2-way shift right (arithmetic sign-extending) by immediate with rounding
AE_SRAI64 64-bit arithmetic shift right by immediate
AE_SRAS24 2-way bidirectional 24-bit shift right arithmetic by shift amount register
AE_SRAS32 2-way bidirectional shift, right (arithmetic sign-extending) by shift amount register
AE_SRAS64 64-bit bidirectional shift, right (arithmetic sign-extending) by shift amount register
AE_SRASQ56 56-bit arithmetic bidirectional shift right by shift amount register
AE_SRLA32 2-way bidirectional shift, right (logical zero-extending) by AR register
AE_SRLA64 64-bit logical bidirectional shift right by AR register
AE_SRLAQ56 56-bit logical bidirectional shift right by AR register
AE_SRLI24 2-way shift 24-bit right (logical zero-extending) by immediate
AE_SRLI32 2-way shift right (logical zero-extending) by immediate
AE_SRLI64 64-bit logical shift right by immediate
AE_SRLS24 2-way bidirectional 24-bit shift right logical by shift amount register
AE_SRLS32 2-way bidirectional shift, right (logical zero-extending) by shift amount register
AE_SRLS64 64-bit bidirectional shift, right (logical zero-extending) by shift amount register
AE_SRLSQ56 56-bit logical bidirectional shift right by shift amount register
AE_SUB16 4-way 16-bit subtraction
AE_SUB16S 4-way 16-bit signed, saturating subtraction
AE_SUB24S 2-way 24-bit signed, saturating subtraction
AE_SUB32 2-way 32-bit subtraction
AE_SUB32S 2-way 32-bit signed, saturating subtraction
AE_SUB64 64-bit subtraction
AE_SUB64S 64-bit signed subtraction with saturation
AE_SUBADD32 2-way 32-bit subtraction/addition
AE_SUBADD32S 2-way 32-bit signed, saturating subtraction/addition
AE_SUBSQ56S 56-bit signed subtraction with saturation
AE_TRUNCA16P24S.H Truncate a 9.23-bit fraction to 1.15-bits
AE_TRUNCA16P24S.L Truncate a 9.23-bit fraction to 1.15-bits
AE_TRUNCA32F64S.L Bidirectional arithmetic shift left by AR register and truncate and shift elements
AE_TRUNCA32Q48 Truncate a 17.47-bit fraction to 1.31-bits
AE_TRUNCA32X2F64S Bidirectional arithmetic shift left by AR register and truncate
AE_TRUNCI32F64S.L Shift left by immediate and truncate and shift elements
AE_TRUNCI32X2F64S Shift left by immediate and truncate
AE_TRUNCP16 Truncate two 9.23-bit fractions to 1.15-bits
AE_TRUNCP24A32X2 2-way truncate of 1.31-bit fraction in AR registers to 1.23-bits
AE_TRUNCP24Q48X2 2-way truncate of 17.47-bit fraction to 1.23-bits
AE_TRUNCQ32 Truncate the bottom 16 bits of a 17.47-bit fraction
AE_VLDL16C 16-bit conditional bit stream load for variable-length decode
AE_VLDL16C.IC 16-bit conditional bit stream load for variable-length decode
AE_VLDL16C.IP 16-bit conditional bit stream load for variable-length decode
AE_VLDL16T 16-bit table entry load for variable-length decode
AE_VLDL32T 32-bit table entry load for variable-length decode
AE_VLDSHT set Huffman Table for variable-length decode
AE_VLEL16T 16-bit table entry load for variable-length encode, indicating if table load complete
AE_VLEL32T 32-bit table entry load for variable-length encode, indicating if table load complete
AE_VLES16C 16-bit conditional bit stream store for variable-length encode
AE_VLES16C.IC 16-bit conditional bit stream store for variable-length encode
AE_VLES16C.IP 16-bit conditional bit stream store for variable-length encode
AE_XOR bitwise XOR on two AE_DR register inputs
AE_ZALIGN64 Zero alignment register
ALL4 All 4 Booleans True
ALL8 All 8 Booleans True
AND Bitwise Logical And
ANDB Boolean And
ANDBC Boolean And with Complement
ANY4 Any 4 Booleans True
ANY8 Any 8 Booleans True
BALL Branch if All Bits Set
BALL.W18 Branch if All Bits Set
BANY Branch if Any Bit Set
BANY.W18 Branch if Any Bit Set
BBC Branch if Bit Clear
BBC.W18 Branch if Bit Clear
BBCI Branch if Bit Clear Immediate
BBCI.W18 Branch if Bit Clear Immediate
BBS Branch if Bit Set
BBS.W18 Branch if Bit Set
BBSI Branch if Bit Set Immediate
BBSI.W18 Branch if Bit Set Immediate
BEQ Branch if Equal
BEQ.W18 Branch if Equal
BEQI Branch if Equal Immediate
BEQI.W18 Branch if Equal Immediate
BEQZ Branch if Equal to Zero
BEQZ.N Narrow Branch if Equal Zero
BEQZ.W18 Branch if Equal to Zero
BF Branch if False
BGE Branch if Greater Than or Equal
BGE.W18 Branch if Greater Than or Equal
BGEI Branch if Greater Than or Equal Immediate
BGEI.W18 Branch if Greater Than or Equal Immediate
BGEU Branch if Greater Than or Equal Unsigned
BGEU.W18 Branch if Greater Than or Equal Unsigned
BGEUI Branch if Greater Than or Equal Unsigned Immediate
BGEUI.W18 Branch if Greater Than or Equal Unsigned Immediate
BGEZ Branch if Greater Than or Equal to Zero
BGEZ.W18 Branch if Greater Than or Equal to Zero
BLT Branch if Less Than
BLT.W18 Branch if Less Than
BLTI Branch if Less Than Immediate
BLTI.W18 Branch if Less Than Immediate
BLTU Branch if Less Than Unsigned
BLTU.W18 Branch if Less Than Unsigned
BLTUI Branch if Less Than Unsigned Immediate
BLTUI.W18 Branch if Less Than Unsigned Immediate
BLTZ Branch if Less Than Zero
BLTZ.W18 Branch if Less Than Zero
BNALL Branch if Not-All Bits Set
BNALL.W18 Branch if Not-All Bits Set
BNE Branch if Not Equal
BNE.W18 Branch if Not Equal
BNEI Branch if Not Equal Immediate
BNEI.W18 Branch if Not Equal Immediate
BNEZ Branch if Not-Equal to Zero
BNEZ.N Narrow Branch if Not Equal Zero
BNEZ.W18 Branch if Not-Equal to Zero
BNONE Branch if No Bit Set
BNONE.W18 Branch if No Bit Set
BREAK Breakpoint
BREAK.N Narrow Breakpoint
BT Branch if True
CALL0 Non-windowed Call
CALL4 Call PC-relative, Rotate Window by 4
CALL8 Call PC-relative, Rotate Window by 8
CALL12 Call PC-relative, Rotate Window by 12
CALLX0 Non-windowed Call Register
CALLX4 Call Register, Rotate Window by 4
CALLX8 Call Register, Rotate Window by 8
CALLX12 Call Register, Rotate Window by 12
CLAMPS Signed Clamp
CLRB_EXPSTATE Clear Bit of State EXPSTATE
DHI Data Cache Hit Invalidate
DHU Data Cache Hit Unlock
DHWB Data Cache Hit Writeback
DHWBI Data Cache Hit Writeback Invalidate
DII Data Cache Index Invalidate
DIU Data Cache Index Unlock
DIWB Data Cache Index Write Back
DIWBI Data Cache Index Write Back Invalidate
DIWBUI.P Data Cache Empty
DPFL Data Cache Prefetch and Lock
DPFR Data Cache Prefetch for Read
DPFRO Data Cache Prefetch for Read Once
DPFW Data Cache Prefetch for Write
DPFWO Data Cache Prefetch for Write Once
DSYNC Load/Store Synchronize
ENTRY Subroutine Entry
ESYNC Execute Synchronize
EXCW Exception Wait
EXTUI Extract Unsigned Immediate
EXTW External Wait
IDTLB Invalidate Data TLB Entry
IHI Instruction Cache Hit Invalidate
IHU Instruction Cache Hit Unlock
III Instruction Cache Index Invalidate
IITLB Invalidate Instruction TLB Entry
IIU Instruction Cache Index Unlock
ILL Illegal Instruction
ILL.N Narrow Illegal Instruction
IPF Instruction Cache Prefetch
IPFL Instruction Cache Prefetch and Lock
ISYNC Instruction Fetch Synchronize
J Unconditional Jump
JX Unconditional Jump Register
L8UI Load 8-bit Unsigned
L16SI Load 16-bit Signed
L16UI Load 16-bit Unsigned
L32AI Load 32-bit Acquire
L32E Load 32-bit for Window Exceptions
L32I Load 32-bit
L32I.N Narrow Load 32-bit
L32R Load 32-bit PC-Relative
LDCT Load Data Cache Tag
LDDEC Load with Autodecrement
LDDR32.P Load to DDR Register
LDINC Load with Autoincrement
LICT Load Instruction Cache Tag
LICW Load Instruction Cache Word
LOOP Loop
LOOPGTZ Loop if Greater Than Zero
LOOPNEZ Loop if Not-Equal Zero
MAX Maximum Value
MAXU Maximum Value Unsigned
MEMW Memory Wait
MIN Minimum Value
MINU Minimum Value Unsigned
MOV.N Narrow Move
MOVEQZ Move if Equal to Zero
MOVF Move if False
MOVGEZ Move if Greater Than or Equal to Zero
MOVI Move Immediate
MOVI.N Narrow Move Immediate
MOVLTZ Move if Less Than Zero
MOVNEZ Move if Not-Equal to Zero
MOVSP Move to Stack Pointer
MOVT Move if True
MUL.AA.HH Signed Multiply
MUL.AA.HL Signed Multiply
MUL.AA.LH Signed Multiply
MUL.AA.LL Signed Multiply
MUL.AD.HH Signed Multiply
MUL.AD.HL Signed Multiply
MUL.AD.LH Signed Multiply
MUL.AD.LL Signed Multiply
MUL.DA.HH Signed Multiply
MUL.DA.HL Signed Multiply
MUL.DA.LH Signed Multiply
MUL.DA.LL Signed Multiply
MUL.DD.HH Signed Multiply
MUL.DD.HL Signed Multiply
MUL.DD.LH Signed Multiply
MUL.DD.LL Signed Multiply
MUL16S Multiply 16-bit Signed
MUL16U Multiply 16-bit Unsigned
MULA.AA.HH Signed Multiply/Accumulate
MULA.AA.HL Signed Multiply/Accumulate
MULA.AA.LH Signed Multiply/Accumulate
MULA.AA.LL Signed Multiply/Accumulate
MULA.AD.HH Signed Multiply/Accumulate
MULA.AD.HL Signed Multiply/Accumulate
MULA.AD.LH Signed Multiply/Accumulate
MULA.AD.LL Signed Multiply/Accumulate
MULA.DA.HH Signed Multiply/Accumulate
MULA.DA.HH.LDDEC Signed Multiply/Accumulate, Load with Autodecrement
MULA.DA.HH.LDINC Signed Multiply/Accumulate, Load with Autoincrement
MULA.DA.HL Signed Multiply/Accumulate
MULA.DA.HL.LDDEC Signed Multiply/Accumulate, Load with Autodecrement
MULA.DA.HL.LDINC Signed Multiply/Accumulate, Load with Autoincrement
MULA.DA.LH Signed Multiply/Accumulate
MULA.DA.LH.LDDEC Signed Multiply/Accumulate, Load with Autodecrement
MULA.DA.LH.LDINC Signed Multiply/Accumulate, Load with Autoincrement
MULA.DA.LL Signed Multiply/Accumulate
MULA.DA.LL.LDDEC Signed Multiply/Accumulate, Load with Autodecrement
MULA.DA.LL.LDINC Signed Multiply/Accumulate, Load with Autoincrement
MULA.DD.HH Signed Multiply/Accumulate
MULA.DD.HH.LDDEC Signed Multiply/Accumulate, Load with Autodecrement
MULA.DD.HH.LDINC Signed Multiply/Accumulate, Load with Autoincrement
MULA.DD.HL Signed Multiply/Accumulate
MULA.DD.HL.LDDEC Signed Multiply/Accumulate, Load with Autodecrement
MULA.DD.HL.LDINC Signed Multiply/Accumulate, Load with Autoincrement
MULA.DD.LH Signed Multiply/Accumulate
MULA.DD.LH.LDDEC Signed Multiply/Accumulate, Load with Autodecrement
MULA.DD.LH.LDINC Signed Multiply/Accumulate, Load with Autoincrement
MULA.DD.LL Signed Multiply/Accumulate
MULA.DD.LL.LDDEC Signed Multiply/Accumulate, Load with Autodecrement
MULA.DD.LL.LDINC Signed Multiply/Accumulate, Load with Autoincrement
MULL Multiply Low
MULS.AA.HH Signed Multiply/Subtract
MULS.AA.HL Signed Multiply/Subtract
MULS.AA.LH Signed Multiply/Subtract
MULS.AA.LL Signed Multiply/Subtract
MULS.AD.HH Signed Multiply/Subtract
MULS.AD.HL Signed Multiply/Subtract
MULS.AD.LH Signed Multiply/Subtract
MULS.AD.LL Signed Multiply/Subtract
MULS.DA.HH Signed Multiply/Subtract
MULS.DA.HL Signed Multiply/Subtract
MULS.DA.LH Signed Multiply/Subtract
MULS.DA.LL Signed Multiply/Subtract
MULS.DD.HH Signed Multiply/Subtract
MULS.DD.HL Signed Multiply/Subtract
MULS.DD.LH Signed Multiply/Subtract
MULS.DD.LL Signed Multiply/Subtract
MULSH Multiply Signed High
MULUH Multiply Unsigned High
NEG Negate
NOP No-operation
NOP.N Narrow No-operation
NSA Normalization Shift Amount
NSAU Normalization Shift Amount Unsigned
OR Bitwise Logical Or
ORB Boolean Or
ORBC Boolean Or with Complement
PDTLB Probe Data TLB
PITLB Probe Instruction TLB
QUOS Quotient Signed
QUOU Quotient Unsigned
RDTLB0 Read Data TLB Entry Virtual
RDTLB1 Read Data TLB Entry Translation
READ_IMPWIRE Read Import Wire IMPWIRE
REMS Remainder Signed
REMU Remainder Unsigned
RER Read ExternalRegister
RET Non-Windowed Return
RET.N Narrow Non-Windowed Return
RETW Windowed Return
RETW.N Narrow Windowed Return
RFDD Return from Debug and Dispatch
RFDE Return from Double Exception
RFDO Return from Debug Operation
RFE Return from Exception
RFI Return from High-Priority Interrupt
RFWO Return from Window Overflow
RFWU Return From Window Underflow
RITLB0 Read Instruction TLB Entry Virtual
RITLB1 Read Instruction TLB Entry Translation
ROTW Rotate Window
RSIL Read and Set Interrupt Level
RSR.243 Read Special Register 243
RSR.ACCHI Read Special Register ACCHI
RSR.ACCLO Read Special Register ACCLO
RSR.ATOMCTL Read Special Register ATOMCTL
RSR.BR Read Special Register BR
RSR.CCOMPARE0 Read Special Register CCOMPARE0
RSR.CCOMPARE1 Read Special Register CCOMPARE1
RSR.CCOUNT Read Special Register CCOUNT
RSR.CONFIGID0 Read Special Register CONFIGID0
RSR.CONFIGID1 Read Special Register CONFIGID1
RSR.CPENABLE Read Special Register CPENABLE
RSR.DBREAKA0 Read Special Register DBREAKA0
RSR.DBREAKA1 Read Special Register DBREAKA1
RSR.DBREAKC0 Read Special Register DBREAKC0
RSR.DBREAKC1 Read Special Register DBREAKC1
RSR.DDR Read Special Register DDR
RSR.DEBUGCAUSE Read Special Register DEBUGCAUSE
RSR.DEPC Read Special Register DEPC
RSR.EPC1 Read Special Register EPC1
RSR.EPC2 Read Special Register EPC2
RSR.EPC3 Read Special Register EPC3
RSR.EPC4 Read Special Register EPC4
RSR.EPC5 Read Special Register EPC5
RSR.EPC6 Read Special Register EPC6
RSR.EPS2 Read Special Register EPS2
RSR.EPS3 Read Special Register EPS3
RSR.EPS4 Read Special Register EPS4
RSR.EPS5 Read Special Register EPS5
RSR.EPS6 Read Special Register EPS6
RSR.EXCCAUSE Read Special Register EXCCAUSE
RSR.EXCSAVE1 Read Special Register EXCSAVE1
RSR.EXCSAVE2 Read Special Register EXCSAVE2
RSR.EXCSAVE3 Read Special Register EXCSAVE3
RSR.EXCSAVE4 Read Special Register EXCSAVE4
RSR.EXCSAVE5 Read Special Register EXCSAVE5
RSR.EXCSAVE6 Read Special Register EXCSAVE6
RSR.EXCVADDR Read Special Register EXCVADDR
RSR.IBREAKA0 Read Special Register IBREAKA0
RSR.IBREAKA1 Read Special Register IBREAKA1
RSR.IBREAKENABLE Read Special Register IBREAKENABLE
RSR.ICOUNT Read Special Register ICOUNT
RSR.ICOUNTLEVEL Read Special Register ICOUNTLEVEL
RSR.INTENABLE Read Special Register INTENABLE
RSR.INTERRUPT Read Special Register INTERRUPT
RSR.LBEG Read Special Register LBEG
RSR.LCOUNT Read Special Register LCOUNT
RSR.LEND Read Special Register LEND
RSR.LITBASE Read Special Register LITBASE
RSR.M0 Read Special Register M0
RSR.M1 Read Special Register M1
RSR.M2 Read Special Register M2
RSR.M3 Read Special Register M3
RSR.MEMCTL Read Special Register MEMCTL
RSR.MISC0 Read Special Register MISC0
RSR.MISC1 Read Special Register MISC1
RSR.PREFCTL Read Special Register PREFCTL
RSR.PRID Read Special Register PRID
RSR.PS Read Special Register PS
RSR.SAR Read Special Register SAR
RSR.SCOMPARE1 Read Special Register SCOMPARE1
RSR.VECBASE Read Special Register VECBASE
RSR.WINDOWBASE Read Special Register WINDOWBASE
RSR.WINDOWSTART Read Special Register WINDOWSTART
RSYNC Register Read Synchronize
RUR.AE_BITHEAD Read State AE_BITHEAD
RUR.AE_BITPTR Read State AE_BITPTR
RUR.AE_BITSUSED Read State AE_BITSUSED
RUR.AE_CBEGIN0 Read User Register CBEGIN0
RUR.AE_CEND0 Read User Register CEND0
RUR.AE_CWRAP Read User Register CWRAP
RUR.AE_CW_SD_NO Read User Register AE_CW_SD_NO
RUR.AE_FIRST_TS Read State AE_FIRST_TS
RUR.AE_NEXTOFFSET Read State AE_NEXTOFFSET
RUR.AE_OVERFLOW Read State AE_OVERFLOW
RUR.AE_OVF_SAR Read User Register AE_OVF_SAR
RUR.AE_SAR Read State AE_SAR
RUR.AE_SEARCHDONE Read State AE_SEARCHDONE
RUR.AE_TABLESIZE Read State AE_TABLESIZE
RUR.AE_TS_FTS_BU_BP Read User Register AE_TS_FTS_BU_BP
RUR.EXPSTATE Read State EXPSTATE
S8I Store 8-bit
S16I Store 16-bit
S32C1I Store 32-bit Compare Conditional
S32E Store 32-bit for Window Exceptions
S32I Store 32-bit
S32I.N Narrow Store 32-bit
S32NB Store 32-bit Non-Buffered
S32RI Store 32-bit Release
SDCT Store Data Cache Tag
SDDR32.P Store from DDR Register
SETB_EXPSTATE Set Bit of State EXPSTATE
SEXT Sign Extend
SICT Store Instruction Cache Tag
SICW Store Instruction Cache Word
SIMCALL Simulator Call
SLL Shift Left Logical
SLLI Shift Left Logical Immediate
SRA Shift Right Arithmetic
SRAI Shift Right Arithmetic Immediate
SRC Shift Right Combined
SRL Shift Right Logical
SRLI Shift Right Logical Immediate
SSA8B Set Shift Amount for BE Byte Shift
SSA8L Set Shift Amount for LE Byte Shift
SSAI Set Shift Amount Immediate
SSL Set Shift Amount for Left Shift
SSR Set Shift Amount for Right Shift
SUB Subtract
SUBX2 Subtract with Shift by 1
SUBX4 Subtract with Shift by 2
SUBX8 Subtract with Shift by 3
SYSCALL System Call
UMUL.AA.HH Unsigned Multiply
UMUL.AA.HL Unsigned Multiply
UMUL.AA.LH Unsigned Multiply
UMUL.AA.LL Unsigned Multiply
WAITI Wait for Interrupt
WDTLB Write Data TLB Entry
WER Write ExternalRegister
WITLB Write Instruction TLB Entry
WRMSK_EXPSTATE Write State EXPSTATE With Mask
WSR.ACCHI Write Special Register ACCHI
WSR.ACCLO Write Special Register ACCLO
WSR.ATOMCTL Write Special Register ATOMCTL
WSR.BR Write Special Register BR
WSR.CCOMPARE0 Write Special Register CCOMPARE0
WSR.CCOMPARE1 Write Special Register CCOMPARE1
WSR.CCOUNT Write Special Register CCOUNT
WSR.CPENABLE Write Special Register CPENABLE
WSR.DBREAKA0 Write Special Register DBREAKA0
WSR.DBREAKA1 Write Special Register DBREAKA1
WSR.DBREAKC0 Write Special Register DBREAKC0
WSR.DBREAKC1 Write Special Register DBREAKC1
WSR.DDR Write Special Register DDR
WSR.DEBUGCAUSE Write Special Register DEBUGCAUSE
WSR.DEPC Write Special Register DEPC
WSR.EPC1 Write Special Register EPC1
WSR.EPC2 Write Special Register EPC2
WSR.EPC3 Write Special Register EPC3
WSR.EPC4 Write Special Register EPC4
WSR.EPC5 Write Special Register EPC5
WSR.EPC6 Write Special Register EPC6
WSR.EPS2 Write Special Register EPS2
WSR.EPS3 Write Special Register EPS3
WSR.EPS4 Write Special Register EPS4
WSR.EPS5 Write Special Register EPS5
WSR.EPS6 Write Special Register EPS6
WSR.EXCCAUSE Write Special Register EXCCAUSE
WSR.EXCSAVE1 Write Special Register EXCSAVE1
WSR.EXCSAVE2 Write Special Register EXCSAVE2
WSR.EXCSAVE3 Write Special Register EXCSAVE3
WSR.EXCSAVE4 Write Special Register EXCSAVE4
WSR.EXCSAVE5 Write Special Register EXCSAVE5
WSR.EXCSAVE6 Write Special Register EXCSAVE6
WSR.EXCVADDR Write Special Register EXCVADDR
WSR.IBREAKA0 Write Special Register IBREAKA0
WSR.IBREAKA1 Write Special Register IBREAKA1
WSR.IBREAKENABLE Write Special Register IBREAKENABLE
WSR.ICOUNT Write Special Register ICOUNT
WSR.ICOUNTLEVEL Write Special Register ICOUNTLEVEL
WSR.INTCLEAR Write Special Register INTCLEAR
WSR.INTENABLE Write Special Register INTENABLE
WSR.INTSET Write Special Register INTSET
WSR.LBEG Write Special Register LBEG
WSR.LCOUNT Write Special Register LCOUNT
WSR.LEND Write Special Register LEND
WSR.LITBASE Write Special Register LITBASE
WSR.M0 Write Special Register M0
WSR.M1 Write Special Register M1
WSR.M2 Write Special Register M2
WSR.M3 Write Special Register M3
WSR.MEMCTL Write Special Register MEMCTL
WSR.MISC0 Write Special Register MISC0
WSR.MISC1 Write Special Register MISC1
WSR.MMID Write Special Register MMID
WSR.PREFCTL Write Special Register PREFCTL
WSR.PS Write Special Register PS
WSR.SAR Write Special Register SAR
WSR.SCOMPARE1 Write Special Register SCOMPARE1
WSR.VECBASE Write Special Register VECBASE
WSR.WINDOWBASE Write Special Register WINDOWBASE
WSR.WINDOWSTART Write Special Register WINDOWSTART
WUR.AE_BITHEAD Write State AE_BITHEAD
WUR.AE_BITPTR Write State AE_BITPTR
WUR.AE_BITSUSED Write State AE_BITSUSED
WUR.AE_CBEGIN0 Write User Register CBEGIN0
WUR.AE_CEND0 Write User Register CEND0
WUR.AE_CWRAP Write User Register CWRAP
WUR.AE_CW_SD_NO Write User Register AE_CW_SD_NO
WUR.AE_FIRST_TS Write State AE_FIRST_TS
WUR.AE_NEXTOFFSET Write State AE_NEXTOFFSET
WUR.AE_OVERFLOW Write State AE_OVERFLOW
WUR.AE_OVF_SAR Write User Register AE_OVF_SAR
WUR.AE_SAR Write State AE_SAR
WUR.AE_SEARCHDONE Write State AE_SEARCHDONE
WUR.AE_TABLESIZE Write State AE_TABLESIZE
WUR.AE_TS_FTS_BU_BP Write User Register AE_TS_FTS_BU_BP
WUR.EXPSTATE Write EXPSTATE
XOR Bitwise Logical Exclusive Or
XORB Boolean Exclusive Or
XSR.ACCHI Exchange Special Register ACCHI
XSR.ACCLO Exchange Special Register ACCLO
XSR.ATOMCTL Exchange Special Register ATOMCTL
XSR.BR Exchange Special Register BR
XSR.CCOMPARE0 Exchange Special Register CCOMPARE0
XSR.CCOMPARE1 Exchange Special Register CCOMPARE1
XSR.CCOUNT Exchange Special Register CCOUNT
XSR.CPENABLE Exchange Special Register CPENABLE
XSR.DBREAKA0 Exchange Special Register DBREAKA0
XSR.DBREAKA1 Exchange Special Register DBREAKA1
XSR.DBREAKC0 Exchange Special Register DBREAKC0
XSR.DBREAKC1 Exchange Special Register DBREAKC1
XSR.DDR Exchange Special Register DDR
XSR.DEBUGCAUSE Exchange Special Register DEBUGCAUSE
XSR.DEPC Exchange Special Register DEPC
XSR.EPC1 Exchange Special Register EPC1
XSR.EPC2 Exchange Special Register EPC2
XSR.EPC3 Exchange Special Register EPC3
XSR.EPC4 Exchange Special Register EPC4
XSR.EPC5 Exchange Special Register EPC5
XSR.EPC6 Exchange Special Register EPC6
XSR.EPS2 Exchange Special Register EPS2
XSR.EPS3 Exchange Special Register EPS3
XSR.EPS4 Exchange Special Register EPS4
XSR.EPS5 Exchange Special Register EPS5
XSR.EPS6 Exchange Special Register EPS6
XSR.EXCCAUSE Exchange Special Register EXCCAUSE
XSR.EXCSAVE1 Exchange Special Register EXCSAVE1
XSR.EXCSAVE2 Exchange Special Register EXCSAVE2
XSR.EXCSAVE3 Exchange Special Register EXCSAVE3
XSR.EXCSAVE4 Exchange Special Register EXCSAVE4
XSR.EXCSAVE5 Exchange Special Register EXCSAVE5
XSR.EXCSAVE6 Exchange Special Register EXCSAVE6
XSR.EXCVADDR Exchange Special Register EXCVADDR
XSR.IBREAKA0 Exchange Special Register IBREAKA0
XSR.IBREAKA1 Exchange Special Register IBREAKA1
XSR.IBREAKENABLE Exchange Special Register IBREAKENABLE
XSR.ICOUNT Exchange Special Register ICOUNT
XSR.ICOUNTLEVEL Exchange Special Register ICOUNTLEVEL
XSR.INTENABLE Exchange Special Register INTENABLE
XSR.LBEG Exchange Special Register LBEG
XSR.LCOUNT Exchange Special Register LCOUNT
XSR.LEND Exchange Special Register LEND
XSR.LITBASE Exchange Special Register LITBASE
XSR.M0 Exchange Special Register M0
XSR.M1 Exchange Special Register M1
XSR.M2 Exchange Special Register M2
XSR.M3 Exchange Special Register M3
XSR.MEMCTL Exchange Special Register MEMCTL
XSR.MISC0 Exchange Special Register MISC0
XSR.MISC1 Exchange Special Register MISC1
XSR.PREFCTL Exchange Special Register PREFCTL
XSR.PS Exchange Special Register PS
XSR.SAR Exchange Special Register SAR
XSR.SCOMPARE1 Exchange Special Register SCOMPARE1
XSR.VECBASE Exchange Special Register VECBASE
XSR.WINDOWBASE Exchange Special Register WINDOWBASE
XSR.WINDOWSTART Exchange Special Register WINDOWSTART