AE_MULFD24X2.FIR.H — Quad 24x24-bit signed fractional (1.23) multiply into two 64-bit (17.47) results, with operands selected for FIR computations.

Instruction Word

Slot
ae2_slot1
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_MULFD24X2.FIR.H 0110
ae_fld_mul_q0 3210
ae_fld_mul_x4_q1 3210
ae_fld_mul_d0 3210
ae_fld_mul_d1 3210
ae_fld_mul_x4_d2 3210

Assembler Syntax

AE_MULFD24X2.FIR.H aed0..15(ae_mul_q0), aed0..15(ae_mul_q1), aed0..15(ae_mul_d0), aed0..15(ae_mul_d1), aed0..15(ae_mul_d2)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_MULFD24X2_FIR_H(ae_f64 q0 /*out*/, ae_f64 q1 /*out*/, ae_f24x2 d0, ae_f24x2 d1, ae_f24x2 c);

Description

AE_MULFD24X2.FIR.H is a quad, 24x24-bit signed fractional (1.23) multiplication into two 64-bit (17.47) results and no saturation. The operands are chosen to accelerate FIR computations.

q0 <-- d0.H * c.H + d0.L * c.L

q1 <-- d0.L * c.H + d1.H * c.L

Implementation Pipeline

In Out
ae_mul_d0 Mstage, ae_mul_d1 Mstage, ae_mul_d2 Mstage ae_mul_q0 Wstage, ae_mul_q1 Wstage

Protos that use AE_MULFD24X2.FIR.H

proto AE_MULFD24X2.FIR.H { out ae_f64 q0, out ae_f64 q1, in ae_f24x2 d0, in ae_f24x2 d1, in ae_f24x2 c }{}{
AE_MULFD24X2.FIR.H q0, q1, d0, d1, c;
}