WITLB — Write Instruction TLB Entry

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
WITLB 010100000110 0000
t 3210
s 3210

Assembler Syntax

WITLB at, as

C Syntax

#include <xtensa/tie/xt_mmu.h>

extern void XT_WITLB(unsigned art, unsigned ars);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

WITLB uses the contents of address register as to specify an instruction TLB entry and writes the contents of address register at into that entry. See for information on the address and result register formats for specific memory protection and translation options. The point at which the instruction TLB write is effected is implementation-specific. Any translation that would be affected by this write before the execution of an ISYNC instruction is therefore undefined.

WITLB is a privileged instruction.

Operation

if CRING != 0 then
	Exception (PrivilegedCause)
else
	(vpn, ei, wi) ← SplitInstTLBEntrySpec(AR[s])
	(ppn, sr, ring, ca) ← SplitInstEntry(wi, AR[t])
	InstTLB[wi][ei].ASID ← ASID(ring)
	InstTLB[wi][ei].VPN ← vpn
	InstTLB[wi][ei].PPN ← ppn
	InstTLB[wi][ei].SR ← sr
	InstTLB[wi][ei].CA ← ca
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)GenExcep(PrivilegedCause) if Exception Option

Implementation Pipeline

In Out
art Wstage, ars Estage

Protos that use WITLB

proto WITLB { in uint32 art, in uint32 ars }{}{
WITLB art, ars;
}