AE_S32X2RA64S.IP — Round asymmetrically two 17.47-bit fractions to 1.31-bits and store

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_S32X2RA64S.IP 1000000000010010 1010
ae_fld_ls_v2 3210
ae_fld_ls_v1 3210
s 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_S32X2RA64S.IP 00000000 0100
ae_fld_ls_v2 3210
ae_fld_ls_v1 3210
s 3210

Assembler Syntax

AE_S32X2RA64S.IP aed0..15(ae_ls_v2), aed0..15(ae_ls_v1), a0..15(ars)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_S32X2RA64S_IP(ae_f64 d2, ae_f64 d1, ae_f32x2 * a /*inout*/);

Description

AE_S32X2RA64S.IP round asymmetrically, saturate the two 17.47-bit values from AE_DR registers d0 and d1 to 1.31-bit values and store the result to memory. In case of saturation, state AE_OVERFLOW is set to 1. This operation is equivalent to an AE_ROUND32X2F64SASYM followed by a store.

The store forms a virtual address using the address register. This instruction also post-increments the address register by the immediate.

Implementation Pipeline

In Out
AE_OVERFLOW Wstage, ae_ls_v2 Mstage, ae_ls_v1 Mstage, ars Estage AE_OVERFLOW Wstage, ars Estage

Protos that use AE_S32X2RA64S.IP

proto AE_S32X2RA64S.IP { in ae_f64 d2, in ae_f64 d1, inout ae_f32x2 * a }{}{
AE_S32X2RA64S.IP d2, d1, a;
}