AE_VLDL16C.IP — 16-bit conditional bit stream load for variable-length decode

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_VLDL16C.IP 011101111110 10000100
s 3210

Assembler Syntax

AE_VLDL16C.IP a0..15(ars)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_VLDL16C_IP(const unsigned short * a /*inout*/);

Description

AE_VLDL16C.IP is a 16-bit conditional bit stream load for variable-length decode. 16 bits are loaded from the bit stream pointed to by a if they are needed to maintain the invariant that we have at least 16 bits of lookahead from the AE_BITPTR position in the AE_BITHEAD state register. In the event that a load occurs, a is advanced to refer to the next 16 bits in memory.

Implementation Pipeline

In Out
AE_NEXTOFFSET Wstage, AE_TABLESIZE Mstage, AE_BITPTR Mstage, AE_BITHEAD Mstage, AE_FIRST_TS Mstage, AE_BITSUSED Mstage, AE_SEARCHDONE Mstage, ars Estage AE_NEXTOFFSET Wstage, AE_TABLESIZE Mstage, AE_BITPTR Mstage, AE_BITHEAD Wstage, ars Mstage

Protos that use AE_VLDL16C.IP

proto AE_VLDL16C.IP { inout const uint16 * a }{}{
AE_VLDL16C.IP a;
}