Conditional Store Sync option

Conditional Store Sync option
Selected

This option adds the S32C1I instruction to ease multiprocessor synchronization by providing an atomic compare and store operation.

. This processor includes the conditional store synchronization instruction for multiprocessor synchronization, so you must implement PIF support for the RCW transaction. Further note, that the AXI and AHB bridges supplied by Cadence come with built-in support for this transaction that is implemented by locking the bus. Refer to the Xtensa Microprocessor Data Book for details.