SSR — Set Shift Amount for Right Shift

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
SSR 010000000000 00000000
s 3210

Assembler Syntax

SSR as

C Syntax

#include <xtensa/tie/xt_core.h>

extern void XT_SSR(int s);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

SSR sets the shift amount register (SAR) for a right shift (for example, SRL, SRA, or SRC). The least significant five bits of address register as are written to SAR. The most significant bit of SAR is cleared. This instruction is similar to a WSR.SAR, but differs in that only AR[s]4..0 is used, instead of AR[s]5..0.

Operation

sa ← AR[s]4..0
SAR ← 0||sa

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
ars Estage SAR Estage

Protos that use SSR

proto SSR { in int32 s }{}{
SSR s;
}
proto SSR_SRA { out int32 dst, in int32 src, in int32 amount }{}{
SSR amount;
SRA dst, src;
}
proto SSR_SRC { out int32 dst, in int32 src1, in int32 src2, in int32 amount }{}{
SSR amount;
SRC dst, src1, src2;
}
proto SSR_SRL { out uint32 dst, in uint32 src, in int32 amount }{}{
SSR amount;
SRL dst, src;
}