Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L32E | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||
t | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
r | 3 | 2 | 1 | 0 |
L32E at, as, -64..-4
extern int XT_L32E(const int * s, immediate o);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
L32E
is a 32-bit load instruction similar to L32I
but with semantics required by window overflow and window underflow exception handlers. In particular, memory access checking is done with PS.RING
instead of CRING
, and the offset used to form the virtual address is a 4-bit one-extended immediate. Therefore, the offset can specify multiples of four from -64 to -4. In configurations without the MMU Option
, there is no PS.RING
, and L32E
is similar to L32I
with a negative offset.
If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation or memory reference encounters an error (for example, protection violation or non-existent memory), the processor raises one of several exceptions .
Without the Unaligned Exception Option , the two least significant bits of the address are ignored. A reference to an address that is not 0 mod 4 produces the same result as a reference to the address with the least significant bits cleared. With the Unaligned Exception Option, such an access raises an exception.
L32E
is a privileged instruction.
if CRING != 0 then Exception (PrivilegedCause) else vAddr ← AR[s] + (126||r||02) ring ← if MMU Option then PS.RING else 0 (mem32, error) ← Load32Ring(vAddr, ring) if error then EXCVADDR ← vAddr Exception (LoadStoreErrorCause) else AR[t] ← mem32 endif endif