Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
REMS | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||
r | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
t | 3 | 2 | 1 | 0 |
REMS ar, as, at
extern unsigned XT_REMS(unsigned ars, unsigned art);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
REMS
performs a 32-bit two's complement division of the contents of address register as
by the contents of address register at
and writes the remainder to address register ar
. The ambiguity which exists when either address register as
or address register at
is negative is resolved by requiring the remainder to have the same sign as address register as
. If the contents of address register at
are zero, REMS
raises an Integer Divide by Zero exception instead of writing a result.
if AR[t] = 032 then Exception (IntegerDivideByZero) else AR[r] ← AR[s] rem AR[t] endif
In | Out |
---|---|
ars Estage , art Estage
|
arr Estage
|