Configure APB access to the Access Port module of the processor
The Enable APB Debug Access option adds an APB slave interface as specified by the AMBA 3 Advanced Peripheral Bus (APB) protocol. In addition to JTAG, the APB slave interface can be used to access debug functionality, for instance to read and write OCD registers, TRAX control, and Performance Counter registers. The APB slave interface operates on its own clock (PBCLK) which is asynchronous with respect to the CLK signal of the processor core and OCD.
With this option, Xtensa becomes a CoreSight-compatible component as viewed/accessed through the APB. The CoreSight registers and functionality are as described in the Xtensa Debug Guide