| Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| BEQZ | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| s | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| imm12 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BEQZ as, label
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
BEQZ branches if address register as is equal to zero. BEQZ provides 12 bits of target range instead of the eight bits available in most conditional branches.
The target instruction address of the branch is given by the address of the BEQZ instruction, plus the sign-extended 12-bit imm12 field of the instruction plus four. If register as is not equal to zero, execution continues with the next sequential instruction.
The inverse of BEQZ is BNEZ.
if AR[s] = 032 then nextPC ← PC + (imm121120||imm12) + 4 endif