| Slot Inst16b | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Format x16b - 16 bit(s) | 1 | 1 | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| BNEZ.N | 1 | 1 | 1 | 1 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| s | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| imm6 | 3 | 2 | 1 | 0 | 5 | 4 |
BNEZ.N as, label
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
This performs the same operation as the BNEZ instruction in a 16-bit encoding. BNEZ.N branches if address register as is not equal to zero. BNEZ.N provides six bits of target range instead of the 12 bits available in BNEZ.
The target instruction address of the branch is given by the address of the BNEZ.N instruction, plus the zero-extended 6-bit imm6 field of the instruction plus four. Because the offset is unsigned, this instruction can only be used to branch forward. If register as is equal to zero, execution continues with the next sequential instruction.
The inverse of BNEZ.N is BEQZ.N.
if AR[s] != 032 then nextPC ← PC + (026||imm6) + 4 endif