| Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| NSAU | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||
| t | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| s | 3 | 2 | 1 | 0 |
NSAU at, as
extern unsigned XT_NSAU(unsigned s);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
NSAU calculates the left shift amount that will normalize the unsigned contents of address register as and writes this amount (in the range 0 to 32) to address register at. If as contains 0, NSAU returns 32. Using SSL and SLL to shift as left by the NSAU result yields the smallest value for which bit 31 is set, unless as contains 0.
if AR[s] = 032 then AR[t] ← 32 else b4 ← AR[s]31..16 = 016 t3 ← if b4 then AR[s]15..0 else AR[s]31..16 b3 ← t315..8 = 08 t2 ← if b3 then t37..0 else t315..8 b2 ← t27..4 = 04 t1 ← if b2 then t23..0 else t27..4 b1 ← t13..2 = 02 b0 ← if b1 then t11 = 0 else t13 = 0 AR[t] ← 027||b4||b3||b2||b1||b0 endif
| In | Out |
|---|---|
ars Estage
|
art Estage
|