| Name | Value |
|---|---|
| Configuration Name | hifi3_hikey960 |
| Description | hifi3 hikey960 RF2 build |
| Built on XPG | 2018-02-10 00:36:11 PST |
| XPG Release | RG-2017.5 |
| XPG Build ID | 464161 |
| Target HW Build ID | 448360 |
| Target Hardware Version | LX6.0.2 |
| Platforms Built | linux,win32 |
| Name | Value |
|---|---|
| TIE Name | No user TIE |
| Option | Selection |
|---|---|
| HiFi3 Audio Engine DSP coprocessor instruction family | Selected |
| > HiFi3 Vector FP | Not Selected |
| Option | Selection |
|---|---|
| C Libraries | Newlib C Library |
| Software ABI | windowed |
| Hardware Floating Point ABI | Not Selected |
| Xtensa Tools should use Extended L32R | Not Selected |
| Build with reset handler at alternate reset base | Not Selected |
| Option | Selection |
|---|---|
| Global Clock Gating | Selected |
| Functional Unit Clock Gating | Selected |
| Asynchronous Reset | Selected |
| Register file implementation block | Flip-flops |
| Full scan | Selected |
| Size of L0 Loop Buffer (in bytes) | 256 |
| Semantic Data Gating selection | All |
| Enable Memory Data Gating | Selected |
| Power Shut-Off Domains selection | None |
| Power Shut-Off Core Retention selection | None |
| Option | Selection |
|---|---|
| Memory Protection/MMU | Region protection with translation |
| Option | Selection |
|---|---|
| MUL32 implementation selection | Pipelined + UH/SH |
| MUL16 | Selected |
| 16-bit MAC with 40 bit Accumulator | Selected |
| CLAMPS | Selected |
| 32 bit integer divider | Selected |
| Single Precision FP (coprocessor id 0) | Not Selected |
| Single+Double Precision FP (coprocessor id 0) | Not Selected |
| Non-IEEE Double Precision Floating Point Accelerator | Not Selected |
| Option | Selection |
|---|---|
| NSA/NSAU | Selected |
| MIN/MAX and MINU/MAXU | Selected |
| SEXT | Selected |
| DEPBITS | Not Selected |
| Enable Density Instructions | Selected |
| Boolean Registers | Selected |
| Enable Processor ID | Selected |
| TIE arbitrary byte enables | Selected |
| Zero-overhead loop instructions | Selected |
| Synchronize instruction | Selected |
| Conditional store synchronize instruction | Selected |
| Number of Coprocessors | 2 |
| Miscellaneous Special Register count | 2 |
| Thread Pointer | Not Selected |
| Option | Selection |
|---|---|
| Number of AR registers for call windows | 64 |
| Byte ordering (endianness) | Little Endian |
| Generate exception on unaligned load/store address | Handled by hardware |
| Max instruction width (bytes) | 8 |
| L32R hardware support option | Normal L32R |
| Pipeline length | 5 |
| Option | Selection |
|---|---|
| Processor Interface + External Bus selection | AXI3 |
| Asynchronous AMBA bridge | Not Selected |
| Request Control Depth | 4 |
| Request Data Depth | 8 |
| Response Depth | 8 |
| Option | Selection |
|---|---|
| Write buffer entries | 16 |
| Prioritize Load Before Store | Not Selected |
| Enable PIF Write Responses | Selected |
| Inbound PIF request buffer depth | 4 |
| PIF Request Attributes | Not Selected |
| Enable PIF Critical Word First | Selected |
| PIF Arbitrary Byte Enables | Selected |
| Enable Early Restart | Selected |
| Option | Selection |
|---|---|
| Cache Prefetch Entries | 8 |
| Enable Prefetch Directly to L1 | Not Selected |
| Option | Selection |
|---|---|
| Width of Instruction Fetch interface | 64 |
| Width of Data Memory/Cache interface | 64 |
| Width of Interface to instruction cache | 64 |
| Width of PIF interface | 64 |
| Option | Selection |
|---|---|
| GPIO32: 32-bit GPIO interface | Selected |
| QIF32: 32-bit Queue Interface | Not Selected |
| Option | Selection |
|---|---|
| Instruction Memory Error type | None |
| Data Memory Error type | None |
| Option | Selection |
|---|---|
| Instruction Cache size (Bytes) | 65536 |
| > Associativity | 4 |
| > Line size (Bytes) | 128 |
| > Line Locking | Selected |
| > Instruction Cache memory error | Not Selected |
| > Dynamic Way Disable | Not Selected |
| Option | Selection |
|---|---|
| Data Cache (Bytes) | 65536 |
| > Associativity | 4 |
| > Line size (Bytes) | 128 |
| > Write Back | Selected |
| > Line Locking | Selected |
| > Data Cache memory error | Not Selected |
| > Number of Data Cache Banks | 1 |
| > Dynamic Way Disable | Not Selected |
| Memory | Size | Address | Inbound PIF | Busy |
|---|---|---|---|---|
| Instruction RAM 0 | 32K | 0xe8080000 | Selected | Not Selected |
| Instruction RAM 1 | 16K | 0xe8088000 | Selected | Not Selected |
| Data RAM 0 | 32K | 0xe8058000 | Selected | Not Selected |
| Data RAM 1 | 128K | 0xe8060000 | Selected | Not Selected |
| Option | Selection |
|---|---|
| Count of Load/Store units | 1 |
| Connection box | Not Selected |
| Option | Selection |
|---|---|
| iDMA | Not Selected |
| Option | Selection |
|---|---|
| Debug | Selected |
| > Instruction address breakpoint registers | 2 |
| > Data address breakpoint registers | 2 |
| > On Chip Debug(OCD) | Selected |
| > Enable APB Debug Access | Selected |
| > External Debug Interrupt | Selected |
| > Number of Performance Counters | 4 |
| Option | Selection |
|---|---|
| Trace port (address trace and pipeline status) | Selected |
| Add data trace | Not Selected |
| TRAX Compressor | Included |
| Size of trace memory (bytes) | 4096 |
| TRAX ATB data interface | Not Selected |
| Enable sharing of TRAX memories | Not Selected |
| Option | Selection |
|---|---|
| Interrupt count | 32 |
| > Count of interrupt priority levels | 5 |
| > Timer count | 2 |
| > EXCM priority level (highest priority of efficiently C-callable handlers) | 3 |
| > Debug interrupt level | 5 |
| Interrupt | Type | Level | BInterrupt Pin |
|---|---|---|---|
| 0 | nmi | nmi | 0 |
| 1 | sw | 3 | |
| 2 | level | 3 | 1 |
| 3 | level | 3 | 2 |
| 4 | level | 3 | 3 |
| 5 | timer.0 | 3 | |
| 6 | timer.1 | 4 | |
| 7 | level | 3 | 4 |
| 8 | level | 2 | 5 |
| 9 | level | 2 | 6 |
| 10 | level | 2 | 7 |
| 11 | level | 2 | 8 |
| 12 | level | 1 | 9 |
| 13 | level | 1 | 10 |
| 14 | level | 1 | 11 |
| 15 | level | 1 | 12 |
| 16 | level | 1 | 13 |
| 17 | level | 1 | 14 |
| 18 | level | 1 | 15 |
| 19 | profiling | 3 | |
| 20 | level | 1 | 16 |
| 21 | level | 1 | 17 |
| 22 | level | 1 | 18 |
| 23 | level | 1 | 19 |
| 24 | level | 1 | 20 |
| 25 | level | 1 | 21 |
| 26 | level | 1 | 22 |
| 27 | level | 1 | 23 |
| 28 | level | 1 | 24 |
| 29 | writeerr | 3 | |
| 30 | level | 1 | 25 |
| 31 | level | 1 | 26 |
| Memory | Base Address | Size |
|---|---|---|
| System RAM | 0xc0000000 | 256M |
| System ROM | 0xd0000000 | 16M |
| Option | Selection |
|---|---|
| Automatically position vectors | Not Selected |
| Vector Layout Style | Xtensa Relocatable |
| Enable Relocatable Vectors | Selected |
| Alternate Static Vector Base Address | 0xc0000000 |
| Default Dynamic Vector Group VECBASE | 0xe8080400 |
| Vector | In Memory | Address | Prefix Bytes | Size Bytes |
|---|---|---|---|---|
| Reset vector | Instruction RAM 0 | 0xe8080000 | 0x0 | 0x300 |
| Vector | In Memory | Address | Prefix Bytes | Size Bytes |
|---|---|---|---|---|
| Window vector base | Instruction RAM 0 | 0xe8080400 | 0x0 | 0x178 |
| Level 2 vector | Instruction RAM 0 | 0xe8080580 | 0x8 | 0x38 |
| Level 3 vector | Instruction RAM 0 | 0xe80805c0 | 0x8 | 0x38 |
| Level 4 vector | Instruction RAM 0 | 0xe8080600 | 0x8 | 0x38 |
| Level 5 vector (Debug) | Instruction RAM 0 | 0xe8080640 | 0x8 | 0x38 |
| NMI vector | Instruction RAM 0 | 0xe80806c0 | 0x48 | 0x38 |
| Kernel vector | Instruction RAM 0 | 0xe8080700 | 0x8 | 0x38 |
| User vector | Instruction RAM 0 | 0xe8080740 | 0x8 | 0x38 |
| Double vector | Instruction RAM 0 | 0xe80807c0 | 0x48 | 0x40 |