AE_L32X2F24.IP — Load two 24-bit fractional values into the AE_DR register

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_L32X2F24.IP 1000000000011000 0 0111
ae_fld_ls_v 3210
s 3210
ae_fld_immls64pos 210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_L32X2F24.IP 11001100 1
ae_fld_ls_v 3210
s 3210
ae_fld_immls64pos 210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_L32X2F24.IP 00101100 1 0100
ae_fld_ls_v 3210
s 3210
ae_fld_immls64pos 210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_L32X2F24.IP 11001100 1
ae_fld_ls_v 3210
s 3210
ae_fld_immls64pos 210

Assembler Syntax

AE_L32X2F24.IP aed0..15(ae_ls_v), a0..15(ars), 0..56

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_L32X2F24_IP(ae_f24x2 d /*out*/, const ae_f24x2 * a /*inout*/, immediate off);

Description

AE_L32X2F24.IP loads two 24-bit values from memory into the AE_DR register. It forms a virtual address using the address register.

The load instruction reads the most significant 24 bits (3 bytes) of each 32-bit word and sign-extends them into 32-bits.

The intent is that the value in memory represents a 32-bit (1.31) fraction that gets truncated and placed into the AE_DR register as 9.23-bit fractions.

The data is placed in the AE_DR register d.

This instruction also post-increments the address register by the immediate value.

Implementation Pipeline

In Out
ars Estage ae_ls_v Mstage, ars Estage

Protos that use AE_L32X2F24.IP

proto AE_L32X2F24.IP { out ae_f24x2 d, inout const ae_f24x2 * a, in immediate off }{}{
AE_L32X2F24.IP d, a, off + 0;
}
proto ae_f24x2_loadip { out ae_f24x2 d, inout const ae_f24x2 * a, in immediate off }{}{
AE_L32X2F24.IP d, a, off + 0;
}
proto ae_p24x2f_loadip { out ae_p24x2f d, inout const ae_p24x2f * a, in immediate off }{}{
AE_L32X2F24.IP d, a, off + 0;
}