EXTUI — Extract Unsigned Immediate

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
EXTUI 100000000000000
r 3210
t 3210
sae 4 3210
op2 3 210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
EXTUI 000
r 3210
t 3210
sae 4 3210
op2 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
EXTUI 010 0000
r 3210
t 3210
sae 4 3210
op2 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
EXTUI 000
r 3210
t 3210
sae 4 3210
op2 3210

Assembler Syntax

EXTUI ar, at, shiftimm, maskimm

C Syntax

#include <xtensa/tie/xt_core.h>

extern unsigned XT_EXTUI(unsigned t, immediate i, immediate o);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

EXTUI performs an unsigned bit field extraction from a 32-bit register value. Specifically, it shifts the contents of address register at right by the shift amount shiftimm, which is a value 0..31 stored in bits 16 and 11..8 of the instruction word (the sa fields). The shift result is then ANDed with a mask of maskimm least-significant 1 bits and the result is written to address register ar. The number of mask bits, maskimm, may take the values 1..16, and is stored in the op2 field as maskimm-1. The bits extracted are therefore sa+op2..sa.

The operation of this instruction when sa+op2 > 31 is undefined and reserved for future use.

Operation

mask ← 031-op2||1op2+1
AR[r] ← (032||AR[t])31+sa..sa and mask

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
art Estage arr Estage

Protos that use EXTUI

proto EXTUI { out uint32 r, in uint32 t, in immediate i, in immediate o }{}{
EXTUI r, t, i + 0, o + 0;
}