BBSI — Branch if Bit Set Immediate

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
BBSI 111 0111
s 3210
bbi 4 3210
imm8 76543210

Assembler Syntax

BBSI as, 0..31, label

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

BBSI branches if the bit specified by the constant encoded in the bbi field of the instruction word is set in address register as. For little-endian processors, bit 0 is the least significant bit and bit 31 is the most significant bit. For big-endian processors, bit 0 is the most significant bit and bit 31 is the least significant bit. The bbi field is split, with bits 3..0 in bits 7..4 of the instruction word, and bit 4 in bit 12 of the instruction word.

The target instruction address of the branch is given by the address of the BBSI instruction, plus the sign-extended 8-bit imm8 field of the instruction plus four. If the specified bit is clear, execution continues with the next sequential instruction.

The inverse of BBSI is BBCI.

Operation

b ← bbi xor msbFirst5
if AR[s]b != 0 then
	nextPC ← PC + (imm8724||imm8) + 4
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)