Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L32R | 0 | 0 | 0 | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
t | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
imm16 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
L32R at, label
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
L32R
is a PC-relative 32-bit load from memory. It is typically used to load constant values into a register when the constant cannot be encoded in a MOVI
instruction.
L32R
forms a virtual address by adding the 16-bit one-extended constant value encoded in the instruction word shifted left by two to the address of the L32R
plus three with the two least significant bits cleared. Therefore, the offset can always specify 32-bit aligned addresses from -262141 to -4 bytes from the address of the L32R
instruction. 32 bits (four bytes) are read from the physical address. This data is then written to address register at
.
In the presence of the Extended L32R Option when LITBASE[0]
is clear, the instruction has the identical operation. When LITBASE[0]
is set, L32R
forms a virtual address by adding the 16-bit one extended constant value encoded in the instruction word shifted left by two to the literal base address indicated by the upper 20 bits of LITBASE
. The offset can specify 32-bit aligned addresses from -262144 to -4 bytes from the literal base address.
If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation or memory reference encounters an error (for example, protection violation or non-existent memory), the processor raises one of several exceptions .
It is not possible to specify an unaligned address.
If the Instruction Memory Access Option is configured, L32R
is one of only a few memory reference instructions that can access instruction RAM/ROM.
if Extended L32R Option and LITBASE0 then vAddr ← (LITBASE31..12||012) + (114||imm16||02) else vAddr ← ((PC + 3)31..2||02) + (114||imm16||02) endif (mem32, error) ← Load32(vAddr) if error then EXCVADDR ← vAddr Exception (LoadStoreErrorCause) else AR[t] ← mem32 endif