ADD — Add

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
ADD 1000000000001101 0000
r 3210
s 3210
t 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
ADD 01010000
r 3210
s 3210
t 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
ADD 10000000 0000
r 3210
s 3210
t 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
ADD 01010000
r 3210
s 3210
t 3210

Assembler Syntax

ADD ar, as, at

C Syntax

#include <xtensa/tie/xt_core.h>

extern int XT_ADD(int s, int t);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

ADD calculates the two's complement 32-bit sum of address registers as and at. The low 32 bits of the sum are written to address register ar. Arithmetic overflow is not detected.

ADD is a 24-bit instruction. The ADD.N density-option instruction performs the same operation in a 16-bit encoding.

Operation

AR[r] ← AR[s] + AR[t]

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
ars Estage, art Estage arr Estage

Protos that use ADD

proto ADD { out int32 r, in int32 s, in int32 t }{}{
ADD r, s, t;
}
proto AE_LP24.XU { out ae_p24x2s d, inout const ae_p24s * a, in int32 off }{}{
ADD a, a, off;
AE_L32.I d, a, 0;
}
proto AE_LP24F.XU { out ae_p24x2s d, inout const ae_p24f * a, in int32 off }{}{
ADD a, a, off;
AE_L32F24.I d, a, 0;
}
proto AE_LP24X2.XU { out ae_p24x2s d, inout const ae_p24x2s * a, in int32 off }{}{
ADD a, a, off;
AE_L32X2.I d, a, 0;
}
proto AE_LP24X2F.XU { out ae_p24x2s d, inout const ae_p24x2f * a, in int32 off }{}{
ADD a, a, off;
AE_L32X2F24.I d, a, 0;
}
proto AE_LQ56.XU { out ae_q56s d, inout const ae_q56s * a, in int32 off }{}{
ADD a, a, off;
AE_L64.I d, a, 0;
}
proto AE_SP24F.L.XU { in ae_p24x2s d, inout ae_p24f * a, in int32 off }{}{
ADD a, a, off;
AE_S32F24.L.I d, a, 0;
}
proto AE_SP24S.L.XU { in ae_p24x2s d, inout ae_p24s * a, in int32 off }{}{
ADD a, a, off;
AE_S32.L.I d, a, 0;
}
proto AE_SP24X2F.XU { in ae_p24x2s d, inout ae_p24x2f * a, in int32 off }{}{
ADD a, a, off;
AE_S32X2F24.I d, a, 0;
}
proto AE_SP24X2S.XU { in ae_p24x2s d, inout ae_p24x2s * a, in int32 off }{}{
ADD a, a, off;
AE_S32X2.I d, a, 0;
}
proto AE_SQ56S.XU { in ae_q56s d, inout ae_q56s * a, in int32 off }{}{
ADD a, a, off;
AE_S64.I d, a, 0;
}