AE_SRLI24 — 2-way shift 24-bit right (logical zero-extending) by immediate

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_SRLI24 1000000000001100 0 01
ae_fld_shift_d 3210
ae_fld_shift_d0 3210
ae_fld_osa32 43210

Slot
ae_slot2_0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_SRLI240010001
ae_fld_shift_d 3210
ae_fld_shift_d0 3210
ae_fld_osa32 4 3210

Assembler Syntax

AE_SRLI24 aed0..15(ae_shift_d), aed0..15(ae_shift_d0), 0..31

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_int24x2 AE_SRLI24(ae_int24x2 d0, immediate sa);

Description

AE_SRLI24 is a two-way logical (zero-extending) right shift of bits [23:0] of AE_DR register d0 by immediate, with result signed extended to 32-bits and placed in d.

Implementation Pipeline

In Out
ae_shift_d0 Mstage ae_shift_d Mstage

Protos that use AE_SRLI24

proto AE_SRLI24 { out ae_int24x2 d, in ae_int24x2 d0, in immediate sa }{}{
AE_SRLI24 d, d0, sa + 0;
}
proto AE_SRLIP24 { out ae_p24x2s d, in ae_p24x2s d0, in immediate sa }{}{
AE_SRLI24 d, d0, sa + 0;
}