SRC — Shift Right Combined

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
SRC 10000001 0000
r 3210
s 3210
t 3210

Assembler Syntax

SRC ar, as, at

C Syntax

#include <xtensa/tie/xt_core.h>

extern int XT_SRC(int s, int t);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

SRC performs a right shift of the concatenation of address registers as and at by the shift amount in SAR. The least significant 32 bits of the shift result are written to address register ar. A shift with a wider input than output is called a funnel shift. SRC directly performs right funnel shifts. Left funnel shifts are done by swapping the high and low operands to SRC and setting SAR to 32 minus the shift amount. The SSL and SSA8B instructions directly implement such SAR settings. Note the result of SRC is undefined if SAR > 32.

Operation

sa ← SAR5..0
AR[r] ← (AR[s]||AR[t])31+sa..sa

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
SAR Estage, ars Estage, art Estage arr Estage

Protos that use SRC

proto SRC { out int32 r, in int32 s, in int32 t }{}{
SRC r, s, t;
}
proto SSAI_SRC { out int32 dst, in int32 src1, in int32 src2, in immediate amount }{}{
SSAI amount + 0;
SRC dst, src1, src2;
}
proto SSR_SRC { out int32 dst, in int32 src1, in int32 src2, in int32 amount }{}{
SSR amount;
SRC dst, src1, src2;
}
proto WSR_SAR_SRC { out int32 dst, in int32 src1, in int32 src2, in int32 amount }{}{
WSR.SAR amount;
SRC dst, src1, src2;
}