ISYNC — Instruction Fetch Synchronize

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
ISYNC 000000000010000000000000

Assembler Syntax

ISYNC

C Syntax

#include <xtensa/tie/xt_core.h>

extern void XT_ISYNC(void);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

ISYNC waits for all previously fetched load, store, cache, TLB, WSR.*, and XSR.* instructions that affect instruction fetch to be performed before fetching the next instruction. RSYNC, ESYNC, and DSYNC are performed as part of this instruction.

The proper sequence for writing instructions and then executing them is:

write instructionsuse DHWB to force the data out of the data cache (this step may be skipped if it is not possible for the data to be dirty in the data cache)use MEMW to wait for the writes to be visible to instruction cache missesuse multiple IHI instructions to invalidate the instruction cache for any lines that were modified (this step may be skipped, along with one of the ISYNC steps on either side, if the affected instructions are in InstRAM or cannot be cached)use ISYNC to ensure that fetch pipeline will see the new instructions

This instruction also waits for all previously executed WSR.* and XSR.* instructions that affect instruction fetch or register access processor state, including:

WSR.LCOUNT, WSR.LBEG, WSR.LENDWSR.IBREAKENABLE, WSR.IBREAKA[i]WSR.CCOMPAREn

See the Special Register Tables in Special Registers and Caches and Local Memories, for a complete description of the ISYNC instruction's uses.

Operation

isync

Exceptions

EveryInst Group (see EveryInst Group:)

Protos that use ISYNC

proto ISYNC { }{}{
ISYNC;
}