Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
RSIL | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||
t | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 |
RSIL at, 0..15
extern int XT_RSIL(immediate t);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
RSIL
first reads the PS
Special Register (described in , PS Register Fields), writes this value to address register at
, and then sets PS.INTLEVEL
to a constant in the range 0..15
encoded in the instruction word. Interrupts at and below the PS.INTLEVEL
level are disabled.
A WSR.PS
or XSR.PS
followed by an RSIL
should be separated with an ESYNC
to guarantee the value written is read back.
On some Xtensa ISA implementations the latency of RSIL
is greater than one cycle, and so it is advantageous to schedule uses of the RSIL
result later.
RSIL
is typically used as follows:
RSIL a2, newlevel
code to be executed at newlevel
WSR.PS a2
The instruction following the RSIL
is guaranteed to be executed at the new interrupt level specified in PS.INTLEVEL
, therefore it is not necessary to insert one of the SYNC
instructions to force the interrupt level change to take effect.
RSIL
is a privileged instruction.
if CRING != 0 then Exception (PrivilegedCause) else AR[t] ← PS PS.INTLEVEL ← s endif
In | Out |
---|---|
PSWOE Rstage , PSCALLINC Estage ,
PSOWB Estage , PSUM Estage , PSEXCM Rstage ,
PSINTLEVEL Estage
|
PSINTLEVEL Mstage , art Estage
|