Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
IHI | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
imm8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IHI as, 0..1020
extern void XT_IHI(int s, immediate i);
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
IHI
performs an instruction cache hit invalidate. It invalidates the specified line in the instruction cache, if it is present. If the specified address is not in the instruction cache, then this instruction has no effect. If the specified line is already invalid, then this instruction has no effect. If the specified line has been locked by an IPFL
instruction, then no invalidation is done and no exception is raised because of the lock. The line remains in the cache and must be unlocked by an IHU
or IIU
instruction before it can be invalidated. Otherwise, if the specified line is present, it is invalidated.
This instruction is required before executing instructions from the instruction cache that have been written by this processor, another processor, or DMA. The writes must first be forced out of the data cache, either by using DHWB
or by using stores that bypass or write through the data cache. An ISYNC
instruction should then be used to guarantee that the modified instructions are visible to instruction cache misses. The instruction cache should then be invalidated for the affected addresses using a series of IHI
instructions. An ISYNC
instruction should then be used to guarantee that this processor's fetch pipeline does not contain instructions from the invalidated lines.
Because the organization of caches is implementation-specific, the operation section below specifies only a call to the implementation's ihitinval
function.
IHI
forms a virtual address by adding the contents of address register as
and an 8-bit zero-extended constant value encoded in the instruction word shifted left by two. Therefore, the offset can specify multiples of four from zero to 1020. If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation encounters an error (for example, protection violation), the processor raises one of several exceptions . The translation is done as if the address were for an instruction fetch.
vAddr ← AR[s] + (022||imm8||02) (pAddr, attributes, cause) ← ftranslate(vAddr, CRING) if invalid(attributes) then EXCVADDR ← vAddr Exception (cause) else ihitinval(vAddr, pAddr) endif