SRL — Shift Right Logical

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
SRL 10010001 0000 0000
r 3210
t 3210

Assembler Syntax

SRL ar, at

C Syntax

#include <xtensa/tie/xt_core.h>

extern unsigned XT_SRL(unsigned t);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

SRL shifts the contents of address register at right, inserting zeros on the left, by the number of bits specified by SAR (shift amount register) and writes the result to address register ar. Typically the SSR or SSA8B instructions are used to load SAR with the shift amount from an address register. Note the result of SRL is undefined if SAR > 32.

Operation

sa ← SAR5..0
AR[r] ← (032||AR[t])31+sa..sa

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
SAR Estage, art Estage arr Estage

Protos that use SRL

proto SRL { out uint32 r, in uint32 t }{}{
SRL r, t;
}
proto SSR_SRL { out uint32 dst, in uint32 src, in int32 amount }{}{
SSR amount;
SRL dst, src;
}