These can all be selected from the Interfaces page of
the Xplorer Configuration Editor.
Selecting a non-zero count of cache prefetch entries option selects whether prefetch is
included; the other options modify its behaviour.
Xtensa processors can prefetch to instruction and data caches if the relevant cache
configuration options are compatible. If not, then prefetch will only be supported to
the data cache. The requirements for prefetching to both instruction and data caches are
as follows:
- Xtensa LX5 and X10 processors and earlier: The instruction and data cache line
widths must be the same, plus the instuction cache and data cache access widths must
be the same
- Xtensa LX6, LX7 and X11 processors and later: The instruction and data cache line
widths must still be the same, but the access width restriction is relaxed as
described in the appropriate Data Book. Note that the conditions have changed, so
make sure to check with the Data Book corresponding to the specific release you will
use to generate hardware.