IPFL — Instruction Cache Prefetch and Lock

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
IPFL 00000111 11010010
s 3210
op2 3210

Assembler Syntax

IPFL as, 0..240

C Syntax

#include <xtensa/tie/xt_instcache.h>

extern void XT_IPFL(int s, immediate i);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

IPFL performs an instruction cache prefetch and lock. The purpose of IPFL is to improve performance, but not to affect state defined by the ISA. Xtensa ISA implementations that do not implement cache locking must raise an illegal instruction exception when this opcode is executed. In general, the performance improvement from using this instruction is implementation-dependent as implementations may not overlap the cache fill with the execution of other instructions.

In some implementations, IPFL checks whether the line containing the specified address is present in the instruction cache, and if not, begins the transfer of the line from memory to the instruction cache. The line is placed in the instruction cache and marked as locked, so it is not replaceable by ordinary instruction cache misses. To unlock the line, use IHU or IIU. To prefetch without locking, use the IPF instruction.

IPFL forms a virtual address by adding the contents of address register as and a 4-bit zero-extended constant value encoded in the instruction word shifted left by four. Therefore, the offset can specify multiples of 16 from zero to 240. If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. The translation is done as if the address were for an instruction fetch. Exceptions are reported exactly as they would be for an instruction fetch. For exceptions fetching the IPFL instruction, EXCVADDR will point to one of the bytes of the IPFL instruction. For exceptions fetching the cache line, EXCVADDR will point to the cache line. EPC points to the IPFL instruction in both cases.

IPFL is a privileged instruction.

Operation

if CRING != 0 then
	Exception (PrivilegedCause)
else
	vAddr ← AR[s] + (024||imm4||04)
	(pAddr, attributes, cause) ← ftranslate(vAddr, CRING)
	if invalid(attributes) then
		EXCVADDR ← vAddr
		Exception (cause)
	else
		iprefetch(vAddr, pAddr, 1)
	endif
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)GenExcep(PrivilegedCause) if Exception Option

Protos that use IPFL

proto IPFL { in int32 s, in immediate i }{}{
IPFL s, i + 0;
}