AE_LALIGN64.I — Load a 64-bit value into the alignment register

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_LALIGN64.I 1000000000011001 0 0111 0
ae_fld_ls_uu 10
s 3210
ae_fld_immls64 321 0

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_LALIGN64.I 110111 0000
ae_fld_ls_uu 10
s 3210
ae_fld_immls64 32 1 0

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_LALIGN64.I 110111 0000
ae_fld_ls_uu 10
s 3210
ae_fld_immls64 32 1 0

Assembler Syntax

AE_LALIGN64.I u0..3(ae_ls_uu), a0..15(ars), -64..56

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern ae_valign AE_LALIGN64_I(const ae_valign * a, immediate i64);

Description

AE_LALIGN64.I is a 64-bit load from memory into the AE_VALIGN register. It forms a virtual address by adding the contents of the address register and an immediate value within the range {-64,...,56} encoded in the instruction word.

Implementation Pipeline

In Out
ars Estage ae_ls_uu Wstage

Protos that use AE_LALIGN64.I

proto AE_LALIGN64.I { out ae_valign uu, in const ae_valign * a, in immediate i64 }{}{
AE_LALIGN64.I uu, a, i64 + 0;
}
proto ae_valign_loadi { out ae_valign uu, in const ae_valign * a, in immediate imm }{}{
AE_LALIGN64.I uu, a, imm + 0;
}