RSR.DBREAKC0 — Read Special Register DBREAKC0

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
RSR.DBREAKC0 0000001110100000 0000
t 3210

Assembler Syntax

RSR.DBREAKC0 a0..15(art)

C Syntax

#include <xtensa/tie/xt_debug.h>

extern unsigned XT_RSR_DBREAKC0(void);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

RSR.* reads the Special Registers that are described in Processor Control Instructions. See Special Registers for more detailed information on the operation of this instruction for each Special Register.

The contents of the Special Register designated by the 8-bit sr field of the instruction word are written to address register at. The name of the Special Register is used in place of the '*' in the assembler syntax above and the translation is made to the 8-bit sr field by the assembler.

RSR is an assembler macro for RSR.* that provides compatibility with the older versions of the instruction containing either the name or the number of the Special Register.

A WSR.* followed by an RSR.* to the same register should be separated with ESYNC to guarantee the value written is read back. On some Xtensa ISA implementations, the latency of RSR.* is greater than one cycle, and so it is advantageous to schedule other instructions before instructions that use the RSR.* result.

RSR.* with Special Register numbers >= 64 is privileged. An RSR.* for an unconfigured register generally will raise an illegal instruction exception.

Operation

sr ← if msbFirst then s||r else r||s
if sr >= 64 and CRING != 0 then
	Exception (PrivilegedCause)
else
	see the Tables in  Special Registers
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)GenExcep(IllegalInstructionCause) if Exception OptionGenExcep(PrivilegedCause) if Exception Option

Implementation Pipeline

In Out
DBREAKC0 Mstage art Mstage

Protos that use RSR.DBREAKC0

proto RSR.DBREAKC0 { out uint32 art }{}{
RSR.DBREAKC0 art;
}