AE_L32F24.XC — Load a 24-bit fractional value and replicate into the AE_DR register

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_L32F24.XC 1000000000001111 0100
ae_fld_ls_v 3210
s 3210
t 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_L32F24.XC 01101111
ae_fld_ls_v 3210
s 3210
t 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_L32F24.XC 10110101 0100
ae_fld_ls_v 3210
s 3210
t 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_L32F24.XC 01101111
ae_fld_ls_v 3210
s 3210
t 3210

Assembler Syntax

AE_L32F24.XC aed0..15(ae_ls_v), a0..15(ars), a0..15(art)

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_L32F24_XC(ae_f24x2 d /*out*/, const ae_f24 * a /*inout*/, int off);

Description

AE_L32F24.XC loads a 24-bit fractional value from memory. into the AE_DR register. It forms a virtual address by adding the contents of the address registers.

The load instruction reads the most significant 24 bits (3 bytes) of the 32-bit word, sign-extends it into 32-bits and replicates into the two halves of the AE_DR register.

The intent is that the value in memory represents a 32-bit (1.31) fraction that gets truncated and placed into the AE_DR register d as a 9.23-bit fraction.

Note: the .XC suffix indicates that the operation is using a circular buffer addressing mode. The updated base address is formed by adding the register offset to the base address with circular wrap-around.

Implementation Pipeline

In Out
AE_CEND0 Estage, AE_CBEGIN0 Estage, ars Estage, art Estage ae_ls_v Mstage, ars Estage

Protos that use AE_L32F24.XC

proto AE_L32F24.XC { out ae_f24x2 d, inout const ae_f24 * a, in int32 off }{}{
AE_L32F24.XC d, a, off;
}
proto AE_LP24F.C { out ae_p24x2s d, inout const ae_p24f * a, in int32 off }{}{
AE_L32F24.XC d, a, off;
}