AE_S32F24.L.IP — Store a 24-bit fractional value from the L entry of the AE_DR register

Instruction Word

Slot
ae2_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format2 - 64 bit(s)0000 1110
AE_S32F24.L.IP 1000000000010111 1 110
ae_fld_ls_v 3210
s 3210
ae_fld_immls32 321 0

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format - 64 bit(s) 1111
AE_S32F24.L.IP 10111001
ae_fld_ls_v 3210
s 3210
ae_fld_immls32 3210

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
AE_S32F24.L.IP 11011111 0100
ae_fld_ls_v 3210
s 3210
ae_fld_immls32 3210

Slot
ae_slot0
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format ae_format1 - 64 bit(s)1 1110
AE_S32F24.L.IP 10111001
ae_fld_ls_v 3210
s 3210
ae_fld_immls32 3210

Assembler Syntax

AE_S32F24.L.IP aed0..15(ae_ls_v), a0..15(ars), -32..28

C Syntax

#include <xtensa/tie/xt_hifi2.h>

extern void AE_S32F24_L_IP(ae_f24x2 d, ae_f24 * a /*inout*/, immediate off);

Description

AE_S32F24.L.IP stores a 24-bit fractional value to memory from the AE_DR register. It forms a virtual address using the address register.

The store instruction writes the least significant 24 bits (3 bytes) of the L entry, padded with zeroes on the right.

The intent is that the value in the AE_DR register is a 9.23-bit fraction that is stored in memory as a 1.31-bit fraction.

This instruction also post-increments the address register by the immediate value.

Implementation Pipeline

In Out
ae_ls_v Mstage, ars Estage ars Estage

Protos that use AE_S32F24.L.IP

proto AE_S32F24.L.IP { in ae_f24x2 d, inout ae_f24 * a, in immediate off }{}{
AE_S32F24.L.IP d, a, off + 0;
}
proto ae_f24_storeip { in ae_f24 d, inout ae_f24 * a, in immediate off }{}{
AE_S32F24.L.IP d, a, off + 0;
}
proto ae_p24f_storeip { in ae_p24f d, inout ae_p24f * a, in immediate off }{}{
AE_S32F24.L.IP d, a, off + 0;
}