Semantic Data Gating option

Allows the insertion of data gates on the inputs of TIE semantics to prevent unnecessary toggling on semantics not currently in use by the core

Semantic Data Gating option
All
In both user-written and core TIE blocks, the output of register files and states fan out to several parallel TIE semantic logic blocks. At any given time, not all of these semantics are in use. If the semantic data gating option is configured, data gates with the appropriate enables are inserted in front of these semantic logic blocks to prevent unnecessary toggles. Two selections enable data gating:
  1. If "all" is selected, then all user-defined TIE semantics and a Cadence-determined optimal list of core TIE semantics are data gated.
  2. If "user" is selected, then only user-defined TIE semantics with the data_gate property are gated, as well as a Cadence-determined optimal list of core TIE semantics.
Although the Xtensa core will lower memory enable signals when a particular memory is not in use, the outbound address and data lines will still toggle. Data gating these signals can save idle-cycle memory dynamic power. If the memory data gating option is configured, data gates with the appropriate enables will be inserted on all instruction and data memories.