Slot Inst | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format x24 - 24 bit(s) | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
BGEI | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
r | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
imm8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BGEI as, imm, label
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
BGEI
branches if address register as
is two's complement greater than or equal to the constant encoded in the r
field. The constant values encoded in the r
field are not simply 0..15. For the constant values that can be encoded by r
, see Xtensa Instruction Set Architecture Reference Manual.
The target instruction address of the branch is given by the address of the BGEI
instruction, plus the sign-extended 8-bit imm8
field of the instruction plus four. If the address register as
is less than the constant, execution continues with the next sequential instruction.
The inverse of BGEI
is BLTI
.
if AR[s] >= B4CONST(r) then nextPC ← PC + (imm8724||imm8) + 4 endif