S32C1I — Store 32-bit Compare Conditional

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
S32C1I 1110 0010
t 3210
s 3210
imm8 76543210

Assembler Syntax

S32C1I at, as, 0..1020

C Syntax

#include <xtensa/tie/xt_sync.h>

extern void XT_S32C1I(unsigned c /*inout*/, const unsigned * p, immediate o);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

S32C1I is a conditional store instruction intended for updating synchronization variables in memory shared between multiple processors. It may also be used to atomically update variables shared between different interrupt levels or other pairs of processes on a single processor. S32C1I attempts to store the contents of address register at to the virtual address formed by adding the contents of address register as and an 8-bit zero-extended constant value encoded in the instruction word shifted left by two. If the old contents of memory at the physical address equals the contents of the SCOMPARE1 Special Register, the new data is written; otherwise the memory is left unchanged. In either case, the value read from the location is written to address register at. In some implementations, under unusual circumstances, the bitwise not of SCOMPARE1 may be returned when memory is left unchanged instead of the current value of the memory location (see S32C1I Modification). The memory read, compare, and write may take place in the processor or the memory system, depending on the Xtensa ISA implementation, as long as these operations exclude other writes to this location. See for more information on where the atomic operation takes place.

From a memory ordering point of view, the atomic pair of accesses has the characteristics of both an acquire and a release. That is, the atomic pair of accesses does not begin until all previous loads, stores, acquires, and releases have performed. The atomic pair must perform before any following load, store, acquire, or release may begin.

If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation or memory reference encounters an error (for example, protection violation or non-existent memory), the processor raises one of several exceptions .

Without the Unaligned Exception Option , the two least significant bits of the address are ignored. A reference to an address that is not 0 mod 4 produces the same result as a reference to the address with the least significant bits cleared. With the Unaligned Exception Option, such an access raises an exception.

S32C1I does both a load and a store when the store is successful. However, memory protection tests check for store capability and the instruction may raise a StoreProhibitedCause exception, but will never raise a LoadProhibited Cause exception.

Operation

vAddr ← AR[s] + (022||imm8||02)
(mem32, error) ← Store32C1 (vAddr, AR[t], SCOMPARE1)
if error then
	EXCVADDR ← vAddr
	Exception (LoadStoreError)
else
	AR[t] ← One Of (mem32, ~SCOMPARE1)
endif

Exceptions

Memory Store Group (see Memory Store Group:)

Implementation Pipeline

In Out
SCOMPARE1 Wstage, art Mstage, ars Estage art Mstage

Protos that use S32C1I

proto S32C1I { inout uint32 c, in const uint32 * p, in immediate o }{}{
S32C1I c, p, o + 0;
}