DPFWO — Data Cache Prefetch for Write Once

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
DPFWO 0111 00110010
s 3210
imm8 76543210

Assembler Syntax

DPFWO as, 0..1020

C Syntax

#include <xtensa/tie/xt_datacache.h>

extern void XT_DPFWO(const int * s, immediate i);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

DPFWO performs a data cache prefetch for write once. The purpose of DPFWO is to improve performance, but not to affect the ISA state. Therefore, some Xtensa ISA implementations may choose to implement this instruction as a simple "no-operation" instruction. In general, the performance improvement from using this instruction is implementation-dependent. Refer to a specific Xtensa Microprocessor Data Book for more details.

In some Xtensa ISA implementations, DPFWO checks whether the line containing the specified address is present in the data cache, and if not, begins the transfer of the line from memory. Four data prefetch instructions provide different "hints" about how the data is likely to be used in the future. DPFWO indicates that the data is likely to be read and written once before it is replaced by another line in the cache. In some implementations, this write hint fetches the data with write permission (for example, in a system with shared and exclusive states). The write-once hint might be used to select a specific cache way or to select a streaming buffer instead of the cache.

DPFWO forms a virtual address by adding the contents of address register as and an
8-bit zero-extended constant value encoded in the instruction word shifted left by two. Therefore, the offset can specify multiples of four from zero to 1020. If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. No exception is raised on either translation or memory reference. Instead of raising an exception, the prefetch is dropped and the instruction becomes a nop.

Because the organization of caches is implementation-specific, the operation section below specifies only a call to the implementation's dprefetch function.

Operation

vAddr ← AR[s] + (022||imm8||02)
(pAddr, attributes, cause) ← ltranslate(vAddr, CRING)
if not invalid(attributes) then
	dprefetch(vAddr, pAddr, 1, 1, 0)
endif

Exceptions

EveryInstR Group (see EveryInstR Group:)

Protos that use DPFWO

proto DPFWO { in const int32 * s, in immediate i }{}{
DPFWO s, i + 0;
}