Use Extended L32R Instruction (for Legacy Hardware)

All Cadence processors from Xtensa LX and Xtensa6 through LX3 and Xtensa 8 include hardware to support two different kinds of L32R instruction: normal (PC relative) and "based". This software selection chooses how the target software is built (and how the compiler generates code) - whether it makes use of the standard PC relative address mode, or whether it uses the extended L32R HW support for a larger address range.

Hardware support for Extended L32R
Not Selected
Xtensa Tools should use Extended L32R
No Hardware Support

A processor needs a mechanism for accessing literals; numbers with values known at compile or link time. Literals are used for constants directly written in C and for the address of global variables. For example, in order to implement the C statement x=123456, when x is a global variable, the compiler must put the literal 123456 into a register, put the address of the variable x into another register, and then store the value in the first register into the address from the second register. For small literals, the literal can be encoded directly inside a movi instruction that moves the value of a literal into a register. For larger literals, the compiler places the literal value in memory and uses the l32r instruction to load the literal from memory into a register. Normally l32r is a PC-relative instruction which can load a literal from any memory location within 256 Kilobytes of the instruction invoking the l32r. The compiler, assembler and linker work together to ensure that literals are placed in range of their invoking l32r instruction, and even combine multiple literals with the same value to save memory. If however, you are using a local IRAM that is 256 KBytes or larger, the only place to put a literal that is in range might be inside the IRAM itself. Prior to the RD release, loading memory from an IRAM was slow and therefore undesirable. Therefore, Cadence offered the extended l32r option for users of large IRAMs. With this option, the l32r instruction loads from an offset of a global base register. This global base register can point to any memory allowing literals to be placed anywhere. However, there are disadvantages to the use of extended L32R instruction. In particular, this option is not supported by third-party RTOSs. Furthermore, since the base register is global, all the literals used by the program must be contiguous and therefore a program is limited to a total of 256 KBytes of literals, or equivalently 64K literals. Additionally, Cadence does not support dynamically loading and unloading code on software configurations that uses the extended L32R. Starting with the RD release, the hardware is able to load literals quickly even when they are in IRAM. Therefore, the extended L32R option is only supported for older hardware.