Slot ae2_slot0 | 6 3 | 6 2 | 6 1 | 6 0 | 5 9 | 5 8 | 5 7 | 5 6 | 5 5 | 5 4 | 5 3 | 5 2 | 5 1 | 5 0 | 4 9 | 4 8 | 4 7 | 4 6 | 4 5 | 4 4 | 4 3 | 4 2 | 4 1 | 4 0 | 3 9 | 3 8 | 3 7 | 3 6 | 3 5 | 3 4 | 3 3 | 3 2 | 3 1 | 3 0 | 2 9 | 2 8 | 2 7 | 2 6 | 2 5 | 2 4 | 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Format ae_format2 - 64 bit(s) | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||
BBCI.W18 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
s | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
bbi | 4 | 3 | 2 | 1 | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
xt_wbr18_imm | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BBCI.W18 as, 0..31, label
(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)
The operation of theBBCI.W18
branch instruction is very similar to the Xtensa ISA instruction BBCI
. The only difference is that the BBCI.W18
instruction provides for a wider immediate field of 18 bits to encode the branch offset, thus enabling branches over a greater address range. b ← bbi xor msbFirst5 if AR[s]b = 0 then nextPC ← PC + (imm8724||imm8) + 4 endif