By default, vector addresses are fixed at processor configuration time and cannot be changed.
This option adds the following capabilities:
Static Vectors Group: the 2 vectors in this group are the reset vector and, if configured, the memory error vector. As before, when a processor configuration is created, addresses are determined for all vectors based on the memory layout. If the relocatable vectors option is selected, an alternate address is also specified at configuration time. The auto-placement algorithm (if enabled) will try and choose an appropriate instruction memory. When the XPG builds the processor, both primary and alternate addresses will be in the generated output. By default, at reset, the processor will jump to the "primary" configured reset address. Alternatively a pin on the processor can be asserted to cause it to jump to the alternate reset address.
When software is generated for the processor, you have the option of placing the reset handler code at the primary address or at the alternate address. If you plan to make use of this feature, you should build both software configurations so you can link binaries with the corresponding handler code.
The hardware implementation of the relocatable vectors option places constraints on the ordering of vectors in memory (if memory errors are configured, the vector must be after the reset vector), and the vectors must be contained within a 4K block of memory.