SLL — Shift Left Logical

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
SLL 10100001 00000000
r 3210
s 3210

Assembler Syntax

SLL ar, as

C Syntax

#include <xtensa/tie/xt_core.h>

extern int XT_SLL(int s);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

SLL shifts the contents of address register as left by the number of bit positions specified (as 32 minus number of bit positions) in the SAR (shift amount register) and writes the result to address register ar. Typically the SSL or SSA8L instructions are used to specify the left shift amount by loading SAR with 32-shift. This transformation allows SLL to be implemented in the SRC funnel shifter (which only shifts right), using the SLL data as the most significant 32 bits and zero as the least significant 32 bits. Note the result of SLL is undefined if SAR > 32.

Operation

sa ← SAR5..0
AR[r] ← (AR[s]||032)31+sa..sa

Exceptions

EveryInstR Group (see EveryInstR Group:)

Implementation Pipeline

In Out
SAR Estage, ars Estage arr Estage

Protos that use SLL

proto SLL { out int32 r, in int32 s }{}{
SLL r, s;
}
proto SSL_SLL { out int32 dst, in int32 src, in int32 amount }{}{
SSL amount;
SLL dst, src;
}