MULA.DA.HL.LDDEC — Signed Multiply/Accumulate, Load with Autodecrement

Instruction Word

Slot
Inst
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Format x24 - 24 bit(s) 0
MULA.DA.HL.LDDEC 010110010 0100
w 10
s 3210
x 0
t 3210

Assembler Syntax

MULA.DA.*.LDDEC mw, as, mx, at Where * expands as follows:

MULA.DA.LL.LDDEC - for (half=0)

MULA.DA.HL.LDDEC - for (half=1)

MULA.DA.LH.LDDEC - for (half=2)

MULA.DA.HH.LDDEC - for (half=3)


C Syntax

#include <xtensa/tie/xt_MAC16.h>

extern void XT_MULA_DA_HL_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);

Description

(please consult the Xtensa ® Instruction Set Architecture Reference Manual for any cross references and additional information)

MULA.DA.*.LDDEC performs a parallel load and multiply/accumulate.

First, it performs a two's complement multiply of half of MAC16 register mx and half of address register at, producing a 32-bit result. The result is sign-extended to 40 bits and added to the contents of the MAC16 accumulator. The mx operand can designate either MAC16 register m0 or m1.

Next, it loads MAC16 register mw from memory using auto-decrement addressing. It forms a virtual address by subtracting 4 from the contents of address register as. Thirty-two bits (four bytes) are read from the physical address. This data is then written to MAC16 register mw, and the virtual address is written back to address register as. The mw operand can designate any of the four MAC16 registers.

If the Region Translation Option or the MMU Option is enabled, the virtual address is translated to the physical address. If not, the physical address is identical to the virtual address. If the translation or memory reference encounters an error (for example, protection violation or non-existent memory), the processor raises one of several exceptions .

Without the Unaligned Exception Option , the two least significant bits of the address are ignored. A reference to an address that is not 0 mod 4 produces the same result as a reference to the address with the least significant bits cleared. With the Unaligned Exception Option, such an access raises an exception.

The MAC16 register source mx and the MAC16 register destination mw may be the same. In this case, the instruction uses the contents of mx as the source operand prior to loading mx with the load data.

Operation

vAddr ← AR[s] − 4
(mem32, error) ← Load32(vAddr)
if error then
	EXCVADDR ← vAddr
	Exception (LoadStoreErrorCause)
else
	m1 ← if half0 then MR[0||x]31..16 else MR[0||x]15..0
	m2 ← if half1 then AR[t]31..16 else AR[t]15..0
	ACC ← ACC + (m11524||m1) \* (m21524||m2)
	AR[s] ← vAddr
	MR[w] ← mem32
endif
 

Exceptions

Memory Load Group (see Memory Load Group:)

Implementation Pipeline

In Out
ACC Mstage, ars Estage, mx Estage, art Estage ACC Mstage, mw Mstage, ars Estage

Protos that use MULA.DA.HL.LDDEC

proto MULA.DA.HL.LDDEC { in immediate w, inout const int16 * s, in immediate x, in int32 t }{}{
MULA.DA.HL.LDDEC w + 0, s, x + 0, t;
}