blob: 7ec414dd97141d399f3d0e80c12b8a3c563a80b9 [file] [log] [blame]
Vishal Bhoj82c80712015-12-15 21:13:33 +05301/*
2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved.
3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * Neither the name of ARM nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific
17 * prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef __HI6220_H__
33#define __HI6220_H__
34
35#include <hi6220_regs_acpu.h>
36#include <hi6220_regs_ao.h>
37#include <hi6220_regs_peri.h>
38#include <hi6220_regs_pmctrl.h>
39
40#include <hisi_mcu.h>
41#include <hisi_sram_map.h>
42
43#define MEDIA_CTRL_BASE 0xf4410000
44#define MEDIA_SUBSYS_CTRL2 (MEDIA_CTRL_BASE + 0x508)
45#define MEDIA_SUBSYS_NOC_DFS (MEDIA_CTRL_BASE + 0x510)
46#define MEDIA_SUBSYS_CTRL5 (MEDIA_CTRL_BASE + 0x51c)
47
48#define MMC0_BASE 0xf723d000
49#define MMC1_BASE 0xf723e000
50
51#define EDMAC_BASE 0xf7370000
52#define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694)
53#define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6))
54
55#define PMUSSI_BASE 0xf8000000
56
57#define TIMER0_BASE 0xf8008000
58#define TIMER00_LOAD (TIMER0_BASE + 0x000)
59#define TIMER00_VALUE (TIMER0_BASE + 0x004)
60#define TIMER00_CONTROL (TIMER0_BASE + 0x008)
61#define TIMER00_BGLOAD (TIMER0_BASE + 0x018)
62
63#define GPIO0_BASE 0xf8011000
64#define GPIO1_BASE 0xf8012000
65#define GPIO2_BASE 0xf8013000
66#define GPIO3_BASE 0xf8014000
67#define GPIO4_BASE 0xf7020000
68#define GPIO5_BASE 0xf7021000
69#define GPIO6_BASE 0xf7022000
70#define GPIO7_BASE 0xf7023000
71#define GPIO8_BASE 0xf7024000
72#define GPIO9_BASE 0xf7025000
73#define GPIO10_BASE 0xf7026000
74#define GPIO11_BASE 0xf7027000
75#define GPIO12_BASE 0xf7028000
76#define GPIO13_BASE 0xf7029000
77#define GPIO14_BASE 0xf702a000
78#define GPIO15_BASE 0xf702b000
79#define GPIO16_BASE 0xf702c000
80#define GPIO17_BASE 0xf702d000
81#define GPIO18_BASE 0xf702e000
82#define GPIO19_BASE 0xf702f000
83
84extern void init_acpu_dvfs(void);
85
86#endif /* __HI6220_H__ */