Merge tag 'u-boot-imx-20220523' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20220523
-------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087
Additionally to u-boot-imx20200520:
- DH MX8MP
- i.MX GPIO: reading GPIO when direction is output
- Menlo i.MX53: switch to DM
And from u-boot-imx20200520:
- fix Verdin hang
- add pca9450 regulator
- conversion to DM_SERIAL
- NAND block handling
- fix crypto
- enable cache on some boards
- add ACC board (MX6)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 9fe1cd9..0b3e3b2 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -409,7 +409,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index a71ee63..253008a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1648,7 +1648,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
serdes_misc_init();
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af..3ca980a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -738,6 +738,7 @@
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dhcom-pdk2.dtb \
+ imx6dl-dhcom-picoitx.dts \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
@@ -771,12 +772,14 @@
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard-revd1.dtb \
+ imx6s-dhcom-drc02.dtb
endif
ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
dtb-y += \
imx6-apalis.dtb \
+ imx6q-bosch-acc.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-cubox-i-emmc-som-v15.dtb \
@@ -936,6 +939,7 @@
imx8mn-beacon-kit.dtb \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
+ imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
diff --git a/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi
new file mode 100644
index 0000000..16669b2
--- /dev/null
+++ b/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
+ */
+
+#include "imx6qdl-dhcom-u-boot.dtsi"
+
+&fec {
+ phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx6dl-dhcom-picoitx.dts b/arch/arm/dts/imx6dl-dhcom-picoitx.dts
new file mode 100644
index 0000000..038bb00
--- /dev/null
+++ b/arch/arm/dts/imx6dl-dhcom-picoitx.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
+ * DHCOM PCB number: 493-300 or newer
+ * PicoITX PCB number: 487-600 or newer
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-picoitx.dtsi"
+
+/ {
+ model = "DH electronics i.MX6DL DHCOM on PicoITX";
+ compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som",
+ "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi
new file mode 100644
index 0000000..37c182d
--- /dev/null
+++ b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/* Copyright (C) 2022 Denx Software Engineering GmbH
+ * Philip Oberfichtner <pro@denx.de>
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ bus@2000000 {
+ u-boot,dm-spl;
+
+ spba-bus@2000000 {
+ u-boot,dm-spl;
+ };
+ };
+
+ bus@2100000 {
+ u-boot,dm-spl;
+ };
+ };
+
+ bootcount {
+ compatible = "u-boot,bootcount-pmic";
+ pmic = <&pmic>;
+ };
+};
+
+&uart1 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc4 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6q-bosch-acc.dts b/arch/arm/dts/imx6q-bosch-acc.dts
new file mode 100644
index 0000000..1bd4ef2
--- /dev/null
+++ b/arch/arm/dts/imx6q-bosch-acc.dts
@@ -0,0 +1,769 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support for the i.MX6-based Bosch ACC board.
+ *
+ * Copyright (C) 2016 Garz & Fricke GmbH
+ * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus@denx.de>
+ * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
+ * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "imx6q.dtsi"
+
+/ {
+ model = "Bosch ACC";
+ compatible = "bosch,imx6q-acc", "fsl,imx6q";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc4;
+ mmc1 = &usdhc2;
+ serial0 = &uart2;
+ serial1 = &uart1;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ backlight_lvds: backlight-lvds {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 200000>;
+ brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
+ num-interpolated-steps = <10>;
+ default-brightness-level = <60>;
+ power-supply = <®_lcd>;
+ };
+
+ panel {
+ compatible = "dataimage,fg1001l0dsswmg01";
+ backlight = <&backlight_lvds>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ refclk: refclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "12mhz_refclk";
+ assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
+ <&clks IMX6QDL_CLK_CKO2>,
+ <&clks IMX6QDL_CLK_CKO2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
+ <&clks IMX6QDL_CLK_CKO2_PODF>,
+ <&clks IMX6QDL_CLK_OSC>;
+ assigned-clock-rates = <0>, <12000000>, <0>;
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1225000
+ 852000 1225000
+ 792000 1150000
+ 396000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 1200000 1225000
+ 996000 1175000
+ 852000 1175000
+ 792000 1150000
+ 396000 1150000
+ >;
+ };
+
+ cpu1: cpu@1 {
+ operating-points = <
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1225000
+ 852000 1225000
+ 792000 1150000
+ 396000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 1200000 1225000
+ 996000 1175000
+ 852000 1175000
+ 792000 1150000
+ 396000 1150000
+ >;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led_red: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ max-brightness = <248>;
+ default-state = "off";
+ pwms = <&pwm2 0 500000>;
+ };
+
+ led_white: led-1 {
+ color = <LED_COLOR_ID_WHITE>;
+ max-brightness = <248>;
+ default-state = "off";
+ pwms = <&pwm3 0 500000>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_gpio_led>;
+
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_5p0: regulator-5p0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5p0";
+ };
+
+ reg_vin: regulator-vin {
+ compatible = "regulator-fixed";
+ regulator-name = "VIN";
+ regulator-min-microvolt = <4500000>;
+ regulator-max-microvolt = <4500000>;
+ regulator-always-on;
+ vin-supply = <®_5p0>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <®_5p0>;
+ };
+
+ reg_usb_h2_vbus: regulator-usb-h2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5p0> ;
+ regulator-always-on;
+ };
+
+ reg_vsnvs: regulator-vsnvs {
+ compatible = "regulator-fixed";
+ regulator-name = "VSNVS_3V0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ vin-supply = <®_5p0>;
+ };
+
+ reg_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD0 POWER";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_enable>;
+ gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ reg_dac: regulator-dac {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_dac";
+ regulator-min-microvolt = <20000>;
+ regulator-max-microvolt = <20000>;
+ vin-supply = <®_5p0> ;
+ regulator-boot-on;
+ };
+
+ reg_sw4: regulator-sw4 {
+ compatible = "regulator-fixed";
+ regulator-name = "SW4_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <®_5p0>;
+ };
+
+ reg_sys: regulator-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "SYS_4V2";
+ regulator-min-microvolt = <4200000>;
+ regulator-max-microvolt = <4200000>;
+ regulator-always-on;
+ vin-supply = <®_5p0>;
+ };
+};
+
+®_arm {
+ vin-supply = <&sw2_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1c_reg>;
+};
+
+®_vdd1p1 {
+ vin-supply = <®_vsnvs>;
+};
+
+®_vdd2p5 {
+ vin-supply = <®_vsnvs>;
+};
+
+®_vdd3p0 {
+ vin-supply = <®_vsnvs>;
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp", "enet_out";
+ phy-mode = "rmii";
+ phy-supply = <®_sw4>;
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+ smsc,disable-energy-detect;
+ };
+ };
+};
+
+&gpu_vg {
+ status = "disabled";
+};
+
+&gpu_2d {
+ status = "disabled";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pmic: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1c_reg: sw1c {
+ regulator-name = "VDD_SOC (sw1abc)";
+ regulator-min-microvolt = <1275000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-name = "VDD_ARM (sw2)";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ compatible = "regulator-fixed";
+ regulator-name = "DDR_1V5a";
+ regulator-boot-on;
+ regulator-always-on;
+
+ };
+
+ sw3b_reg: sw3b {
+ compatible = "regulator-fixed";
+ regulator-name = "DDR_1V5b";
+ regulator-boot-on;
+ regulator-always-on;
+
+ };
+
+ sw4_reg: sw4 {
+ regulator-name = "AUX 3V15 (sw4)";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ status = "disabled";
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ lm75: sensor@49 {
+ compatible = "national,lm75b";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm75>;
+ reg = <0x49>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ rtc: rtc@51 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ eeprom_ext: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ usb3503: usb@8 {
+ compatible = "smsc,usb3503";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3503>;
+ reg = <0x08>;
+ connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */
+ intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */
+ initial-mode = <1>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
+ refclk-frequency = <12000000>;
+ };
+
+ exc3000: touchscreen@2a {
+ compatible = "eeti,exc3000";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctouch>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ touchscreen-size-x = <4096>;
+ touchscreen-size-y = <4096>;
+ };
+
+ vcnl4035: light-sensor@60 {
+ compatible = "vishay,vcnl4035";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_proximity>;
+ reg = <0x60>;
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pwm1 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm3 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbh2 {
+ pinctrl-names = "idle", "active";
+ pinctrl-0 = <&pinctrl_usbh2_idle>;
+ pinctrl-1 = <&pinctrl_usbh2_active>;
+ vbus-supply = <®_usb_h2_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ vbus-supply = <®_usb_otg_vbus>;
+ disable-over-current;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ voltage-ranges = <3300 3300>;
+ vmmc-supply = <®_sw4>;
+ fsl,wp-controller;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ keep-power-in-suspend;
+ voltage-ranges = <3300 3300>;
+ vmmc-supply = <®_sw4>;
+ fsl,wp-controller;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog1>;
+ fsl,ext-reset-output;
+ timeout-sec=<10>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
+ };
+
+ pinctrl_reset_gpio_led: reset-gpio-led-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_lcd_enable: lcdenablegrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */
+ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */
+ >;
+ };
+
+ pinctrl_lm75: lm75grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_proximity: proximitygrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_rtc: rtc-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */
+ >;
+ };
+
+ pinctrl_ctouch: ctouch-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh2_idle: usbh2-idle-grp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
+ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018
+ >;
+ };
+
+ pinctrl_usbh2_active: usbh2-active-grp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
+ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018
+ >;
+ };
+
+ pinctrl_usb3503: usb3503-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */
+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069
+ MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059
+ >;
+ };
+
+ pinctrl_wdog1: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi
new file mode 100644
index 0000000..702cd4a
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/*
+ * Special SoM hardware required which uses the pins from micro SD card. The
+ * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
+ * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
+ * card must be disabled and the uart1 rts/cts must be output on other DHCOM
+ * pins, see uart1 and usdhc3 node below.
+ */
+&can2 {
+ status = "okay";
+};
+
+&gpio1 {
+ /*
+ * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+ * GPIO line, however the i.MX6 UART driver assumes RX happens
+ * during TX anyway and that it only controls drive enable DE
+ * line. Hence, the RX is always enabled here.
+ */
+ rs485-rx-en-hog {
+ gpio-hog;
+ gpios = <18 0>; /* GPIO Q */
+ line-name = "rs485-rx-en";
+ output-low;
+ };
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "DRC02-In1", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
+ "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "",
+ "", "", "", "", "DRC02-Out1", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+ gpio-line-names =
+ "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "",
+ "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&uart1 {
+ /*
+ * Due to the use of can2 the signals for can2 Tx and Rx are routed to
+ * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs
+ * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts.
+ */
+ /delete-property/ uart-has-rtscts;
+ cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
+ pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;
+ pinctrl-names = "default";
+ rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+};
+
+&uart5 {
+ /*
+ * On DRC02 this UART is used as RS485 interface and RS485_TX_En is
+ * controlled by DHCOM GPIO P. So remove rts/cts pins and the property
+ * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
+ * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
+ * node above.
+ */
+ /delete-property/ uart-has-rtscts;
+ linux,rs485-enabled-at-boot-time;
+ pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>;
+ pinctrl-names = "default";
+ rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
+};
+
+&usbh1 {
+ disable-over-current;
+};
+
+&usdhc2 { /* SD card */
+ status = "okay";
+};
+
+&usdhc3 {
+ /*
+ * Due to the use of can2 the micro SD card on module have to be
+ * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as
+ * can2 Tx and Rx.
+ */
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl-0 = <
+ /*
+ * The following DHCOM GPIOs are used on this board.
+ * Therefore, they have been removed from the list below.
+ * I: uart1 rts
+ * M: uart1 cts
+ * P: uart5 rs485-tx-en
+ * Q: uart5 rs485-rx-en
+ */
+ &pinctrl_hog_base
+ &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+ &pinctrl_dhcom_g &pinctrl_dhcom_h
+ &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+ &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_r
+ &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+ &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+ >;
+ pinctrl-names = "default";
+
+ pinctrl_uart5_core: uart5-core-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
index a1ffb1d..0673c21 100644
--- a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
@@ -5,19 +5,6 @@
#include "imx6qdl-dhcom-u-boot.dtsi"
-/ {
- fec_vio: regulator-fec {
- compatible = "regulator-fixed";
-
- regulator-name = "fec-vio";
- gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
- };
-};
-
&fec {
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <1>;
- phy-reset-post-delay = <10>;
-
- phy-supply = <&fec_vio>;
};
diff --git a/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi b/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi
new file mode 100644
index 0000000..4cd4cb9
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ led {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_YELLOW>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ pinctrl-0 = <&pinctrl_dhcom_i>;
+ pinctrl-names = "default";
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "",
+ "", "", "", "", "", "", "", "",
+ "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H",
+ "DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "",
+ "", "", "", "", "PicoITX-Out1", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+ gpio-line-names =
+ "", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "",
+ "", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&iomuxc {
+ pinctrl-0 = <
+ /*
+ * The following DHCOM GPIOs are used on this board.
+ * Therefore, they have been removed from the list below.
+ * I: yellow led
+ */
+ &pinctrl_hog_base
+ &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+ &pinctrl_dhcom_g &pinctrl_dhcom_h
+ &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+ &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+ &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+ &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+ >;
+ pinctrl-names = "default";
+};
diff --git a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
index 4c3b5e8..190567a 100644
--- a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
@@ -1,8 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2020 Harald Seiler <hws@denx.de>
+ * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
*/
+/ {
+ aliases {
+ eeprom0 = &eeprom0;
+ };
+};
+
+&fec {
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <10>;
+ phy-supply = <®_eth_vio>;
+};
+
+&i2c3 {
+ eeprom0: eeprom@50 {
+ };
+};
+
®_usb_otg_vbus {
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
diff --git a/arch/arm/dts/imx6qdl-gw51xx.dtsi b/arch/arm/dts/imx6qdl-gw51xx.dtsi
index 812acf7..139ffe0 100644
--- a/arch/arm/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw51xx.dtsi
@@ -130,7 +130,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw52xx.dtsi b/arch/arm/dts/imx6qdl-gw52xx.dtsi
index 81a9ce3..1b5c836 100644
--- a/arch/arm/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi
@@ -196,7 +196,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi
index 77ac103..e5e9e0c 100644
--- a/arch/arm/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi
@@ -190,7 +190,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi
index 98c81e9..2f41f09 100644
--- a/arch/arm/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi
@@ -227,7 +227,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi
index 1e95267..6586d87 100644
--- a/arch/arm/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/dts/imx6qdl-gw560x.dtsi
@@ -281,7 +281,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw5903.dtsi b/arch/arm/dts/imx6qdl-gw5903.dtsi
index 6ebf6ae..1df3fab 100644
--- a/arch/arm/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5903.dtsi
@@ -225,7 +225,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi
index 286c7a9..381f605 100644
--- a/arch/arm/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5904.dtsi
@@ -203,7 +203,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
fixed-link {
diff --git a/arch/arm/dts/imx6qdl-gw5907.dtsi b/arch/arm/dts/imx6qdl-gw5907.dtsi
index a36b6e7..68585f8 100644
--- a/arch/arm/dts/imx6qdl-gw5907.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5907.dtsi
@@ -132,7 +132,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw5910.dtsi b/arch/arm/dts/imx6qdl-gw5910.dtsi
index 446c104..594468d 100644
--- a/arch/arm/dts/imx6qdl-gw5910.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5910.dtsi
@@ -148,7 +148,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi
index 8fd8fdb..f51ec3d 100644
--- a/arch/arm/dts/imx6qdl-gw5912.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5912.dtsi
@@ -144,7 +144,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-gw5913.dtsi b/arch/arm/dts/imx6qdl-gw5913.dtsi
index c2c1c2b..44d347f 100644
--- a/arch/arm/dts/imx6qdl-gw5913.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5913.dtsi
@@ -123,7 +123,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
- phy-reset-post-delay = <100>;
+ phy-reset-post-delay = <300>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi
new file mode 100644
index 0000000..16669b2
--- /dev/null
+++ b/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
+ */
+
+#include "imx6qdl-dhcom-u-boot.dtsi"
+
+&fec {
+ phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx6s-dhcom-drc02.dts b/arch/arm/dts/imx6s-dhcom-drc02.dts
new file mode 100644
index 0000000..4077b60
--- /dev/null
+++ b/arch/arm/dts/imx6s-dhcom-drc02.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2
+ * DHCOM PCB number: 493-400 or newer
+ * DRC02 PCB number: 568-100 or newer
+ */
+/dts-v1/;
+
+/*
+ * The kernel only distinguishes between i.MX6 Quad and DualLite,
+ * but the Solo is actually a DualLite with only one CPU. So use
+ * DualLite for the Solo and disable one CPU node.
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-drc02.dtsi"
+
+/ {
+ model = "DH electronics i.MX6S DHCOM on DRC02";
+ compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som",
+ "fsl,imx6dl";
+
+ cpus {
+ /delete-node/ cpu@1;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
index 154116d..5b02204 100644
--- a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
@@ -392,7 +392,7 @@
&i2c2 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
- clock-frequency = <320000>;
+ clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 8861542..e9fbf7b 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -121,6 +121,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&fec1 {
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 6f70722..4d0ecb0 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -80,6 +80,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
new file mode 100644
index 0000000..ae838ca
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ aliases {
+ eeprom0 = &eeprom0;
+ eeprom1 = &eeprom1;
+ mmc0 = &usdhc2; /* MicroSD */
+ mmc1 = &usdhc3; /* eMMC */
+ mmc2 = &usdhc1; /* SDIO */
+ };
+
+ config {
+ dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&buck4 {
+ u-boot,dm-spl;
+};
+
+&buck5 {
+ u-boot,dm-spl;
+};
+
+&eqos {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&i2c3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c3_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+ u-boot,dm-spl;
+};
+
+&pmic {
+ u-boot,dm-spl;
+
+ regulators {
+ u-boot,dm-spl;
+ };
+};
+
+®_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&uart1 {
+ u-boot,dm-spl;
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ status = "disabled";
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
new file mode 100644
index 0000000..e95abfb
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/qca-ar803x.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mp-dhcom-som.dtsi"
+
+/ {
+ model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";
+ compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio-keys {
+ #size-cells = <0>;
+ compatible = "gpio-keys";
+
+ button-0 {
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
+ label = "TA1-GPIO-A";
+ linux,code = <KEY_A>;
+ pinctrl-0 = <&pinctrl_dhcom_a>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-1 {
+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
+ label = "TA2-GPIO-B";
+ linux,code = <KEY_B>;
+ pinctrl-0 = <&pinctrl_dhcom_b>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-2 {
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
+ label = "TA3-GPIO-C";
+ linux,code = <KEY_C>;
+ pinctrl-0 = <&pinctrl_dhcom_c>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-3 {
+ gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
+ label = "TA4-GPIO-D";
+ linux,code = <KEY_D>;
+ pinctrl-0 = <&pinctrl_dhcom_d>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+ };
+
+ led {
+ compatible = "gpio-leds";
+
+ led-5 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */
+ pinctrl-0 = <&pinctrl_dhcom_e>;
+ pinctrl-names = "default";
+ };
+
+ led-6 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
+ pinctrl-0 = <&pinctrl_dhcom_f>;
+ pinctrl-names = "default";
+ };
+
+ led-7 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */
+ pinctrl-0 = <&pinctrl_dhcom_h>;
+ pinctrl-names = "default";
+ };
+
+ led-8 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ pinctrl-0 = <&pinctrl_dhcom_i>;
+ pinctrl-names = "default";
+ };
+ };
+};
+
+/*
+ * PDK2 carrier board uses SoM with KSZ9131 populated and connected to
+ * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
+ */
+/delete-node/ ðphy0f;
+
+/*
+ * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
+ * ethernet RGMII interface. The SoM is not populated with second FEC PHY.
+ */
+/delete-node/ ðphy1f;
+
+&fec { /* Second ethernet */
+ phy-handle = <ðphypdk>;
+
+ mdio {
+ ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_ethphy1>;
+ pinctrl-names = "default";
+ reg = <7>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ rxc-skew-ps = <3000>;
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ rxdv-skew-ps = <0>;
+ txc-skew-ps = <3000>;
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ max-speed = <100>;
+ };
+ };
+};
+
+&flexcan1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ fsl,over-current-active-low;
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi
new file mode 100644
index 0000000..63cc6c9
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -0,0 +1,1042 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp.dtsi"
+
+/ {
+ model = "DH electronics i.MX8M Plus DHCOM SoM";
+ compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
+
+ aliases {
+ ethernet0 = &eqos;
+ ethernet1 = &fec;
+ rtc0 = &rv3032;
+ rtc1 = &snvs_rtc;
+ spi0 = &flexspi;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
+ reg = <0x0 0x40000000 0 0x08000000>;
+ };
+
+ reg_eth_vio: regulator-eth-vio {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_enet_vio>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "eth_vio";
+ vin-supply = <&buck4>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 19 0>; /* SD2_RESET */
+ off-on-delay-us = <12000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VDD_3V3_SD";
+ startup-delay-us = <100>;
+ vin-supply = <&buck4>;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+};
+
+&eqos { /* First ethernet */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-handle = <ðphy0g>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Up to one of these two PHYs may be populated. */
+ ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
+ compatible = "ethernet-phy-id0007.c110",
+ "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio3>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_ethphy0>;
+ pinctrl-names = "default";
+ reg = <1>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ /* Non-default PHY population option. */
+ status = "disabled";
+ };
+
+ ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
+ compatible = "ethernet-phy-id0022.1642",
+ "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio3>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <0>;
+ pinctrl-0 = <&pinctrl_ethphy0>;
+ pinctrl-names = "default";
+ reg = <5>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ /* Default PHY population option. */
+ status = "okay";
+ };
+ };
+};
+
+&fec { /* Second ethernet */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-handle = <ðphy1f>;
+ phy-mode = "rgmii";
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Up to one PHY may be populated. */
+ ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
+ compatible = "ethernet-phy-id0007.c110",
+ "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_ethphy1>;
+ pinctrl-names = "default";
+ reg = <1>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ /* Non-default PHY population option. */
+ status = "disabled";
+ };
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi>;
+ status = "okay";
+
+ flash@0 { /* W25Q128JWPIM */
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
+ "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "DHCOM-K", "", "", "", "",
+ "", "", "", "", "DHCOM-INT", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "SOM-HW0", "",
+ "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
+ "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "SOM-HW1", "", "", "", "",
+ "", "", "", "DHCOM-D", "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "DHCOM-C", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c3 {
+ /*
+ * iMX8MP 1P33A Errata ERR007805
+ * I2C is limited to 384 kHz due to SoC bug.
+ */
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic: pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+
+ /*
+ * i.MX 8M Plus Data Sheet for Consumer Products
+ * 3.1.4 Operating ranges
+ * MIMX8ML8CVNKZAB
+ */
+ regulators {
+ buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
+ regulator-compatible = "BUCK1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-ramp-delay = <3125>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck2: BUCK2 { /* VDD_ARM */
+ regulator-compatible = "BUCK2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-ramp-delay = <3125>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck4: BUCK4 { /* VDD_3V3 */
+ regulator-compatible = "BUCK4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck5: BUCK5 { /* VDD_1V8 */
+ regulator-compatible = "BUCK5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck6: BUCK6 { /* NVCC_DRAM_1V1 */
+ regulator-compatible = "BUCK6";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1: LDO1 { /* NVCC_SNVS_1V8 */
+ regulator-compatible = "LDO1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3: LDO3 { /* VDDA_1V8 */
+ regulator-compatible = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4: LDO4 { /* PMIC_LDO4 */
+ regulator-compatible = "LDO4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo5: LDO5 { /* NVCC_SD2 */
+ regulator-compatible = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+
+ adc@48 {
+ compatible = "ti,tla2024";
+ reg = <0x48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 { /* Voltage over AIN0 and AIN1. */
+ reg = <0>;
+ };
+
+ channel@1 { /* Voltage over AIN0 and AIN3. */
+ reg = <1>;
+ };
+
+ channel@2 { /* Voltage over AIN1 and AIN3. */
+ reg = <2>;
+ };
+
+ channel@3 { /* Voltage over AIN2 and AIN3. */
+ reg = <3>;
+ };
+
+ channel@4 { /* Voltage over AIN0 and GND. */
+ reg = <4>;
+ };
+
+ channel@5 { /* Voltage over AIN1 and GND. */
+ reg = <5>;
+ };
+
+ channel@6 { /* Voltage over AIN2 and GND. */
+ reg = <6>;
+ };
+
+ channel@7 { /* Voltage over AIN3 and GND. */
+ reg = <7>;
+ };
+ };
+
+ touchscreen@49 {
+ compatible = "ti,tsc2004";
+ reg = <0x49>;
+ interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ vio-supply = <&buck4>;
+ };
+
+ eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */
+ compatible = "atmel,24c02";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+
+ rv3032: rtc@51 {
+ compatible = "microcrystal,rv3032";
+ reg = <0x51>;
+ interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ };
+
+ eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */
+ compatible = "atmel,24c02";
+ pagesize = <16>;
+ reg = <0x53>;
+ };
+};
+
+&i2c4 {
+ /*
+ * iMX8MP 1P33A Errata ERR007805
+ * I2C is limited to 384 kHz due to SoC bug.
+ */
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c5 { /* HDMI EDID bus */
+ /*
+ * iMX8MP 1P33A Errata ERR007805
+ * I2C is limited to 384 kHz due to SoC bug.
+ */
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c5>;
+ pinctrl-1 = <&pinctrl_i2c5_gpio>;
+ scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-0 = <&pinctrl_pwm1>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
+&uart1 {
+ /* CA53 console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ /* Bluetooth */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_vbus>;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vmmc-supply = <&buck4>;
+ bus-width = <4>;
+ non-removable;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: bcrmf@1 { /* muRata 2AE */
+ reg = <1>;
+ compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
+ /*
+ * The "host-wake" interrupt output is by default not
+ * connected to the SoC, but can be connected on to
+ * SoC pin on the carrier board.
+ */
+ reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* SD slot */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ vmmc-supply = <&buck4>;
+ vqmmc-supply = <&buck5>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_hog_base
+ &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+ &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
+ &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+ /* GPIO_M is connected to CLKOUT2 */
+ &pinctrl_dhcom_int>;
+ pinctrl-names = "default";
+
+ pinctrl_dhcom_a: dhcom-a-grp {
+ fsl,pins = <
+ /* ENET_QOS_EVENT0-OUT */
+ MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2
+ >;
+ };
+
+ pinctrl_dhcom_b: dhcom-b-grp {
+ fsl,pins = <
+ /* ENET_QOS_EVENT0-IN */
+ MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2
+ >;
+ };
+
+ pinctrl_dhcom_c: dhcom-c-grp {
+ fsl,pins = <
+ /* GPIO_C */
+ MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2
+ >;
+ };
+
+ pinctrl_dhcom_d: dhcom-d-grp {
+ fsl,pins = <
+ /* GPIO_D */
+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2
+ >;
+ };
+
+ pinctrl_dhcom_e: dhcom-e-grp {
+ fsl,pins = <
+ /* GPIO_E */
+ MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2
+ >;
+ };
+
+ pinctrl_dhcom_f: dhcom-f-grp {
+ fsl,pins = <
+ /* GPIO_F */
+ MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2
+ >;
+ };
+
+ pinctrl_dhcom_g: dhcom-g-grp {
+ fsl,pins = <
+ /* GPIO_G */
+ MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2
+ >;
+ };
+
+ pinctrl_dhcom_h: dhcom-h-grp {
+ fsl,pins = <
+ /* GPIO_H */
+ MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2
+ >;
+ };
+
+ pinctrl_dhcom_i: dhcom-i-grp {
+ fsl,pins = <
+ /* CSI1_SYNC */
+ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
+ >;
+ };
+
+ pinctrl_dhcom_j: dhcom-j-grp {
+ fsl,pins = <
+ /* CSIx_#RST */
+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2
+ >;
+ };
+
+ pinctrl_dhcom_k: dhcom-k-grp {
+ fsl,pins = <
+ /* CSIx_PWDN */
+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2
+ >;
+ };
+
+ pinctrl_dhcom_l: dhcom-l-grp {
+ fsl,pins = <
+ /* CSI2_SYNC */
+ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2
+ >;
+ };
+
+ pinctrl_dhcom_int: dhcom-int-grp {
+ fsl,pins = <
+ /* INT_HIGHEST_PRIO */
+ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2
+ >;
+ };
+
+ pinctrl_hog_base: dhcom-hog-base-grp {
+ fsl,pins = <
+ /* GPIOs for memory coding */
+ MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080
+ MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080
+ MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080
+ /* GPIOs for hardware coding */
+ MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080
+ MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080
+ >;
+ };
+
+ pinctrl_ecspi1: dhcom-ecspi1-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44
+ MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44
+ MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44
+ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40
+ >;
+ };
+
+ pinctrl_ecspi2: dhcom-ecspi2-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
+ >;
+ };
+
+ pinctrl_eqos: dhcom-eqos-grp { /* RGMII */
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ >;
+ };
+
+ pinctrl_enet_vio: dhcom-enet-vio-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
+ >;
+ };
+
+ pinctrl_ethphy0: dhcom-ethphy0-grp {
+ fsl,pins = <
+ /* ENET1_#RST Reset */
+ MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
+ /* ENET1_#INT Interrupt */
+ MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
+ >;
+ };
+
+ pinctrl_ethphy1: dhcom-ethphy1-grp {
+ fsl,pins = <
+ /* ENET1_#RST Reset */
+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11
+ /* ENET1_#INT Interrupt */
+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11
+ >;
+ };
+
+ pinctrl_fec: dhcom-fec-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
+ MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f
+ >;
+ };
+
+ pinctrl_flexcan1: dhcom-flexcan1-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
+ >;
+ };
+
+ pinctrl_flexcan2: dhcom-flexcan2-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154
+ MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154
+ >;
+ };
+
+ pinctrl_flexspi: dhcom-flexspi-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
+ pinctrl_hdmi: dhcom-hdmi-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154
+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154
+ >;
+ };
+
+ pinctrl_i2c3: dhcom-i2c3-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
+ >;
+ };
+
+ pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
+ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
+ >;
+ };
+
+ pinctrl_i2c4: dhcom-i2c4-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084
+ >;
+ };
+
+ pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84
+ MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84
+ >;
+ };
+
+ pinctrl_i2c5: dhcom-i2c5-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x40000084
+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x40000084
+ >;
+ };
+
+ pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
+ MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
+ >;
+ };
+
+ pinctrl_pmic: dhcom-pmic-grp {
+ fsl,pins = <
+ /* PMIC_nINT */
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
+ >;
+ };
+
+ pinctrl_pwm1: dhcom-pwm1-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6
+ >;
+ };
+
+ pinctrl_rtc: dhcom-rtc-grp {
+ fsl,pins = <
+ /* RTC_#INT Interrupt */
+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6
+ >;
+ };
+
+ pinctrl_touch: dhcom-touch-grp {
+ fsl,pins = <
+ /* #TOUCH_INT */
+ MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080
+ >;
+ };
+
+ pinctrl_uart1: dhcom-uart1-grp {
+ fsl,pins = <
+ /* Console UART */
+ MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49
+ MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49
+ MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
+ MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49
+ >;
+ };
+
+ pinctrl_uart2: dhcom-uart2-grp {
+ fsl,pins = <
+ /* Bluetooth UART */
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
+ MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
+ MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
+ >;
+ };
+
+ pinctrl_uart3: dhcom-uart3-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49
+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49
+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49
+ >;
+ };
+
+ pinctrl_uart4: dhcom-uart4-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usb0_vbus: dhcom-usb0-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
+ >;
+ };
+
+ pinctrl_usb1_vbus: dhcom-usb1-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6
+ MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80
+ >;
+ };
+
+ pinctrl_usdhc1: dhcom-usdhc1-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
+ /* BT_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
+ /* WL_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
+ /* BT_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
+ /* WL_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
+ /* BT_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
+ /* WL_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
+ >;
+ };
+
+ pinctrl_usdhc2: dhcom-usdhc2-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
+ >;
+ };
+
+ pinctrl_usdhc3: dhcom-usdhc3-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
+ >;
+ };
+
+ pinctrl_wdog: dhcom-wdog-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 7aa9083..f43eb62 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -43,6 +43,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
index 476a8e3..e2f4b0e 100644
--- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
@@ -9,6 +9,14 @@
};
};
+&pinctrl_uart1 {
+ u-boot,dm-spl;
+};
+
+&uart1 {
+ u-boot,dm-spl;
+};
+
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 919c1f6..67da69a 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -2,30 +2,6 @@
#include "imx8mq-u-boot.dtsi"
-&{/soc@0} {
- u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30000000} {
- u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30400000} {
- u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000} {
- u-boot,dm-spl;
-};
-
-&{/soc@0/bus@32c00000} {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
-
&pinctrl_uart1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
index a65a942..8d6f305 100644
--- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
@@ -5,3 +5,11 @@
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
+
+&uart1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi b/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi
new file mode 100644
index 0000000..9537aed
--- /dev/null
+++ b/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+&pinctrl_uart1 {
+ u-boot,dm-spl;
+};
+
+&uart1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index 1dc060c..912a3d4 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -10,6 +10,30 @@
};
+&{/soc@0} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30000000} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30400000} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@32c00000} {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
&binman {
u-boot-spl-ddr {
align = <4>;
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 0f1e832..2ce8a8f 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -723,6 +723,7 @@
void update_umctl2_rank_space_setting(unsigned int pstat_num);
void get_trained_CDD(unsigned int fsp);
+unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr);
static inline void reg32_write(unsigned long addr, u32 val)
{
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b2a8ad7..1da7552 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -48,6 +48,16 @@
#ifdef CONFIG_IMX8MM
#define USDHC3_BASE_ADDR 0x30B60000
#endif
+#define UART_BASE_ADDR(n) ( \
+ !!sizeof(struct { \
+ static_assert((n) >= 1 && (n) <= 4); \
+ int pad; \
+ }) * ( \
+ (n) == 1 ? UART1_BASE_ADDR : \
+ (n) == 2 ? UART2_BASE_ADDR : \
+ (n) == 3 ? UART3_BASE_ADDR : \
+ UART4_BASE_ADDR) \
+ )
#define TZASC_BASE_ADDR 0x32F80000
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index 1856659..b3e6b3f 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -17,6 +17,7 @@
#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91
#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
#define AHAB_READ_FUSE_REQ_CID 0x97
+#define AHAB_GET_FW_VERSION_CID 0x9D
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
#define AHAB_WRITE_FUSE_REQ_CID 0xD6
#define AHAB_CAAM_RELEASE_CID 0xD7
@@ -39,6 +40,7 @@
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
int ahab_release_caam(u32 core_did, u32 *response);
+int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
#endif
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index d39f6b0..77794d7 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -179,16 +179,16 @@
#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
#define IMX_RTC_BASE (0x07000 + IMX_IO_BASE)
-#define UART1_BASE (0x0a000 + IMX_IO_BASE)
-#define UART2_BASE (0x0b000 + IMX_IO_BASE)
-#define UART3_BASE (0x0c000 + IMX_IO_BASE)
-#define UART4_BASE (0x0d000 + IMX_IO_BASE)
+#define UART1_BASE_ADDR (0x0a000 + IMX_IO_BASE)
+#define UART2_BASE_ADDR (0x0b000 + IMX_IO_BASE)
+#define UART3_BASE_ADDR (0x0c000 + IMX_IO_BASE)
+#define UART4_BASE_ADDR (0x0d000 + IMX_IO_BASE)
#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE)
#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
-#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
-#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
+#define UART5_BASE_ADDR (0x1b000 + IMX_IO_BASE)
+#define UART6_BASE_ADDR (0x1c000 + IMX_IO_BASE)
#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE)
#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
@@ -204,6 +204,18 @@
#define NFC_BASE_ADDR IMX_NFC_BASE
+#define UART_BASE_ADDR(n) ( \
+ !!sizeof(struct { \
+ static_assert((n) >= 1 && (n) <= 6); \
+ int pad; \
+ }) * ( \
+ (n) == 1 ? UART1_BASE_ADDR : \
+ (n) == 2 ? UART2_BASE_ADDR : \
+ (n) == 3 ? UART3_BASE_ADDR : \
+ (n) == 4 ? UART4_BASE_ADDR : \
+ (n) == 5 ? UART5_BASE_ADDR : \
+ UART6_BASE_ADDR) \
+ )
/* FMCR System Control bit definition*/
#define UART4_RXD_CTL (1 << 25)
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 566db54..d5c0ed8 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -598,6 +598,18 @@
#define UART4_BASE 0x43FB0000
#define UART5_BASE 0x43FB4000
+#define UART_BASE_ADDR(n) ( \
+ !!sizeof(struct { \
+ static_assert((n) >= 1 && (n) <= 5); \
+ int pad; \
+ }) * ( \
+ (n) == 1 ? UART1_BASE : \
+ (n) == 2 ? UART2_BASE : \
+ (n) == 3 ? UART3_BASE : \
+ (n) == 4 ? UART4_BASE : \
+ UART5_BASE_ADDR) \
+ )
+
#define I2C1_BASE_ADDR 0x43f80000
#define I2C1_CLK_OFFSET 26
#define I2C2_BASE_ADDR 0x43F98000
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index f119e9f..c54f52b 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -506,10 +506,6 @@
int ret = 0;
mtd = boot_cfg->mtd;
- if (mtd_block_isbad(mtd, off)) {
- printf("Block %d is bad, skipped\n", (int)CONV_TO_BLOCKS(off));
- return 1;
- }
fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
if (!fcb_raw_page) {
@@ -530,7 +526,7 @@
else if (plat_config.misc_flags & FCB_ENCODE_BCH_40b)
mxs_nand_mode_fcb_40bit(mtd);
- ret = nand_read(mtd, off, &size, (u_char *)fcb);
+ ret = nand_read_skip_bad(mtd, off, &size, NULL, mtd->size, (u_char *)fcb);
/* switch BCH back */
mxs_nand_mode_normal(mtd);
@@ -617,6 +613,7 @@
for (i = 0; i < g_boot_search_count; i++) {
if (mtd_block_isbad(mtd, off)) {
printf("Block %d is bad, skipped\n", i);
+ off += mtd->erasesize;
continue;
}
@@ -676,20 +673,15 @@
void *dbbt_data_page, loff_t off)
{
size_t size;
+ size_t actual_size;
struct mtd_info *mtd;
loff_t to;
int ret;
mtd = boot_cfg->mtd;
- if (mtd_block_isbad(mtd, off)) {
- printf("Block %d is bad, skipped\n",
- (int)CONV_TO_BLOCKS(off));
- return 1;
- }
-
size = sizeof(struct dbbt_block);
- ret = nand_read(mtd, off, &size, (u_char *)dbbt);
+ ret = nand_read_skip_bad(mtd, off, &size, &actual_size, mtd->size, (u_char *)dbbt);
printf("NAND DBBT read from 0x%llx offset 0x%zx read: %s\n",
off, size, ret ? "ERROR" : "OK");
if (ret)
@@ -697,9 +689,9 @@
/* dbbtpages == 0 if no bad blocks */
if (dbbt->dbbtpages > 0) {
- to = off + 4 * mtd->writesize;
+ to = off + 4 * mtd->writesize + actual_size - size;
size = mtd->writesize;
- ret = nand_read(mtd, to, &size, dbbt_data_page);
+ ret = nand_read_skip_bad(mtd, to, &size, NULL, mtd->size, dbbt_data_page);
printf("DBBT data read from 0x%llx offset 0x%zx read: %s\n",
to, size, ret ? "ERROR" : "OK");
@@ -729,6 +721,7 @@
if (mtd_block_isbad(mtd, off)) {
printf("Block %d is bad, skipped\n",
(int)(i + CONV_TO_BLOCKS(off)));
+ off += mtd->erasesize;
continue;
}
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 0858ea5..936c8f8 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -100,7 +100,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 24299ae..61397bf 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -148,6 +148,13 @@
select GATEWORKS_SC
select MISC
+config TARGET_IMX8MP_DH_DHCOM_PDK2
+ bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
+ select BINMAN
+ select IMX8MP
+ select IMX8M_LPDDR4
+ select SUPPORT_SPL
+
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
select BINMAN
@@ -265,6 +272,7 @@
source "board/bsh/imx8mn_smm_s2/Kconfig"
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
+source "board/dhelectronics/dh_imx8mp/Kconfig"
source "board/engicam/imx8mm/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 8e23e6d..5933535 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -72,15 +72,13 @@
* According to TRM, TZASC_ID_SWAP_BYPASS should be set in
* order to avoid AXI Bus errors when GPU is in use
*/
- if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp())
- setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
+ setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
/*
* imx8mn and imx8mp implements the lock bit for
* TZASC_ID_SWAP_BYPASS, enable it to lock settings
*/
- if (is_imx8mn() || is_imx8mp())
- setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
+ setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
/*
* set Region 0 attribute to allow secure and non-secure
@@ -1410,7 +1408,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
@@ -1535,6 +1533,16 @@
return ENVL_UNKNOWN;
switch (dev) {
+ case USB_BOOT:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+ return ENVL_NAND;
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+ return ENVL_MMC;
+ if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+ return ENVL_NOWHERE;
+ return ENVL_UNKNOWN;
case QSPI_BOOT:
case SPI_NOR_BOOT:
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
@@ -1563,3 +1571,29 @@
}
#endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+const struct rproc_att hostmap[] = {
+ /* aux core , host core, size */
+ { 0x00000000, 0x007e0000, 0x00020000 },
+ /* OCRAM_S */
+ { 0x00180000, 0x00180000, 0x00008000 },
+ /* OCRAM */
+ { 0x00900000, 0x00900000, 0x00020000 },
+ /* OCRAM */
+ { 0x00920000, 0x00920000, 0x00020000 },
+ /* QSPI Code - alias */
+ { 0x08000000, 0x08000000, 0x08000000 },
+ /* DDR (Code) - alias */
+ { 0x10000000, 0x80000000, 0x0FFE0000 },
+ /* TCML */
+ { 0x1FFE0000, 0x007E0000, 0x00040000 },
+ /* OCRAM_S */
+ { 0x20180000, 0x00180000, 0x00008000 },
+ /* OCRAM */
+ { 0x20200000, 0x00900000, 0x00040000 },
+ /* DDR (Data) */
+ { 0x40000000, 0x40000000, 0x80000000 },
+ { /* sentinel */ }
+};
+#endif
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 9ffe5ac..8115bf4 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -14,7 +14,13 @@
#include <linux/compiler.h>
#include <cpu_func.h>
-#ifndef CONFIG_IMX8M
+/* Just to avoid build error */
+#if CONFIG_IS_ENABLED(IMX8M)
+#define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
+#define SRC_M4_ENABLE_MASK BIT(0)
+#define SRC_M4_REG_OFFSET 0
+#endif
+
const __weak struct rproc_att hostmap[] = { };
static const struct rproc_att *get_host_mapping(unsigned long auxcore)
@@ -36,10 +42,11 @@
* is valid, returns the entry point address.
* Translates load addresses in the elf file to the U-Boot address space.
*/
-static unsigned long load_elf_image_m_core_phdr(unsigned long addr)
+static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack)
{
Elf32_Ehdr *ehdr; /* ELF header structure pointer */
Elf32_Phdr *phdr; /* Program header structure pointer */
+ int num = 0;
int i;
ehdr = (Elf32_Ehdr *)addr;
@@ -54,19 +61,24 @@
continue;
if (!mmap) {
- printf("Invalid aux core address: %08x",
+ printf("Invalid aux core address: %08x\n",
phdr->p_paddr);
return 0;
}
- dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa;
+ dst = (void *)(ulong)(phdr->p_paddr - mmap->da) + mmap->sa;
src = (void *)addr + phdr->p_offset;
debug("Loading phdr %i to 0x%p (%i bytes)\n",
i, dst, phdr->p_filesz);
- if (phdr->p_filesz)
+ if (phdr->p_filesz) {
memcpy(dst, src, phdr->p_filesz);
+ /* Stack in __isr_vector is the first section/word */
+ if (!num)
+ *stack = *(uint32_t *)src;
+ num++;
+ }
if (phdr->p_filesz != phdr->p_memsz)
memset(dst + phdr->p_filesz, 0x00,
phdr->p_memsz - phdr->p_filesz);
@@ -77,7 +89,6 @@
return ehdr->e_entry;
}
-#endif
int arch_auxiliary_core_up(u32 core_id, ulong addr)
{
@@ -86,20 +97,17 @@
if (!addr)
return -EINVAL;
-#ifdef CONFIG_IMX8M
- stack = *(u32 *)addr;
- pc = *(u32 *)(addr + 4);
-#else
/*
* handling ELF64 binaries
* isn't supported yet.
*/
if (valid_elf_image(addr)) {
- stack = 0x0;
- pc = load_elf_image_m_core_phdr(addr);
+ pc = load_elf_image_m_core_phdr(addr, &stack);
if (!pc)
return CMD_RET_FAILURE;
+ if (!CONFIG_IS_ENABLED(ARM64))
+ stack = 0x0;
} else {
/*
* Assume binary file with vector table at the beginning.
@@ -109,7 +117,7 @@
stack = *(u32 *)addr;
pc = *(u32 *)(addr + 4);
}
-#endif
+
printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
stack, pc);
@@ -120,36 +128,32 @@
flush_dcache_all();
/* Enable M4 */
-#ifdef CONFIG_IMX8M
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
- 0, 0, 0, 0, NULL);
-#else
- clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
- SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
-#endif
+ if (CONFIG_IS_ENABLED(IMX8M)) {
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
+ } else {
+ clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
+ SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
+ }
return 0;
}
int arch_auxiliary_core_check_up(u32 core_id)
{
-#ifdef CONFIG_IMX8M
struct arm_smccc_res res;
-
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
- 0, 0, 0, 0, &res);
-
- return res.a0;
-#else
unsigned int val;
+ if (CONFIG_IS_ENABLED(IMX8M)) {
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
+ return res.a0;
+ }
+
val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
if (val & SRC_M4C_NON_SCLR_RST_MASK)
return 0; /* assert in reset */
return 1;
-#endif
}
/*
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 947b73f..eceb730 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -347,6 +347,20 @@
select SUPPORT_SPL
imply CMD_DM
+config TARGET_MX6Q_ACC
+ bool "Support for Bosch ACC board"
+ depends on MX6QDL
+ select BOARD_LATE_INIT
+ select OF_CONTROL
+ select SPL_OF_LIBFDT
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
depends on MX6QDL
@@ -686,6 +700,7 @@
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
+source "board/bosch/acc/Kconfig"
source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pcl063/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 2434bcf..67bd991 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -744,7 +744,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
setup_serial_number();
return 0;
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index dc9ac31..c672be5 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -361,7 +361,7 @@
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 08bdc0c..217b7c4 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -93,7 +93,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 16981de..5fa4234 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -950,7 +950,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index 782025d..f129ebd 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -28,14 +28,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static const iomux_v3_cfg_t uart_pads[] = {
- MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -81,8 +75,6 @@
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
init_uart_clk(2);
return 0;
diff --git a/board/bosch/acc/Kconfig b/board/bosch/acc/Kconfig
new file mode 100644
index 0000000..da54d96
--- /dev/null
+++ b/board/bosch/acc/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_MX6Q_ACC
+
+config SYS_VENDOR
+ default "bosch"
+
+config SYS_BOARD
+ default "acc"
+
+config SYS_CONFIG_NAME
+ default "imx6q-bosch-acc"
+
+config SYS_BOOT_EMMC
+ bool "Boot from EMMC"
+ default y
+ help
+ Say N here if you want to boot from SD card or microUSB.
+ Say Y to boot from eMMC.
+
+endif
diff --git a/board/bosch/acc/MAINTAINERS b/board/bosch/acc/MAINTAINERS
new file mode 100644
index 0000000..1b88003
--- /dev/null
+++ b/board/bosch/acc/MAINTAINERS
@@ -0,0 +1,9 @@
+MX6Q_ACC
+M: Matthias Winker <matthias.winker@de.bosch.com>
+M: Philip Oberfichtner <pro@denx.de>
+S: Maintained
+F: board/bosch/acc
+F: include/configs/imx6q-bosch-acc.h
+F: configs/imx6q_bosch_acc_defconfig
+F: arch/arm/dts/imx6q-bosch-acc.dts
+F: arch/arm/dts/imx6q-bosch-acc-u-boot.dts
diff --git a/board/bosch/acc/Makefile b/board/bosch/acc/Makefile
new file mode 100644
index 0000000..d425a67
--- /dev/null
+++ b/board/bosch/acc/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2017
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := acc.o
diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c
new file mode 100644
index 0000000..dbc03c9
--- /dev/null
+++ b/board/bosch/acc/acc.c
@@ -0,0 +1,755 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
+ * Copyright (c) 2019 Bosch Thermotechnik GmbH
+ * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/device-internal.h>
+#include <env.h>
+#include <env_internal.h>
+#include <hang.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <fuse.h>
+
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_ACC_PLAT_DETECT IMX_GPIO_NR(5, 9)
+#define GPIO_ACC_RAM_VOLT_DETECT IMX_GPIO_NR(5, 0)
+#define GPIO_BUZZER IMX_GPIO_NR(1, 18)
+#define GPIO_LAN1_RESET IMX_GPIO_NR(4, 27)
+#define GPIO_LAN2_RESET IMX_GPIO_NR(4, 19)
+#define GPIO_LAN3_RESET IMX_GPIO_NR(4, 18)
+#define GPIO_USB_HUB_RESET IMX_GPIO_NR(5, 5)
+#define GPIO_EXP_RS485_RESET IMX_GPIO_NR(4, 16)
+#define GPIO_TOUCH_RESET IMX_GPIO_NR(1, 20)
+
+#define BOARD_INFO_MAGIC 0x19730517
+
+struct board_info {
+ int magic;
+ int board;
+ int rev;
+};
+
+static struct board_info *detect_board(void);
+
+#define PFID_BOARD_ACC 0xe
+
+static const char * const name_board[] = {
+ [PFID_BOARD_ACC] = "ACC",
+};
+
+#define PFID_REV_22 0x8
+#define PFID_REV_21 0x9
+#define PFID_REV_20 0xa
+#define PFID_REV_14 0xb
+#define PFID_REV_13 0xc
+#define PFID_REV_12 0xd
+#define PFID_REV_11 0xe
+#define PFID_REV_10 0xf
+
+static const char * const name_revision[] = {
+ [0 ... PFID_REV_10] = "Unknown",
+ [PFID_REV_10] = "1.0",
+ [PFID_REV_11] = "1.1",
+ [PFID_REV_12] = "1.2",
+ [PFID_REV_13] = "1.3",
+ [PFID_REV_14] = "1.4",
+ [PFID_REV_20] = "2.0",
+ [PFID_REV_21] = "2.1",
+ [PFID_REV_22] = "2.2",
+};
+
+/*
+ * NXP Reset Default: 0x0001B0B0
+ * - Schmitt trigger input (PAD_CTL_HYS)
+ * - 100K Ohm Pull Up (PAD_CTL_PUS_100K_UP)
+ * - Pull Enabled (PAD_CTL_PUE)
+ * - Pull/Keeper Enabled (PAD_CTL_PKE)
+ * - CMOS output (No PAD_CTL_ODE)
+ * - Medium Speed (PAD_CTL_SPEED_MED)
+ * - 40 Ohm drive strength (PAD_CTL_DSE_40ohm)
+ * - Slow (PAD_CTL_SRE_SLOW)
+ */
+
+/* Input, no pull up/down: 0x0x000100B0 */
+#define GPIN_PAD_CTRL (PAD_CTL_HYS \
+ | PAD_CTL_SPEED_MED \
+ | PAD_CTL_DSE_40ohm \
+ | PAD_CTL_SRE_SLOW)
+
+/* Input, pull up: 0x0x0001B0B0 */
+#define GPIN_PU_PAD_CTRL (PAD_CTL_HYS \
+ | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_PUE \
+ | PAD_CTL_PKE \
+ | PAD_CTL_SPEED_MED \
+ | PAD_CTL_DSE_40ohm \
+ | PAD_CTL_SRE_SLOW)
+
+/* Input, pull down: 0x0x000130B0 */
+#define GPIN_PD_PAD_CTRL (PAD_CTL_HYS \
+ | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_PUE \
+ | PAD_CTL_PKE \
+ | PAD_CTL_SPEED_MED \
+ | PAD_CTL_DSE_40ohm \
+ | PAD_CTL_SRE_SLOW)
+
+static const iomux_v3_cfg_t board_detect_pads[] = {
+ /* Platform detect */
+ IOMUX_PADS(PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ /* RAM Volt detect */
+ IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ /* PFID 0..9 */
+ IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ /* Manufacturer */
+ IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+ /* Redundant */
+ IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIN_PU_PAD_CTRL))
+};
+
+static int gpio_acc_pfid[] = {
+ IMX_GPIO_NR(2, 0),
+ IMX_GPIO_NR(2, 1),
+ IMX_GPIO_NR(2, 2),
+ IMX_GPIO_NR(2, 3),
+ IMX_GPIO_NR(2, 4),
+ IMX_GPIO_NR(6, 14),
+ IMX_GPIO_NR(6, 15),
+ IMX_GPIO_NR(2, 5),
+ IMX_GPIO_NR(2, 6),
+ IMX_GPIO_NR(2, 7),
+ IMX_GPIO_NR(6, 16),
+ IMX_GPIO_NR(5, 4),
+};
+
+static int init_gpio(int nr)
+{
+ int ret;
+
+ ret = gpio_request(nr, "");
+ if (ret != 0) {
+ printf("Could not request gpio nr: %d\n", nr);
+ hang();
+ }
+ ret = gpio_direction_input(nr);
+ if (ret != 0) {
+ printf("Could not set gpio nr: %d to input\n", nr);
+ hang();
+ }
+ return 0;
+}
+
+/*
+ * We want to detect the board type only once in SPL,
+ * so we store the board_info struct at beginning in IRAM.
+ *
+ * U-Boot itself can read it also, and do not need again
+ * to detect board type.
+ *
+ */
+static struct board_info *detect_board(void)
+{
+ struct board_info *binfo = (struct board_info *)IRAM_BASE_ADDR;
+ int i;
+
+ if (binfo->magic == BOARD_INFO_MAGIC)
+ return binfo;
+
+ puts("Board: ");
+ SETUP_IOMUX_PADS(board_detect_pads);
+ init_gpio(GPIO_ACC_PLAT_DETECT);
+ if (gpio_get_value(GPIO_ACC_PLAT_DETECT)) {
+ puts("not supported");
+ hang();
+ } else {
+ puts("Bosch ");
+ }
+
+ for (i = 0; i < sizeof(gpio_acc_pfid) / sizeof(int); i++)
+ init_gpio(gpio_acc_pfid[i]);
+
+ binfo->board = gpio_get_value(gpio_acc_pfid[0]) << 0 |
+ gpio_get_value(gpio_acc_pfid[1]) << 1 |
+ gpio_get_value(gpio_acc_pfid[2]) << 2 |
+ gpio_get_value(gpio_acc_pfid[11]) << 3;
+ printf("%s ", name_board[binfo->board]);
+
+ binfo->rev = gpio_get_value(gpio_acc_pfid[7]) << 0 |
+ gpio_get_value(gpio_acc_pfid[8]) << 1 |
+ gpio_get_value(gpio_acc_pfid[9]) << 2 |
+ gpio_get_value(gpio_acc_pfid[10]) << 3;
+ printf("rev: %s\n", name_revision[binfo->rev]);
+
+ binfo->magic = BOARD_INFO_MAGIC;
+
+ return binfo;
+}
+
+static void unset_early_gpio(void)
+{
+ init_gpio(GPIO_LAN1_RESET);
+ init_gpio(GPIO_LAN2_RESET);
+ init_gpio(GPIO_LAN3_RESET);
+ init_gpio(GPIO_USB_HUB_RESET);
+ init_gpio(GPIO_EXP_RS485_RESET);
+ init_gpio(GPIO_TOUCH_RESET);
+
+ gpio_set_value(GPIO_LAN1_RESET, 1);
+ gpio_set_value(GPIO_LAN2_RESET, 1);
+ gpio_set_value(GPIO_LAN3_RESET, 1);
+ gpio_set_value(GPIO_USB_HUB_RESET, 1);
+ gpio_set_value(GPIO_EXP_RS485_RESET, 1);
+ gpio_set_value(GPIO_TOUCH_RESET, 1);
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+ return ENVL_MMC;
+
+ switch (prio) {
+ case 0:
+ return ENVL_NOWHERE;
+
+ case 1:
+ return ENVL_MMC;
+ }
+
+ return ENVL_UNKNOWN;
+}
+
+int board_late_init(void)
+{
+ struct board_info *binfo = detect_board();
+
+ switch (binfo->board) {
+ case PFID_BOARD_ACC:
+ env_set("bootconf", "conf-imx6q-bosch-acc.dtb");
+ break;
+ default:
+ printf("Unknown board %d\n", binfo->board);
+ break;
+ }
+
+ unset_early_gpio();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+/* Early
+ * - Buzzer -> GPIO IN, Pull-Down (PWM enabled by Kernel later-on, lacks of an
+ * external pull-down resistor)
+ * - Touch clean reset on every boot
+ * - Ethernet(s), USB Hub, Expansion RS485 -> Clean reset on each u-boot init
+ */
+static const iomux_v3_cfg_t early_pads[] = {
+ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* Buzzer PWM */
+ IOMUX_PADS(PAD_DISP0_DAT6__GPIO4_IO27 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #FEC_RESET_B */
+ IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH1_RESET */
+ IOMUX_PADS(PAD_DI0_PIN3__GPIO4_IO19 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH2_RESET */
+ IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #USB Reset */
+ IOMUX_PADS(PAD_DI0_DISP_CLK__GPIO4_IO16 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #UART_RESET */
+ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #CTOUCH_RESET */
+};
+
+static void setup_iomux_early(void)
+{
+ SETUP_IOMUX_PADS(early_pads);
+}
+
+static void set_early_gpio(void)
+{
+ init_gpio(GPIO_BUZZER);
+ init_gpio(GPIO_LAN1_RESET);
+ init_gpio(GPIO_LAN2_RESET);
+ init_gpio(GPIO_LAN3_RESET);
+ init_gpio(GPIO_USB_HUB_RESET);
+ init_gpio(GPIO_EXP_RS485_RESET);
+ init_gpio(GPIO_TOUCH_RESET);
+
+ /* Reset signals are active low */
+ gpio_set_value(GPIO_BUZZER, 0);
+ gpio_set_value(GPIO_LAN1_RESET, 0);
+ gpio_set_value(GPIO_LAN2_RESET, 0);
+ gpio_set_value(GPIO_LAN3_RESET, 0);
+ gpio_set_value(GPIO_USB_HUB_RESET, 0);
+ gpio_set_value(GPIO_EXP_RS485_RESET, 0);
+ gpio_set_value(GPIO_TOUCH_RESET, 0);
+}
+
+/* UART */
+#define UART_PAD_CTRL \
+ (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#undef UART_PAD_CTRL
+#define UART_PAD_CTRL 0x1b0b1
+static const iomux_v3_cfg_t uart2_pads[] = {
+ IOMUX_PADS(PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CLK__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart2_pads);
+}
+
+void spl_board_init(void)
+{
+}
+
+static const struct mx6dq_iomux_ddr_regs acc_mx6d_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00008038,
+ .dram_sdclk_1 = 0x00008038,
+ .dram_cas = 0x00008028,
+ .dram_ras = 0x00008028,
+ .dram_reset = 0x00000028,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00008000,
+ .dram_sdodt0 = 0x00000028,
+ .dram_sdodt1 = 0x00000028,
+ .dram_sdqs0 = 0x00008038,
+ .dram_sdqs1 = 0x00008038,
+ .dram_sdqs2 = 0x00008038,
+ .dram_sdqs3 = 0x00008038,
+ .dram_sdqs4 = 0x00008038,
+ .dram_sdqs5 = 0x00008038,
+ .dram_sdqs6 = 0x00008038,
+ .dram_sdqs7 = 0x00008038,
+ .dram_dqm0 = 0x00008038,
+ .dram_dqm1 = 0x00008038,
+ .dram_dqm2 = 0x00008038,
+ .dram_dqm3 = 0x00008038,
+ .dram_dqm4 = 0x00008038,
+ .dram_dqm5 = 0x00008038,
+ .dram_dqm6 = 0x00008038,
+ .dram_dqm7 = 0x00008038,
+};
+
+static const struct mx6dq_iomux_grp_regs acc_mx6d_grp_ioregs = {
+ .grp_ddr_type = 0x000C0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x00000030,
+ .grp_ctlds = 0x00000028,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000038,
+ .grp_b1ds = 0x00000038,
+ .grp_b2ds = 0x00000038,
+ .grp_b3ds = 0x00000038,
+ .grp_b4ds = 0x00000038,
+ .grp_b5ds = 0x00000038,
+ .grp_b6ds = 0x00000038,
+ .grp_b7ds = 0x00000038,
+};
+
+static const struct mx6_mmdc_calibration acc_mx6d_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x0020001F,
+ .p0_mpwldectrl1 = 0x00280021,
+ .p1_mpwldectrl0 = 0x00120028,
+ .p1_mpwldectrl1 = 0x000D001F,
+ .p0_mpdgctrl0 = 0x43340342,
+ .p0_mpdgctrl1 = 0x03300325,
+ .p1_mpdgctrl0 = 0x4334033E,
+ .p1_mpdgctrl1 = 0x03280270,
+ .p0_mprddlctl = 0x46373B3E,
+ .p1_mprddlctl = 0x3B383544,
+ .p0_mpwrdlctl = 0x36383E40,
+ .p1_mpwrdlctl = 0x4030433A,
+};
+
+/* Micron MT41K128M16JT-125 (standard - 1600,CL=11)
+ * !!! i.MX6 does NOT support data rates higher than DDR3-1066 !!!
+ * So this setting is actually invalid!
+ *
+static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1600 = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 0,
+};
+ */
+
+/* Micron MT41K128M16JT-125 is backward-compatible with 1333,CL=9 (-15E) and 1066,CL=7 (-187E)
+ * Lowering to 1066 saves on ACC ~0.25 Watt at DC In with negligible performance loss
+ * width set to 64, as four chips are used on acc (4 * 16 = 64)
+ */
+static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = {
+ .mem_speed = 1066,
+ .density = 2,
+ .width = 64,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1313, // 13.125ns
+ .trcmin = 5063, // 50.625ns
+ .trasmin = 3750, // 37.5ns
+ .SRT = 0, // Set to 1 for temperatures above 85°C
+};
+
+static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = {
+ .ddr_type = DDR_TYPE_DDR3,
+ /* width of data bus:0=16,1=32,2=64 */
+ .dsize = 2,
+ .cs_density = 32, /* 32Gb per CS */
+ .ncs = 1, /* single chip select */
+ .cs1_mirror = 0,
+ .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+ .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+ .walat = 0, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x33, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x33, /* 33 cycles, 500us (JEDEC default) */
+};
+
+#define ACC_SPREAD_SPECTRUM_STOP 0x0fa
+#define ACC_SPREAD_SPECTRUM_STEP 0x001
+#define ACC_SPREAD_SPECTRUM_DENOM 0x190
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* Turn clocks on/off */
+ writel(0x00C0000F, &ccm->CCGR0);
+ writel(0x0030FC00, &ccm->CCGR1);
+ writel(0x03FF0033, &ccm->CCGR2);
+ writel(0x3FF3300F, &ccm->CCGR3);
+ writel(0x0003C300, &ccm->CCGR4);
+ writel(0x0F3000C3, &ccm->CCGR5);
+ writel(0x00000FFF, &ccm->CCGR6);
+
+ /* Enable spread spectrum */
+ writel(BM_ANADIG_PLL_528_SS_ENABLE |
+ BF_ANADIG_PLL_528_SS_STOP(ACC_SPREAD_SPECTRUM_STOP) |
+ BF_ANADIG_PLL_528_SS_STEP(ACC_SPREAD_SPECTRUM_STEP),
+ &ccm->analog_pll_528_ss);
+
+ writel(BF_ANADIG_PLL_528_DENOM_B(ACC_SPREAD_SPECTRUM_DENOM),
+ &ccm->analog_pll_528_denom);
+}
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) && !IS_ENABLED(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+
+static const iomux_v3_cfg_t usdhc2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(0x00017069)),
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(0x00010038)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(0x00017069)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(0x00017069)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(0x00017069)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(0x00017069)),
+ IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(0x0001B0B0)), /* CD */
+};
+
+static const iomux_v3_cfg_t usdhc4_pads[] = {
+ IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(0x00017059)),
+ IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(0x00010059)),
+ IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(0x00017059)),
+ IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(0x00017059)),
+ IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(0x00017059)),
+ IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(0x00017059)),
+ IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(0x00017059)),
+ IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(0x00017059)),
+ IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(0x00017059)),
+ IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(0x00017059)),
+};
+
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC2_BASE_ADDR, 1, 4},
+ {USDHC4_BASE_ADDR, 1, 8},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ detect_board();
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ return !gpio_get_value(USDHC2_CD_GPIO);
+ case USDHC4_BASE_ADDR:
+ return 1; /* eMMC always present */
+ }
+
+ return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+
+ gpio_direction_input(USDHC2_CD_GPIO);
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC2
+ * mmc1 USDHC4
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ SETUP_IOMUX_PADS(usdhc4_pads);
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning - USDHC%d controller not supporting\n",
+ i + 1);
+ return 0;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bmode = imx6_src_get_boot_mode();
+ u8 boot_dev = BOOT_DEVICE_MMC1;
+
+ detect_board();
+
+ switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
+ case IMX6_BMODE_SD:
+ case IMX6_BMODE_ESD:
+ /* SD/eSD - BOOT_DEVICE_MMC1 */
+ if (IS_ENABLED(CONFIG_SYS_BOOT_EMMC)) {
+ /*
+ * boot from SD is not allowed, if boot from eMMC is
+ * configured.
+ */
+ puts("SD boot not allowed\n");
+ spl_boot_list[0] = BOOT_DEVICE_NONE;
+ return;
+ }
+
+ boot_dev = BOOT_DEVICE_MMC1;
+ break;
+
+ case IMX6_BMODE_MMC:
+ case IMX6_BMODE_EMMC:
+ /* MMC/eMMC */
+ boot_dev = BOOT_DEVICE_MMC2;
+ break;
+ default:
+ /* Default - BOOT_DEVICE_MMC1 */
+ printf("Wrong board boot order\n");
+ break;
+ }
+
+ spl_boot_list[0] = boot_dev;
+}
+
+static void setup_ddr(void)
+{
+ struct board_info *binfo = detect_board();
+
+ switch (binfo->rev) {
+ case PFID_REV_20:
+ case PFID_REV_21:
+ case PFID_REV_22:
+ default:
+ /* Rev 2 board has i.MX6 Dual with 64-bit RAM */
+ mx6dq_dram_iocfg(acc_mx6d_mem_ddr3_1066.width,
+ &acc_mx6d_ddr_ioregs,
+ &acc_mx6d_grp_ioregs);
+ mx6_dram_cfg(&acc_mx6d_ddr_info, &acc_mx6d_mmdc_calib,
+ &acc_mx6d_mem_ddr3_1066);
+ /* Perform DDR DRAM calibration */
+ udelay(100);
+ mmdc_do_write_level_calibration(&acc_mx6d_ddr_info);
+ mmdc_do_dqs_calibration(&acc_mx6d_ddr_info);
+ break;
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog power-down counter (only enabled after reset) */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* Enable device tree and early DM support*/
+ spl_early_init();
+
+ /* Setup early required pinmuxes */
+ setup_iomux_early();
+ set_early_gpio();
+
+ /* Setup UART pinmux */
+ setup_iomux_uart();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ setup_ddr();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
+
+#if IS_ENABLED(CONFIG_USB_EHCI_MX6)
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL BIT(9)
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "imx6q-bosch-acc"))
+ return 0;
+ return -1;
+}
+
+void reset_cpu(ulong addr)
+{
+ puts("Hanging CPU for watchdog reset!\n");
+ hang();
+}
+
+#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
+void show_boot_progress(int val)
+{
+ u32 fuseval;
+ int ret;
+
+ if (val < 0)
+ val *= -1;
+
+ switch (val) {
+ case BOOTSTAGE_ID_ENTER_CLI_LOOP:
+ printf("autoboot failed, check fuse\n");
+ ret = fuse_read(0, 6, &fuseval);
+ if (ret == 0 && (fuseval & 0x2) == 0x0) {
+ printf("Enter cmdline, as device not closed\n");
+ return;
+ }
+ ret = fuse_read(5, 7, &fuseval);
+ if (ret == 0 && fuseval == 0x0) {
+ printf("Enter cmdline, as it is a Development device\n");
+ return;
+ }
+ panic("do not enter cmdline");
+ break;
+ }
+}
+#endif
diff --git a/board/bsh/imx8mn_smm_s2/spl.c b/board/bsh/imx8mn_smm_s2/spl.c
index 0f61acc..ce0504a 100644
--- a/board/bsh/imx8mn_smm_s2/spl.c
+++ b/board/bsh/imx8mn_smm_s2/spl.c
@@ -40,19 +40,8 @@
puts("Failed to find clock node. Check device tree\n");
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset(wdog);
-
init_uart_clk(3);
if (IS_ENABLED(CONFIG_NAND_MXS)) {
@@ -83,6 +72,8 @@
preloader_console_init();
+ enable_tzc380();
+
/* DDR initialization */
spl_dram_init();
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
index 5b93491..b230478 100644
--- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
@@ -24,33 +24,6 @@
#include <linux/delay.h>
-static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
-{
- unsigned int tmp;
-
- reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
- do {
- tmp = reg32_read(DDRC_MRSTAT(0));
- } while (tmp & 0x1);
-
- reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
- reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
- reg32setbit(DDRC_MRCTRL0(0), 31);
- do {
- tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
- } while ((tmp & 0x8) == 0);
- tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
- reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
- while (tmp) { //try to find a significant byte in the word
- if (tmp & 0xff) {
- tmp &= 0xff;
- break;
- }
- tmp >>= 8;
- }
- return tmp;
-}
-
struct lpddr4_desc {
char name[16];
unsigned int id;
diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c
index 36cad14..f5063eb 100644
--- a/board/data_modul/imx8mm_edm_sbc/spl.c
+++ b/board/data_modul/imx8mm_edm_sbc/spl.c
@@ -28,14 +28,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static const iomux_v3_cfg_t uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -47,8 +41,6 @@
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static int data_modul_imx8mm_edm_sbc_board_power_init(void)
@@ -149,8 +141,6 @@
data_modul_imx8mm_edm_sbc_early_init_f();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -160,6 +150,8 @@
hang();
}
+ preloader_console_init();
+
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index 2969e90a..e8aba83 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -100,9 +100,9 @@
return 0;
}
- eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
+ eeprom = ofnode_get_aliases_node("eeprom0");
if (!ofnode_valid(eeprom)) {
- printf("Invalid hardware path to EEPROM!\n");
+ printf("Can't find eeprom0 alias!\n");
return -ENODEV;
}
@@ -225,16 +225,35 @@
}
#ifdef CONFIG_MULTI_DTB_FIT
+static int strcmp_prefix(const char *s1, const char *s2)
+{
+ size_t n;
+
+ n = min(strlen(s1), strlen(s2));
+ return strncmp(s1, s2, n);
+}
+
int board_fit_config_name_match(const char *name)
{
- if (is_mx6dq()) {
- if (!strcmp(name, "imx6q-dhcom-pdk2"))
- return 0;
- } else if (is_mx6sdl()) {
- if (!strcmp(name, "imx6dl-dhcom-pdk2"))
+ char *want;
+ char *have;
+
+ /* Test Board suffix, e.g. -dhcom-drc02 */
+ want = strchr(CONFIG_DEFAULT_DEVICE_TREE, '-');
+ have = strchr(name, '-');
+
+ if (!want || !have || strcmp(want, have))
+ return -EINVAL;
+
+ /* Test SoC prefix */
+ if (is_mx6dq() && !strcmp_prefix(name, "imx6q-"))
+ return 0;
+
+ if (is_mx6sdl()) {
+ if (!strcmp_prefix(name, "imx6s-") || !strcmp_prefix(name, "imx6dl-"))
return 0;
}
- return -1;
+ return -EINVAL;
}
#endif
diff --git a/board/dhelectronics/dh_imx8mp/Kconfig b/board/dhelectronics/dh_imx8mp/Kconfig
new file mode 100644
index 0000000..8fb80a0
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MP_DH_DHCOM_PDK2
+
+config SYS_BOARD
+ default "dh_imx8mp"
+
+config SYS_VENDOR
+ default "dhelectronics"
+
+config SYS_CONFIG_NAME
+ default "imx8mp_dhcom_pdk2"
+
+config IMX_CONFIG
+ default "board/dhelectronics/dh_imx8mp/imximage-lpddr4.cfg"
+
+endif
diff --git a/board/dhelectronics/dh_imx8mp/MAINTAINERS b/board/dhelectronics/dh_imx8mp/MAINTAINERS
new file mode 100644
index 0000000..7c70cfd
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/MAINTAINERS
@@ -0,0 +1,8 @@
+DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: arch/arm/dts/imx8mp-dhcom-pdk2.dts
+F: arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
+F: board/dhelectronics/imx8mp_dhcom_pdk2/
+F: configs/imx8mp_dhcom_pdk2_defconfig
+F: include/configs/imx8mp_dhcom_pdk2.h
diff --git a/board/dhelectronics/dh_imx8mp/Makefile b/board/dhelectronics/dh_imx8mp/Makefile
new file mode 100644
index 0000000..86ffc31
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2022 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o lpddr4_timing_4G_32.o
+else
+obj-y += imx8mp_dhcom_pdk2.o
+endif
+
+obj-y += common.o
diff --git a/board/dhelectronics/dh_imx8mp/common.c b/board/dhelectronics/dh_imx8mp/common.c
new file mode 100644
index 0000000..44456da
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/common.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u8 dh_get_memcfg(void)
+{
+ struct gpio_desc gpio[4];
+ u8 memcfg = 0;
+ ofnode node;
+ int i, ret;
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node)) {
+ printf("%s: no /config node?\n", __func__);
+ return BIT(2) | BIT(0);
+ }
+
+ ret = gpio_request_list_by_name_nodev(node,
+ "dh,ram-coding-gpios",
+ gpio, ARRAY_SIZE(gpio),
+ GPIOD_IS_IN);
+ for (i = 0; i < ret; i++)
+ memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+ gpio_free_list_nodev(gpio, ret);
+
+ return memcfg;
+}
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
new file mode 100644
index 0000000..8676c44
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <i2c_eeprom.h>
+#include <malloc.h>
+#include <net.h>
+#include <miiphy.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+ icache_enable();
+ return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
+ u8 memcfg = dh_get_memcfg();
+
+ *size = (u64)memsz[memcfg] << 20ULL;
+
+ return 0;
+}
+
+/* IMX8M SNVS registers needed for the bootcount functionality */
+#define SNVS_BASE_ADDR 0x30370000
+#define SNVS_LPSR 0x4c
+#define SNVS_LPLVDR 0x64
+#define SNVS_LPPGDR_INIT 0x41736166
+
+static void setup_snvs(void)
+{
+ /* Enable SNVS clock */
+ clock_enable(CCGR_SNVS, 1);
+ /* Initialize glitch detect */
+ writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
+ /* Clear interrupt status */
+ writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
+}
+
+static void setup_eqos(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Set INTF as RGMII, enable RGMII TXC clock. */
+ clrsetbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+ setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+ set_clk_eqos(ENET_125MHZ);
+}
+
+static void setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Enable RGMII TX clk output. */
+ setbits_le32(&gpr->gpr[1], BIT(22));
+
+ set_clk_enet(ENET_125MHZ);
+}
+
+static int setup_mac_address_from_eeprom(char *alias, char *env, bool odd)
+{
+ unsigned char enetaddr[6];
+ struct udevice *dev;
+ int ret, offset;
+
+ offset = fdt_path_offset(gd->fdt_blob, alias);
+ if (offset < 0) {
+ printf("%s: No eeprom0 path offset\n", __func__);
+ return offset;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, offset, &dev);
+ if (ret) {
+ printf("Cannot find EEPROM!\n");
+ return ret;
+ }
+
+ ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
+ if (ret) {
+ printf("Error reading configuration EEPROM!\n");
+ return ret;
+ }
+
+ /*
+ * Populate second ethernet MAC from first ethernet EEPROM with MAC
+ * address LSByte incremented by 1. This is only used on SoMs without
+ * second ethernet EEPROM, i.e. early prototypes.
+ */
+ if (odd)
+ enetaddr[5]++;
+
+ eth_env_set_enetaddr(env, enetaddr);
+
+ return 0;
+}
+
+static void setup_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ bool skip_eth0 = false;
+ bool skip_eth1 = false;
+ int ret;
+
+ ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+ if (ret) /* ethaddr is already set */
+ skip_eth0 = true;
+
+ ret = eth_env_get_enetaddr("eth1addr", enetaddr);
+ if (ret) /* eth1addr is already set */
+ skip_eth1 = true;
+
+ /* Both MAC addresses are already set in U-Boot environment. */
+ if (skip_eth0 && skip_eth1)
+ return;
+
+ /*
+ * If IIM fuses contain valid MAC address, use it.
+ * The IIM MAC address fuses are NOT programmed by default.
+ */
+ imx_get_mac_from_fuse(0, enetaddr);
+ if (is_valid_ethaddr(enetaddr)) {
+ if (!skip_eth0)
+ eth_env_set_enetaddr("ethaddr", enetaddr);
+ /*
+ * The LSbit of MAC address in fuses is always 0, use the
+ * next consecutive MAC address for the second ethernet.
+ */
+ enetaddr[5]++;
+ if (!skip_eth1)
+ eth_env_set_enetaddr("eth1addr", enetaddr);
+ return;
+ }
+
+ /* Use on-SoM EEPROMs with pre-programmed MAC address. */
+ if (!skip_eth0) {
+ /* We cannot do much more if this returns -ve . */
+ setup_mac_address_from_eeprom("eeprom0", "ethaddr", false);
+ }
+
+ if (!skip_eth1) {
+ ret = setup_mac_address_from_eeprom("eeprom1", "eth1addr",
+ false);
+ if (ret) { /* Second EEPROM might not be populated. */
+ /* We cannot do much more if this returns -ve . */
+ setup_mac_address_from_eeprom("eeprom0", "eth1addr",
+ true);
+ }
+ }
+}
+
+int board_init(void)
+{
+ setup_eqos();
+ setup_fec();
+ setup_snvs();
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_mac_address();
+ return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
+}
diff --git a/board/dhelectronics/dh_imx8mp/imximage-lpddr4.cfg b/board/dhelectronics/dh_imx8mp/imximage-lpddr4.cfg
new file mode 100644
index 0000000..8aadedb
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/imximage-lpddr4.cfg
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x920000
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
new file mode 100644
index 0000000..6d496a9
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
+
+u8 dh_get_memcfg(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
new file mode 100644
index 0000000..2eda4a5
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
@@ -0,0 +1,1844 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x1323 },
+ { 0x3d400024, 0x1c79100 },
+ { 0x3d400064, 0x710106 },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc0030720 },
+ { 0x3d4000d4, 0xb80000 },
+ { 0x3d4000dc, 0xe40036 },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x1e262028 },
+ { 0x3d400104, 0x7073b },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x11040a11 },
+ { 0x3d400114, 0x2050e0e },
+ { 0x3d400118, 0x1010008 },
+ { 0x3d40011c, 0x501 },
+ { 0x3d400130, 0x20700 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x10d },
+ { 0x3d400144, 0xbb005e },
+ { 0x3d400180, 0x3a5001c },
+ { 0x3d400184, 0x2f071e5 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49b820c },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x810191a },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1021 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1021 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x3a5 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xe94 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x36e4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x36e4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xe400 },
+ { 0x54033, 0x3336 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xe400 },
+ { 0x54039, 0x3336 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xe94 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x36e4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x36e4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xe400 },
+ { 0x54033, 0x3336 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xe400 },
+ { 0x54039, 0x3336 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x419 },
+ { 0x2000c, 0xe9 },
+ { 0x2000d, 0x91c },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x70 },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x1c },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3732mts 1D */
+ .drate = 3732,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3732mts 2D */
+ .drate = 3732,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3732, 400, 100, },
+};
diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c
new file mode 100644
index 0000000..312e4b9
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+ MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX8MP_PAD_SAI2_RXC__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+ MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static void dh_imx8mp_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static int dh_imx8mp_board_power_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("Failed to get PMIC\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output. */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
+ if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
+ /* Set DVS0 to 0.85V for special case. */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
+
+ /* Set DVS1 to 0.85v for suspend. */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+
+ /*
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
+ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ /* Kernel uses OD/OD frequency for SoC. */
+
+ /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+
+ /* Set WDOG_B_CFG to cold reset. */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+ /* Set LDO4 and CONFIG2 to enable the I2C level translator. */
+ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
+ pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
+
+ return 0;
+}
+
+static struct dram_timing_info *dram_timing_info[8] = {
+ NULL, /* 512 MiB */
+ NULL, /* 1024 MiB */
+ NULL, /* 1536 MiB */
+ NULL, /* 2048 MiB */
+ NULL, /* 3072 MiB */
+ &dh_imx8mp_dhcom_dram_timing_32g_x32, /* 4096 MiB */
+ NULL, /* 6144 MiB */
+ NULL, /* 8192 MiB */
+};
+
+static void spl_dram_init(void)
+{
+ const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
+ u8 memcfg = dh_get_memcfg();
+ int i;
+
+ printf("DDR: %d MiB [0x%x]\n", size[memcfg], memcfg);
+
+ if (!dram_timing_info[memcfg]) {
+ printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
+ memcfg);
+ for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++)
+ if (dram_timing_info[i]) /* Configuration found */
+ break;
+ }
+
+ ddr_init(dram_timing_info[memcfg]);
+}
+
+void spl_board_init(void)
+{
+ /*
+ * Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
+ * allow to change it. Should set the clock after PMIC setting done.
+ * Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
+ * ND VDD_SOC.
+ */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+}
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(0);
+
+ dh_imx8mp_early_init_f();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0) {
+ printf("Failed to find clock node. Check device tree\n");
+ hang();
+ }
+
+ enable_tzc380();
+
+ dh_imx8mp_board_power_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 7eeec6c..4d96324 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -57,7 +57,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
puts("Normal Boot\n");
}
@@ -72,23 +72,6 @@
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -135,8 +118,6 @@
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 63f335b..14cb513 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -52,7 +52,7 @@
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
puts("Normal Boot\n");
@@ -115,23 +115,6 @@
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
void board_init_f(ulong dummy)
{
int ret;
@@ -140,8 +123,6 @@
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c
index fb6c61c..8971a82 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -20,23 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index 503a752..719b1f6 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -43,7 +43,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
@@ -134,8 +134,6 @@
init_uart_clk(1);
- board_early_init_f();
-
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index 66bfc2b..ece9ff2 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -58,6 +58,23 @@
return 0;
}
+void display_ele_fw_version(void)
+{
+ u32 fw_version, sha1, res;
+ int ret;
+
+ ret = ahab_get_fw_version(&fw_version, &sha1, &res);
+ if (ret) {
+ printf("ahab get firmware version failed %d, 0x%x\n", ret, res);
+ } else {
+ printf("ELE firmware version %u.%u.%u-%x",
+ (fw_version & (0x00ff0000)) >> 16,
+ (fw_version & (0x0000ff00)) >> 8,
+ (fw_version & (0x000000ff)), sha1);
+ ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n");
+ }
+}
+
void spl_board_init(void)
{
struct udevice *dev;
@@ -77,6 +94,8 @@
puts("Normal Boot\n");
+ display_ele_fw_version();
+
/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
/* Load the lposc fuse to work around ROM issue. The fuse depends on S400 to read. */
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
deleted file mode 100644
index 46448a5..0000000
--- a/board/gateworks/gw_ventana/gsc.c
+++ /dev/null
@@ -1,471 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Gateworks Corporation
- *
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <common.h>
-#include <i2c.h>
-#include <linux/ctype.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-#include <dm/device.h>
-#include <dm/uclass.h>
-
-#include "ventana_eeprom.h"
-#include "gsc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(DM_I2C)
-struct udevice *i2c_get_dev(int busno, int slave)
-{
- struct udevice *dev, *bus;
- int ret;
-
- ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
- if (ret)
- return NULL;
- ret = dm_i2c_probe(bus, slave, 0, &dev);
- if (ret)
- return NULL;
-
- return dev;
-}
-#endif
-
-/*
- * The Gateworks System Controller will fail to ACK a master transaction if
- * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
- * When this does occur, it will never be busy long enough to fail more than
- * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
- * 3 retries.
- */
-int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
-{
- int retry = 3;
- int n = 0;
- int ret;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- dev = i2c_get_dev(CONFIG_I2C_GSC, chip);
- if (!dev)
- return -ENODEV;
- ret = i2c_set_chip_offset_len(dev, alen);
- if (ret) {
- puts("EEPROM: Failed to set alen\n");
- return ret;
- }
-#else
- i2c_set_bus_num(CONFIG_I2C_GSC);
-#endif
-
- while (n++ < retry) {
-#if CONFIG_IS_ENABLED(DM_I2C)
- ret = dm_i2c_read(dev, addr, buf, len);
-#else
- ret = i2c_read(chip, addr, alen, buf, len);
-#endif
- if (!ret)
- break;
- debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
- n, ret);
- if (ret != -EREMOTEIO)
- break;
- mdelay(10);
- }
- return ret;
-}
-
-int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
-{
- int retry = 3;
- int n = 0;
- int ret;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- dev = i2c_get_dev(CONFIG_I2C_GSC, chip);
- if (!dev)
- return -ENODEV;
- ret = i2c_set_chip_offset_len(dev, alen);
- if (ret) {
- puts("EEPROM: Failed to set alen\n");
- return ret;
- }
-#endif
-
- while (n++ < retry) {
-#if CONFIG_IS_ENABLED(DM_I2C)
- ret = dm_i2c_write(dev, addr, buf, len);
-#else
- ret = i2c_write(chip, addr, alen, buf, len);
-#endif
- if (!ret)
- break;
- debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
- n, ret);
- if (ret != -EREMOTEIO)
- break;
- mdelay(10);
- }
- mdelay(100);
- return ret;
-}
-
-int gsc_get_board_temp(void)
-{
- const void *fdt = gd->fdt_blob;
- int node, reg, mode, val;
- const char *label;
- u8 buf[2];
- int ret;
-
- node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
- if (node <= 0)
- return node;
-
- /* iterate over hwmon nodes */
- node = fdt_first_subnode(fdt, node);
- while (node > 0) {
- reg = fdtdec_get_int(fdt, node, "reg", -1);
- mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
- label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
-
- if ((reg == -1) || (mode == -1) || !label) {
- printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
- continue;
- }
-
- if ((mode != 0) || strcmp(label, "temp"))
- continue;
-
- memset(buf, 0, sizeof(buf));
- ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf));
- val = buf[0] | buf[1] << 8;
- if (val >= 0) {
- if (val > 0x8000)
- val -= 0xffff;
- return val;
- }
- node = fdt_next_subnode(fdt, node);
- }
-
- return 0;
-}
-
-/* display hardware monitor ADC channels */
-int gsc_hwmon(void)
-{
- const void *fdt = gd->fdt_blob;
- int node, reg, mode, len, val, offset;
- const char *label;
- u8 buf[2];
- int ret;
-
- node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
- if (node <= 0)
- return node;
-
- /* iterate over hwmon nodes */
- node = fdt_first_subnode(fdt, node);
- while (node > 0) {
- reg = fdtdec_get_int(fdt, node, "reg", -1);
- mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
- offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0);
- label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
-
- if ((reg == -1) || (mode == -1) || !label)
- printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
-
- memset(buf, 0, sizeof(buf));
- ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf));
- val = buf[0] | buf[1] << 8;
- if (val >= 0) {
- const u32 *div;
- int r[2];
-
- switch (mode) {
- case 0: /* temperature (C*10) */
- if (val > 0x8000)
- val -= 0xffff;
- printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
- break;
- case 1: /* prescaled voltage */
- if (val != 0xffff)
- printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
- break;
- case 2: /* scaled based on ref volt and resolution */
- val *= 2500;
- val /= 1 << 12;
-
- /* apply pre-scaler voltage divider */
- div = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len);
- if (div && (len == sizeof(uint32_t) * 2)) {
- r[0] = fdt32_to_cpu(div[0]);
- r[1] = fdt32_to_cpu(div[1]);
- if (r[0] && r[1]) {
- val *= (r[0] + r[1]);
- val /= r[1];
- }
- }
-
- /* adjust by offset */
- val += (offset / 1000);
-
- printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
- break;
- }
- }
- node = fdt_next_subnode(fdt, node);
- }
-
- return 0;
-}
-
-int gsc_info(int verbose)
-{
- unsigned char buf[16];
-
- if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
- return CMD_RET_FAILURE;
-
- printf("GSC: v%d", buf[GSC_SC_FWVER]);
- printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
- printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
- ? "en" : "dis");
- if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
- buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
- puts(" WDT_RESET");
- gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
- &buf[GSC_SC_STATUS], 1);
- }
- printf(" board temp at %dC", gsc_get_board_temp() / 10);
- puts("\n");
- if (!verbose)
- return CMD_RET_SUCCESS;
-
- gsc_hwmon();
-
- return 0;
-}
-
-/*
- * The Gateworks System Controller implements a boot
- * watchdog (always enabled) as a workaround for IMX6 boot related
- * errata such as:
- * ERR005768 - no fix scheduled
- * ERR006282 - fixed in silicon r1.2
- * ERR007117 - fixed in silicon r1.3
- * ERR007220 - fixed in silicon r1.3
- * ERR007926 - no fix scheduled
- * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
- *
- * Disable the boot watchdog
- */
-int gsc_boot_wd_disable(void)
-{
- u8 reg;
-
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
- reg |= (1 << GSC_SC_CTRL1_WDDIS);
- if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return 0;
- }
- puts("Error: could not disable GSC Watchdog\n");
- return 1;
-}
-
-/* determine BOM revision from model */
-int get_bom_rev(const char *str)
-{
- int rev_bom = 0;
- int i;
-
- for (i = strlen(str) - 1; i > 0; i--) {
- if (str[i] == '-')
- break;
- if (str[i] >= '1' && str[i] <= '9') {
- rev_bom = str[i] - '0';
- break;
- }
- }
- return rev_bom;
-}
-
-/* determine PCB revision from model */
-char get_pcb_rev(const char *str)
-{
- char rev_pcb = 'A';
- int i;
-
- for (i = strlen(str) - 1; i > 0; i--) {
- if (str[i] == '-')
- break;
- if (str[i] >= 'A') {
- rev_pcb = str[i];
- break;
- }
- }
- return rev_pcb;
-}
-
-/*
- * get dt name based on model and detail level:
- */
-const char *gsc_get_dtb_name(int level, char *buf, int sz)
-{
- const char *model = (const char *)ventana_info.model;
- const char *pre = is_mx6dq() ? "imx6q-" : "imx6dl-";
- int modelno, rev_pcb, rev_bom;
-
- /* a few board models are dt equivalents to other models */
- if (strncasecmp(model, "gw5906", 6) == 0)
- model = "gw552x-d";
- else if (strncasecmp(model, "gw5908", 6) == 0)
- model = "gw53xx-f";
- else if (strncasecmp(model, "gw5905", 6) == 0)
- model = "gw5904-a";
-
- modelno = ((model[2] - '0') * 1000)
- + ((model[3] - '0') * 100)
- + ((model[4] - '0') * 10)
- + (model[5] - '0');
- rev_pcb = tolower(get_pcb_rev(model));
- rev_bom = get_bom_rev(model);
-
- /* compare model/rev/bom in order of most specific to least */
- snprintf(buf, sz, "%s%04d", pre, modelno);
- switch (level) {
- case 0: /* full model first (ie gw5400-a1) */
- if (rev_bom) {
- snprintf(buf, sz, "%sgw%04d-%c%d", pre, modelno, rev_pcb, rev_bom);
- break;
- }
- fallthrough;
- case 1: /* don't care about bom rev (ie gw5400-a) */
- snprintf(buf, sz, "%sgw%04d-%c", pre, modelno, rev_pcb);
- break;
- case 2: /* don't care about the pcb rev (ie gw5400) */
- snprintf(buf, sz, "%sgw%04d", pre, modelno);
- break;
- case 3: /* look for generic model (ie gw540x) */
- snprintf(buf, sz, "%sgw%03dx", pre, modelno / 10);
- break;
- case 4: /* look for more generic model (ie gw54xx) */
- snprintf(buf, sz, "%sgw%02dxx", pre, modelno / 100);
- break;
- default: /* give up */
- return NULL;
- }
-
- return buf;
-}
-
-#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD)
-static int do_gsc_sleep(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- unsigned char reg;
- unsigned long secs = 0;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- secs = dectoul(argv[1], NULL);
- printf("GSC Sleeping for %ld seconds\n", secs);
-
- reg = (secs >> 24) & 0xff;
- if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1))
- goto error;
- reg = (secs >> 16) & 0xff;
- if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1))
- goto error;
- reg = (secs >> 8) & 0xff;
- if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1))
- goto error;
- reg = secs & 0xff;
- if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1))
- goto error;
- if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- goto error;
- reg |= (1 << 2);
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- goto error;
- reg &= ~(1 << 2);
- reg |= 0x3;
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- goto error;
-
- return CMD_RET_SUCCESS;
-
-error:
- printf("i2c error\n");
- return CMD_RET_FAILURE;
-}
-
-static int do_gsc_wd(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- unsigned char reg;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- if (strcasecmp(argv[1], "enable") == 0) {
- int timeout = 0;
-
- if (argc > 2)
- timeout = dectoul(argv[2], NULL);
- if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return CMD_RET_FAILURE;
- reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
- if (timeout == 60)
- reg |= (1 << GSC_SC_CTRL1_WDTIME);
- else
- timeout = 30;
- reg |= (1 << GSC_SC_CTRL1_WDEN);
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return CMD_RET_FAILURE;
- printf("GSC Watchdog enabled with timeout=%d seconds\n",
- timeout);
- } else if (strcasecmp(argv[1], "disable") == 0) {
- if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return CMD_RET_FAILURE;
- reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return CMD_RET_FAILURE;
- printf("GSC Watchdog disabled\n");
- } else {
- return CMD_RET_USAGE;
- }
- return CMD_RET_SUCCESS;
-}
-
-static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- if (argc < 2)
- return gsc_info(1);
-
- if (strcasecmp(argv[1], "wd") == 0)
- return do_gsc_wd(cmdtp, flag, --argc, ++argv);
- else if (strcasecmp(argv[1], "sleep") == 0)
- return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
-
- return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
- gsc, 4, 1, do_gsc, "GSC configuration",
- "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
- );
-
-#endif /* CONFIG_CMD_GSC */
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index c06630a..99f52b9 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -32,9 +32,10 @@
int board_phy_config(struct phy_device *phydev)
{
unsigned short val;
+ ofnode node;
- /* Marvel 88E1510 */
- if (phydev->phy_id == 0x1410dd1) {
+ switch (phydev->phy_id) {
+ case 0x1410dd1:
puts("MV88E1510");
/*
* Page 3, Register 16: LED[2:0] Function Control Register
@@ -47,10 +48,8 @@
val |= 0x0017;
phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
- }
-
- /* TI DP83867 */
- else if (phydev->phy_id == 0x2000a231) {
+ break;
+ case 0x2000a231:
puts("TIDP83867 ");
/* LED configuration */
val = 0;
@@ -66,6 +65,22 @@
val &= ~0x1f00;
val |= 0x0b00; /* chD tx clock*/
phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
+ break;
+ case 0xd565a401:
+ puts("GPY111 ");
+ node = phy_get_ofnode(phydev);
+ if (ofnode_valid(node)) {
+ u32 rx_delay, tx_delay;
+
+ rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
+ tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
+ val &= ~((0x7 << 12) | (0x7 << 8));
+ val |= (rx_delay / 500) << 12;
+ val |= (tx_delay / 500) << 8;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
+ }
+ break;
}
if (phydev->drv->config)
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 223f22d..6e6ce01 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -87,37 +87,20 @@
ddr_init(dram_timing);
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#ifdef CONFIG_IMX8MM
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#elif CONFIG_IMX8MN
-static const iomux_v3_cfg_t uart_pads[] = {
- IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#elif CONFIG_IMX8MP
-static const iomux_v3_cfg_t uart_pads[] = {
- MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
-
#endif
int board_early_init_f(void)
@@ -128,8 +111,6 @@
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -276,8 +257,6 @@
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -287,6 +266,8 @@
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index 9545e63..61ab384 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -226,16 +226,21 @@
static int detect_lvds(struct display_info_t const *dev)
{
+ struct udevice *idev, *ibus;
u8 touchid[23];
u8 *touchptr = &touchid[0];
int ret;
- ret = i2c_set_bus_num(0);
+ ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &ibus);
+ if (ret)
+ return 0;
+
+ ret = dm_i2c_probe(ibus, 0x38, 0, &idev);
if (ret)
return 0;
/* Touchscreen is at address 0x38, ID register is 0xbb. */
- ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
+ ret = dm_i2c_read(idev, 0xbb, touchid, sizeof(touchid));
if (ret)
return 0;
@@ -385,23 +390,6 @@
return 0;
}
-#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
- static const iomux_v3_cfg_t i2c_pads[] = {
- /* I2C1 */
- NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
- /* I2C2 */
- NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
static void setup_iomux_video(void)
{
static const iomux_v3_cfg_t lcd_pads[] = {
@@ -505,7 +493,6 @@
{
setup_iomux_uart();
setup_iomux_fec();
- setup_iomux_i2c();
setup_iomux_nand();
setup_iomux_video();
diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c
index a4d0bec..9d3708a 100644
--- a/board/menlo/mx8menlo/mx8menlo.c
+++ b/board/menlo/mx8menlo/mx8menlo.c
@@ -12,19 +12,6 @@
#include <asm/mach-imx/iomux-v3.h>
#include <spl.h>
-#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-/* Verdin UART_3, Console/Debug UART */
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
#define SNVS_BASE_ADDR 0x30370000
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
@@ -42,14 +29,6 @@
void board_early_init(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
init_uart_clk(1);
setup_snvs();
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index 1f3f383..037fd27 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -74,30 +74,10 @@
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-/* Verdin UART_3, Console/Debug UART */
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
__weak void board_early_init(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
init_uart_clk(0);
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
int power_init_board(void)
@@ -143,8 +123,6 @@
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -162,6 +140,8 @@
hang();
}
+ preloader_console_init();
+
enable_tzc380();
power_init_board();
diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
index 8334c9b..e3c1a12 100644
--- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c
+++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
@@ -24,7 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/* Verdin UART_3, Console/Debug UART */
static const iomux_v3_cfg_t uart_pads[] = {
@@ -32,18 +31,8 @@
MX8MP_PAD_UART3_TXD__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static const iomux_v3_cfg_t wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(2);
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index fc61b44..82a10ff 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -43,15 +43,12 @@
ulong size, void *dst)
{
int err;
-#ifdef CONFIG_SYS_NAND_BLOCK_SIZE
ulong sector;
sector = *(int *)load->priv;
- offs = sector + nand_spl_adjust_offset(sector, offs - sector);
-#else
offs *= load->bl_len;
size *= load->bl_len;
-#endif
+ offs = sector + nand_spl_adjust_offset(sector, offs - sector);
err = nand_spl_load_image(offs, size, dst);
if (err)
return 0;
diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
index 2cf882f..c53fa74 100644
--- a/configs/cgtqmx8_defconfig
+++ b/configs/cgtqmx8_defconfig
@@ -1,6 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SYS_MALLOC_LEN=0x2400000
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index c45561a..558619f 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -53,7 +53,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2"
+CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02 imx6dl-dhcom-picoitx"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
new file mode 100644
index 0000000..3c02f0f
--- /dev/null
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17780000
+CONFIG_SYS_MALLOC_LEN=0x01000000
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x1fe000
+CONFIG_MX6QDL=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_MX6Q_ACC=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-bosch-acc"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=8
+CONFIG_SPL_SIZE_LIMIT=69632
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x1ff000
+CONFIG_IMX_HAB=y
+# CONFIG_CMD_BMODE is not set
+# CONFIG_CMD_DEKBLOB is not set
+CONFIG_BUILD_TARGET=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa
+# CONFIG_SPL_CRC32 is not set
+# CONFIG_SPL_CRYPTO is not set
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_FUSE is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+# CONFIG_CMD_PINMUX is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+# CONFIG_CMD_SLEEP is not set
+# CONFIG_CMD_MP is not set
+# CONFIG_CMD_HASH is not set
+CONFIG_CMD_EXT4=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_APPEND=y
+CONFIG_ENV_WRITEABLE_LIST=y
+CONFIG_ENV_ACCESS_IGNORE_FORCE=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_TFTP_BLOCKSIZE=512
+CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_EXT4_WRITE=y
+CONFIG_FS_FAT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 0bde51a..8b3d1b3 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -1,6 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO=y
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index d734586..b418e86 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -1,6 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index 0d3e19e..a416495 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -105,6 +105,7 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index edceb18..5eb99c5 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -200,7 +200,6 @@
CONFIG_RTC_M41T62=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index 490de19..0165a4e 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -113,7 +113,6 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index 56a30744..bc1cfa4 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -41,6 +41,8 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
@@ -82,4 +84,14 @@
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index 639fee7..63a6549 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -112,7 +112,6 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
new file mode 100644
index 0000000..2764152
--- /dev/null
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -0,0 +1,244 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xFE0000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk2"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_ENV_OFFSET_REDUND=0xFF0000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-pdk2.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_SMC=y
+CONFIG_HASH_VERIFY=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
+CONFIG_ENV_SPI_MAX_HZ=80000000
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x0
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 081f7e0..c3ffed8 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -27,7 +27,6 @@
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index a7585ba..323a7ea 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -1,6 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
@@ -135,6 +133,7 @@
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_S35392A=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index 5d06dc4..3feb639 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -1,6 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
@@ -136,6 +134,7 @@
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_S35392A=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index 97c8bb5..626ac24 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -112,7 +112,6 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig
index 1cca21e..8e02460 100644
--- a/configs/imx8mq_cm_defconfig
+++ b/configs/imx8mq_cm_defconfig
@@ -78,6 +78,7 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index a86311b..095e42e 100644
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -83,5 +83,6 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig
index 1375c78..f07b789 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -37,7 +37,7 @@
CONFIG_SPL_ATF=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_LZMADEC is not set
-# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index df4907a..90d3e59 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -11,9 +11,6 @@
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
CONFIG_TARGET_M53MENLO=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo"
CONFIG_SPL_TEXT_BASE=0x70008000
@@ -53,7 +50,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -75,8 +71,7 @@
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
@@ -102,6 +97,7 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
CONFIG_RTC_M41T62=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 12789c9..79057f7 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -12,7 +12,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 2bfeac3..2f90262 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -14,7 +14,7 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SPI_BOOT=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 09d71ae..5a43a55 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -23,7 +23,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
index 809fcce..b949b5e 100644
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@@ -14,7 +14,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
index 1b55ad3..3fea1b1 100644
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -15,7 +15,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig
index 1b0d12c..91aca29 100644
--- a/configs/pico-imx8mq_defconfig
+++ b/configs/pico-imx8mq_defconfig
@@ -83,5 +83,6 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index a52c4ac..9e6829b 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -149,12 +149,20 @@
driver_hash[caam_algo].digestsize,
1);
+ flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len);
+ flush_dcache_range((ulong)ctx->sha_desc,
+ (ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE));
+ flush_dcache_range((ulong)ctx->hash,
+ (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
+
ret = run_descriptor_jr(ctx->sha_desc);
if (ret) {
debug("Error %x\n", ret);
return ret;
} else {
+ invalidate_dcache_range((ulong)ctx->hash,
+ (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
}
free(ctx);
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 1d951cf..acd2992 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -623,7 +623,7 @@
static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
{
- int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
+ int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY;
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 inst_handles;
@@ -652,6 +652,15 @@
* the RNG.
*/
ret = instantiate_rng(sec_idx, sec, gen_sk);
+ /*
+ * entropy delay is calculated via self-test method.
+ * self-test are run across different volatge, temp.
+ * if worst case value for ent_dly is identified,
+ * loop can be skipped for that platform.
+ */
+ if (IS_ENABLED(CONFIG_MX6SX))
+ break;
+
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
@@ -758,8 +767,14 @@
return -1;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
- if (ofnode_valid(scu_node))
+ if (ofnode_valid(scu_node)) {
+ if (IS_ENABLED(CONFIG_DM_RNG)) {
+ ret = device_bind_driver(NULL, "caam-rng", "caam-rng", NULL);
+ if (ret)
+ printf("Couldn't bind rng driver (%d)\n", ret);
+ }
return ret;
+ }
#endif
#ifdef CONFIG_FSL_CORENET
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index a54449e..975d553 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -198,9 +198,14 @@
tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
} while ((tmp & 0x8) == 0);
tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
- tmp = tmp & 0xff;
reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
-
+ while (tmp) { //try to find a significant byte in the word
+ if (tmp & 0xff) {
+ tmp &= 0xff;
+ break;
+ }
+ tmp >>= 8;
+ }
return tmp;
}
diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c
index 0e2874c..175e460 100644
--- a/drivers/gpio/imx_rgpio2p.c
+++ b/drivers/gpio/imx_rgpio2p.c
@@ -39,6 +39,14 @@
return val & (1 << offset) ? 1 : 0;
}
+static int imx_rgpio2p_bank_get_direction(struct gpio_regs *regs, int offset)
+{
+ if ((readl(®s->gpio_pddr) >> offset) & 0x01)
+ return IMX_RGPIO2P_DIRECTION_OUT;
+
+ return IMX_RGPIO2P_DIRECTION_IN;
+}
+
static void imx_rgpio2p_bank_direction(struct gpio_regs *regs, int offset,
enum imx_rgpio2p_direction direction)
{
@@ -67,7 +75,11 @@
static int imx_rgpio2p_bank_get_value(struct gpio_regs *regs, int offset)
{
- return (readl(®s->gpio_pdir) >> offset) & 0x01;
+ if (imx_rgpio2p_bank_get_direction(regs, offset) ==
+ IMX_RGPIO2P_DIRECTION_IN)
+ return (readl(®s->gpio_pdir) >> offset) & 0x01;
+
+ return (readl(®s->gpio_pdor) >> offset) & 0x01;
}
static int imx_rgpio2p_direction_input(struct udevice *dev, unsigned offset)
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index 3ffdeb2..87f5880 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -272,6 +272,47 @@
return ret;
}
+int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (!fw_version) {
+ printf("Invalid parameters for f/w version read\n");
+ return -EINVAL;
+ }
+
+ if (!sha1) {
+ printf("Invalid parameters for commit sha1\n");
+ return -EINVAL;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_GET_FW_VERSION_CID;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ *fw_version = msg.data[1];
+ *sha1 = msg.data[2];
+
+ return ret;
+}
+
int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
{
struct udevice *dev = gd->arch.s400_dev;
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index ee5d7fd..7893e9d 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -1246,22 +1246,6 @@
/* Enable BCH complete interrupt */
writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
- /* Hook some operations at the MTD level. */
- if (mtd->_read_oob != mxs_nand_hook_read_oob) {
- nand_info->hooked_read_oob = mtd->_read_oob;
- mtd->_read_oob = mxs_nand_hook_read_oob;
- }
-
- if (mtd->_write_oob != mxs_nand_hook_write_oob) {
- nand_info->hooked_write_oob = mtd->_write_oob;
- mtd->_write_oob = mxs_nand_hook_write_oob;
- }
-
- if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
- nand_info->hooked_block_markbad = mtd->_block_markbad;
- mtd->_block_markbad = mxs_nand_hook_block_markbad;
- }
-
return 0;
}
@@ -1380,6 +1364,9 @@
else
nand_info->max_ecc_strength_supported = 40;
+ if (IS_ENABLED(CONFIG_NAND_MXS_USE_MINIMUM_ECC))
+ nand_info->use_minimum_ecc = true;
+
err = mxs_nand_alloc_buffers(nand_info);
if (err)
return err;
@@ -1467,6 +1454,22 @@
if (err)
goto err_free_buffers;
+ /* Hook some operations at the MTD level. */
+ if (mtd->_read_oob != mxs_nand_hook_read_oob) {
+ nand_info->hooked_read_oob = mtd->_read_oob;
+ mtd->_read_oob = mxs_nand_hook_read_oob;
+ }
+
+ if (mtd->_write_oob != mxs_nand_hook_write_oob) {
+ nand_info->hooked_write_oob = mtd->_write_oob;
+ mtd->_write_oob = mxs_nand_hook_write_oob;
+ }
+
+ if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
+ nand_info->hooked_block_markbad = mtd->_block_markbad;
+ mtd->_block_markbad = mxs_nand_hook_block_markbad;
+ }
+
err = nand_register(0, mtd);
if (err)
goto err_free_buffers;
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c
index 59a67ee..2bfb181 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -218,14 +218,14 @@
mxs_nand_setup_ecc(mtd);
}
-int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
- struct nand_chip *chip;
- unsigned int page;
+ unsigned int sz;
+ unsigned int block, lastblock;
+ unsigned int page, page_offset;
unsigned int nand_page_per_block;
- unsigned int sz = 0;
+ struct nand_chip *chip;
u8 *page_buf = NULL;
- u32 page_off;
chip = mtd_to_nand(mtd);
if (!chip->numchips)
@@ -235,47 +235,42 @@
if (!page_buf)
return -ENOMEM;
- page = offs >> chip->page_shift;
- page_off = offs & (mtd->writesize - 1);
+ /* offs has to be aligned to a page address! */
+ block = offs / mtd->erasesize;
+ lastblock = (offs + size - 1) / mtd->erasesize;
+ page = (offs % mtd->erasesize) / mtd->writesize;
+ page_offset = offs % mtd->writesize;
nand_page_per_block = mtd->erasesize / mtd->writesize;
- debug("%s offset:0x%08x len:%d page:%x\n", __func__, offs, size, page);
+ while (block <= lastblock && size > 0) {
+ if (!is_badblock(mtd, mtd->erasesize * block, 1)) {
+ /* Skip bad blocks */
+ while (page < nand_page_per_block) {
+ int curr_page = nand_page_per_block * block + page;
- while (size) {
- if (mxs_read_page_ecc(mtd, page_buf, page) < 0)
- return -1;
-
- if (size > (mtd->writesize - page_off))
- sz = (mtd->writesize - page_off);
- else
- sz = size;
-
- memcpy(buf, page_buf + page_off, sz);
-
- offs += mtd->writesize;
- page++;
- buf += (mtd->writesize - page_off);
- page_off = 0;
- size -= sz;
-
- /*
- * Check if we have crossed a block boundary, and if so
- * check for bad block.
- */
- if (!(page % nand_page_per_block)) {
- /*
- * Yes, new block. See if this block is good. If not,
- * loop until we find a good block.
- */
- while (is_badblock(mtd, offs, 1)) {
- page = page + nand_page_per_block;
- /* Check i we've reached the end of flash. */
- if (page >= mtd->size >> chip->page_shift) {
+ if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) {
free(page_buf);
- return -ENOMEM;
+ return -EIO;
}
+
+ if (size > (mtd->writesize - page_offset))
+ sz = (mtd->writesize - page_offset);
+ else
+ sz = size;
+
+ memcpy(dst, page_buf + page_offset, sz);
+ dst += sz;
+ size -= sz;
+ page_offset = 0;
+ page++;
}
+
+ page = 0;
+ } else {
+ lastblock++;
}
+
+ block++;
}
free(page_buf);
@@ -294,6 +289,19 @@
u32 nand_spl_adjust_offset(u32 sector, u32 offs)
{
- /* Handle the offset adjust in nand_spl_load_image,*/
+ unsigned int block, lastblock;
+
+ block = sector / mtd->erasesize;
+ lastblock = (sector + offs) / mtd->erasesize;
+
+ while (block <= lastblock) {
+ if (is_badblock(mtd, block * mtd->erasesize, 1)) {
+ offs += mtd->erasesize;
+ lastblock++;
+ }
+
+ block++;
+ }
+
return offs;
}
diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c
index 2394b19..116ac49 100644
--- a/drivers/power/pmic/pca9450.c
+++ b/drivers/power/pmic/pca9450.c
@@ -19,8 +19,10 @@
static const struct pmic_child_info pmic_children_info[] = {
/* buck */
{ .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER},
+ { .prefix = "B", .driver = PCA9450_REGULATOR_DRIVER},
/* ldo */
{ .prefix = "l", .driver = PCA9450_REGULATOR_DRIVER},
+ { .prefix = "L", .driver = PCA9450_REGULATOR_DRIVER},
{ },
};
@@ -81,9 +83,9 @@
};
static const struct udevice_id pca9450_ids[] = {
- { .compatible = "nxp,pca9450a", .data = 0x25, },
- { .compatible = "nxp,pca9450b", .data = 0x25, },
- { .compatible = "nxp,pca9450c", .data = 0x25, },
+ { .compatible = "nxp,pca9450a", .data = NXP_CHIP_TYPE_PCA9450A, },
+ { .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, },
+ { .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, },
{ }
};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 9145408..d6cea8e 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -60,6 +60,21 @@
This config enables implementation of driver-model regulator uclass
features for regulators on ROHM BD71837 and BD71847 in SPL.
+config DM_REGULATOR_PCA9450
+ bool "Enable Driver Model for NXP PCA9450 regulators"
+ depends on DM_REGULATOR && DM_PMIC_PCA9450
+ help
+ This config enables implementation of driver-model regulator uclass
+ features for regulators on NXP PCA9450 PMICs. PCA9450 contains 6 bucks
+ and 5 LDOS. The driver implements get/set api for value and enable.
+
+config SPL_DM_REGULATOR_PCA9450
+ bool "Enable Driver Model for NXP PCA9450 regulators in SPL"
+ depends on DM_REGULATOR_PCA9450
+ help
+ This config enables implementation of driver-model regulator uclass
+ features for regulators on ROHM PCA9450 in SPL.
+
config DM_REGULATOR_DA9063
bool "Enable Driver Model for REGULATOR DA9063"
depends on DM_REGULATOR && DM_PMIC_DA9063
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index b9883df..bc73606 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_PCA9450) += pca9450.o
obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o
diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c
new file mode 100644
index 0000000..23badaa
--- /dev/null
+++ b/drivers/power/regulator/pca9450.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * NXP PCA9450 regulator driver
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ *
+ * Largely based on:
+ * ROHM BD71837 regulator driver
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <linux/bitops.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define HW_STATE_CONTROL 0
+#define DEBUG
+
+/**
+ * struct pca9450_vrange - describe linear range of voltages
+ *
+ * @min_volt: smallest voltage in range
+ * @step: how much voltage changes at each selector step
+ * @min_sel: smallest selector in the range
+ * @max_sel: maximum selector in the range
+ */
+struct pca9450_vrange {
+ unsigned int min_volt;
+ unsigned int step;
+ u8 min_sel;
+ u8 max_sel;
+};
+
+/**
+ * struct pca9450_plat - describe regulator control registers
+ *
+ * @name: name of the regulator. Used for matching the dt-entry
+ * @enable_reg: register address used to enable/disable regulator
+ * @enablemask: register mask used to enable/disable regulator
+ * @volt_reg: register address used to configure regulator voltage
+ * @volt_mask: register mask used to configure regulator voltage
+ * @ranges: pointer to ranges of regulator voltages and matching register
+ * values
+ * @numranges: number of voltage ranges pointed by ranges
+ * @dvs: whether the voltage can be changed when regulator is enabled
+ */
+struct pca9450_plat {
+ const char *name;
+ u8 enable_reg;
+ u8 enablemask;
+ u8 volt_reg;
+ u8 volt_mask;
+ struct pca9450_vrange *ranges;
+ unsigned int numranges;
+ bool dvs;
+};
+
+#define PCA_RANGE(_min, _vstep, _sel_low, _sel_hi) \
+{ \
+ .min_volt = (_min), .step = (_vstep), \
+ .min_sel = (_sel_low), .max_sel = (_sel_hi), \
+}
+
+#define PCA_DATA(_name, enreg, enmask, vreg, vmask, _range, _dvs) \
+{ \
+ .name = (_name), .enable_reg = (enreg), .enablemask = (enmask), \
+ .volt_reg = (vreg), .volt_mask = (vmask), .ranges = (_range), \
+ .numranges = ARRAY_SIZE(_range), .dvs = (_dvs), \
+}
+
+static struct pca9450_vrange pca9450_buck123_vranges[] = {
+ PCA_RANGE(600000, 12500, 0, 0x7f),
+};
+
+static struct pca9450_vrange pca9450_buck456_vranges[] = {
+ PCA_RANGE(600000, 25000, 0, 0x70),
+ PCA_RANGE(3400000, 0, 0x71, 0x7f),
+};
+
+static struct pca9450_vrange pca9450_ldo1_vranges[] = {
+ PCA_RANGE(1600000, 100000, 0x0, 0x3),
+ PCA_RANGE(3000000, 100000, 0x4, 0x7),
+};
+
+static struct pca9450_vrange pca9450_ldo2_vranges[] = {
+ PCA_RANGE(800000, 50000, 0x0, 0x7),
+};
+
+static struct pca9450_vrange pca9450_ldo34_vranges[] = {
+ PCA_RANGE(800000, 100000, 0x0, 0x19),
+ PCA_RANGE(3300000, 0, 0x1a, 0x1f),
+};
+
+static struct pca9450_vrange pca9450_ldo5_vranges[] = {
+ PCA_RANGE(1800000, 100000, 0x0, 0xf),
+};
+
+/*
+ * We use enable mask 'HW_STATE_CONTROL' to indicate that this regulator
+ * must not be enabled or disabled by SW. The typical use-case for PCA9450
+ * is powering NXP i.MX8. In this use-case we (for now) only allow control
+ * for BUCK4, BUCK5, BUCK6 which are not boot critical.
+ */
+static struct pca9450_plat pca9450_reg_data[] = {
+ /* Bucks 1-3 which support dynamic voltage scaling */
+ PCA_DATA("BUCK1", PCA9450_BUCK1CTRL, HW_STATE_CONTROL,
+ PCA9450_BUCK1OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK,
+ pca9450_buck123_vranges, true),
+ PCA_DATA("BUCK2", PCA9450_BUCK2CTRL, HW_STATE_CONTROL,
+ PCA9450_BUCK2OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK,
+ pca9450_buck123_vranges, true),
+ PCA_DATA("BUCK3", PCA9450_BUCK3CTRL, HW_STATE_CONTROL,
+ PCA9450_BUCK3OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK,
+ pca9450_buck123_vranges, true),
+ /* Bucks 4-6 which do not support dynamic voltage scaling */
+ PCA_DATA("BUCK4", PCA9450_BUCK4CTRL, HW_STATE_CONTROL,
+ PCA9450_BUCK4OUT, PCA9450_DVS_BUCK_RUN_MASK,
+ pca9450_buck456_vranges, false),
+ PCA_DATA("BUCK5", PCA9450_BUCK5CTRL, HW_STATE_CONTROL,
+ PCA9450_BUCK5OUT, PCA9450_DVS_BUCK_RUN_MASK,
+ pca9450_buck456_vranges, false),
+ PCA_DATA("BUCK6", PCA9450_BUCK6CTRL, HW_STATE_CONTROL,
+ PCA9450_BUCK6OUT, PCA9450_DVS_BUCK_RUN_MASK,
+ pca9450_buck456_vranges, false),
+ /* LDOs */
+ PCA_DATA("LDO1", PCA9450_LDO1CTRL, HW_STATE_CONTROL,
+ PCA9450_LDO1CTRL, PCA9450_LDO12_MASK,
+ pca9450_ldo1_vranges, false),
+ PCA_DATA("LDO2", PCA9450_LDO2CTRL, HW_STATE_CONTROL,
+ PCA9450_LDO2CTRL, PCA9450_LDO12_MASK,
+ pca9450_ldo2_vranges, false),
+ PCA_DATA("LDO3", PCA9450_LDO3CTRL, HW_STATE_CONTROL,
+ PCA9450_LDO3CTRL, PCA9450_LDO34_MASK,
+ pca9450_ldo34_vranges, false),
+ PCA_DATA("LDO4", PCA9450_LDO4CTRL, HW_STATE_CONTROL,
+ PCA9450_LDO4CTRL, PCA9450_LDO34_MASK,
+ pca9450_ldo34_vranges, false),
+ PCA_DATA("LDO5", PCA9450_LDO5CTRL_H, HW_STATE_CONTROL,
+ PCA9450_LDO5CTRL_H, PCA9450_LDO5_MASK,
+ pca9450_ldo5_vranges, false),
+};
+
+static int vrange_find_value(struct pca9450_vrange *r, unsigned int sel,
+ unsigned int *val)
+{
+ if (!val || sel < r->min_sel || sel > r->max_sel)
+ return -EINVAL;
+
+ *val = r->min_volt + r->step * (sel - r->min_sel);
+ return 0;
+}
+
+static int vrange_find_selector(struct pca9450_vrange *r, int val,
+ unsigned int *sel)
+{
+ int ret = -EINVAL;
+ int num_vals = r->max_sel - r->min_sel + 1;
+
+ if (val >= r->min_volt &&
+ val <= r->min_volt + r->step * (num_vals - 1)) {
+ if (r->step) {
+ *sel = r->min_sel + ((val - r->min_volt) / r->step);
+ ret = 0;
+ } else {
+ *sel = r->min_sel;
+ ret = 0;
+ }
+ }
+ return ret;
+}
+
+static int pca9450_get_enable(struct udevice *dev)
+{
+ struct pca9450_plat *plat = dev_get_plat(dev);
+ int val;
+
+ /*
+ * boot critical regulators on pca9450 must not be controlled by sw
+ * due to the 'feature' which leaves power rails down if pca9450 is
+ * reseted to snvs state. hence we can't get the state here.
+ *
+ * if we are alive it means we probably are on run state and
+ * if the regulator can't be controlled we can assume it is
+ * enabled.
+ */
+ if (plat->enablemask == HW_STATE_CONTROL)
+ return 1;
+
+ val = pmic_reg_read(dev->parent, plat->enable_reg);
+ if (val < 0)
+ return val;
+
+ return (val & plat->enablemask);
+}
+
+static int pca9450_set_enable(struct udevice *dev, bool enable)
+{
+ int val = 0;
+ struct pca9450_plat *plat = dev_get_plat(dev);
+
+ /*
+ * boot critical regulators on pca9450 must not be controlled by sw
+ * due to the 'feature' which leaves power rails down if pca9450 is
+ * reseted to snvs state. Hence we can't set the state here.
+ */
+ if (plat->enablemask == HW_STATE_CONTROL)
+ return enable ? 0 : -EINVAL;
+
+ if (enable)
+ val = plat->enablemask;
+
+ return pmic_clrsetbits(dev->parent, plat->enable_reg, plat->enablemask,
+ val);
+}
+
+static int pca9450_get_value(struct udevice *dev)
+{
+ struct pca9450_plat *plat = dev_get_plat(dev);
+ unsigned int reg, tmp;
+ int i, ret;
+
+ ret = pmic_reg_read(dev->parent, plat->volt_reg);
+ if (ret < 0)
+ return ret;
+
+ reg = ret;
+ reg &= plat->volt_mask;
+
+ for (i = 0; i < plat->numranges; i++) {
+ struct pca9450_vrange *r = &plat->ranges[i];
+
+ if (!vrange_find_value(r, reg, &tmp))
+ return tmp;
+ }
+
+ pr_err("Unknown voltage value read from pmic\n");
+
+ return -EINVAL;
+}
+
+static int pca9450_set_value(struct udevice *dev, int uvolt)
+{
+ struct pca9450_plat *plat = dev_get_plat(dev);
+ unsigned int sel;
+ int i, found = 0;
+
+ /*
+ * An under/overshooting may occur if voltage is changed for other
+ * regulators but buck 1,2,3 or 4 when regulator is enabled. Prevent
+ * change to protect the HW
+ */
+ if (!plat->dvs)
+ if (pca9450_get_enable(dev)) {
+ /* If the value is already set, skip the warning. */
+ if (pca9450_get_value(dev) == uvolt)
+ return 0;
+ pr_err("Only DVS bucks can be changed when enabled\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < plat->numranges; i++) {
+ struct pca9450_vrange *r = &plat->ranges[i];
+
+ found = !vrange_find_selector(r, uvolt, &sel);
+ if (found) {
+ unsigned int tmp;
+
+ /*
+ * We require exactly the requested value to be
+ * supported - this can be changed later if needed
+ */
+ found = !vrange_find_value(r, sel, &tmp);
+ if (found && tmp == uvolt)
+ break;
+ found = 0;
+ }
+ }
+
+ if (!found)
+ return -EINVAL;
+
+ return pmic_clrsetbits(dev->parent, plat->volt_reg,
+ plat->volt_mask, sel);
+}
+
+static int pca9450_regulator_probe(struct udevice *dev)
+{
+ struct pca9450_plat *plat = dev_get_plat(dev);
+ int i, type;
+
+ type = dev_get_driver_data(dev_get_parent(dev));
+
+ if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC) {
+ debug("Unknown PMIC type\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pca9450_reg_data); i++) {
+ if (strcmp(dev->name, pca9450_reg_data[i].name))
+ continue;
+
+ /* PCA9450B/PCA9450C uses BUCK1 and BUCK3 in dual-phase */
+ if (type == NXP_CHIP_TYPE_PCA9450BC &&
+ !strcmp(pca9450_reg_data[i].name, "BUCK3")) {
+ continue;
+ }
+
+ *plat = pca9450_reg_data[i];
+
+ return 0;
+ }
+
+ pr_err("Unknown regulator '%s'\n", dev->name);
+
+ return -ENOENT;
+}
+
+static const struct dm_regulator_ops pca9450_regulator_ops = {
+ .get_value = pca9450_get_value,
+ .set_value = pca9450_set_value,
+ .get_enable = pca9450_get_enable,
+ .set_enable = pca9450_set_enable,
+};
+
+U_BOOT_DRIVER(pca9450_regulator) = {
+ .name = PCA9450_REGULATOR_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &pca9450_regulator_ops,
+ .probe = pca9450_regulator_probe,
+ .plat_auto = sizeof(struct pca9450_plat),
+};
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index 6da0483..4c04bbf 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -132,6 +132,5 @@
/* Networking */
#define CONFIG_FEC_MXC_PHYADDR -1
-#define FEC_QUIRK_ENET_MAC
#endif /* __CGTQMX8_H */
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 2b14464..178f5a6 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -30,9 +30,6 @@
/* Bootcounter */
#define CONFIG_SYS_BOOTCOUNT_BE
-/* FEC ethernet */
-#define CONFIG_FEC_MXC_PHYADDR 7
-
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index bb53a33..6790053 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -70,7 +70,7 @@
/*
* Serial Driver info
*/
-#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/*
* Flash & Environment
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
new file mode 100644
index 0000000..6d36255
--- /dev/null
+++ b/include/configs/imx6q-bosch-acc.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
+ * Copyright (c) 2019 Bosch Thermotechnik GmbH
+ * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+#ifndef __IMX6Q_ACC_H
+#define __IMX6Q_ACC_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+#ifdef CONFIG_SYS_BOOT_EMMC
+#define MMC_ROOTFS_DEV 0
+#define MMC_ROOTFS_PART 2
+#endif
+
+#ifdef CONFIG_SYS_BOOT_EMMC
+/* eMMC Boot */
+#define ENV_EXTRA \
+ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
+ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
+ "fitpart=1\0" \
+ "optargs=ro quiet systemd.gpt_auto=false\0" \
+ "production=1\0" \
+ "mmcautodetect=yes\0" \
+ "mmcrootfstype=ext4\0" \
+ "finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+ "mmcargs=run finduuid; setenv bootargs " \
+ "root=PARTUUID=${uuid} ${optargs} rootfstype=${mmcrootfstype}\0" \
+ "mmc_mmc_fit=run env_persist; run setbm; run mmcloadfit; " \
+ "run auth_fit_or_reset; run mmcargs addcon; " \
+ "bootm ${fit_addr}#${bootconf}\0" \
+ "bootset=0\0" \
+ "setbm=if test ${bootset} -eq 1; " \
+ "then setenv mmcpart 4; setenv fitpart 3; " \
+ "else; setenv mmcpart 2; setenv fitpart 1; fi\0" \
+ "handle_ustate=if test ${ustate} -eq 2; then setenv ustate 3; fi\0" \
+ "switch_bootset=if test ${bootset} -eq 1; then setenv bootset 0; " \
+ "else; setenv bootset 1;fi\0" \
+ "env_persisted=0\0" \
+ "env_persist=if test ${env_persisted} != 1; " \
+ "then env set env_persisted 1; run save_env; fi;\0" \
+ "save_env=env save; env save\0" \
+ "altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0"
+
+#define CONFIG_ENV_FLAGS_LIST_STATIC \
+ "bootset:bw," \
+ "clone_pending:bw," \
+ "endurance_test:bw," \
+ "env_persisted:bw," \
+ "factory_reset:bw," \
+ "fdtcontroladdr:xw," \
+ "fitpart:dw," \
+ "mmcpart:dw," \
+ "production:bw," \
+ "ustate:dw"
+
+#else
+/* SD Card boot */
+#define ENV_EXTRA \
+ "mmcdev=1\0" \
+ "fitpart=1\0" \
+ "rootpart=2\0" \
+ "optargs=ro systemd.gpt_auto=false\0" \
+ "finduuid=part uuid mmc ${mmcdev}:${rootpart} uuid\0" \
+ "mmcargs=run finduuid;setenv bootargs root=PARTUUID=${uuid} ${optargs}\0" \
+ "mmc_mmc_fit=run mmcloadfit; run auth_fit_or_reset; run mmcargs addcon; " \
+ "bootm ${fit_addr}#${bootconf}\0"
+
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootconf=conf-imx6q-bosch-acc.dtb\0"\
+ "mmcfit_name=fitImage\0" \
+ "mmcloadfit=ext4load mmc ${mmcdev}:${fitpart} ${fit_addr} ${mmcfit_name}\0" \
+ "auth_fit_or_reset=hab_auth_img ${fit_addr} ${filesize} || reset\0" \
+ "console=ttymxc0\0" \
+ "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
+ "fit_addr=19000000\0" \
+ ENV_EXTRA
+
+/* Physical Memory Map */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* SPL */
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#ifdef CONFIG_SYS_BOOT_EMMC
+
+/* Boot from eMMC */
+#define CONFIG_SYS_FSL_ESDHC_ADDR 1
+
+#else
+
+/* Boot from SD-card */
+# define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#endif
+
+#endif
+#endif
+
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
+
+#endif /* __IMX6Q_ACC_H */
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index c20c32b..8d9212e 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -145,7 +145,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
@@ -160,7 +160,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h
index fd18316..530ecd1 100644
--- a/include/configs/imx8mm-mx8menlo.h
+++ b/include/configs/imx8mm-mx8menlo.h
@@ -30,7 +30,4 @@
"initrd_addr=0x43800000\0" \
"kernel_image=fitImage\0"
-#undef CONFIG_MXC_UART_BASE
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
-
#endif /* __IMX8MM_MX8MENLO_H */
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index 7c17f14..573ddaf 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -91,7 +91,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index 33778a2..67667dd 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -41,8 +41,6 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
@@ -52,7 +50,6 @@
/* PHY needs a longer autonegotiation timeout after reset */
#define PHY_ANEG_TIMEOUT 20000
-#define FEC_QUIRK_ENET_MAC
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index 42b7848..5e8f19c 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -68,7 +68,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
@@ -78,6 +78,5 @@
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
#endif
diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
index f521add..b9b24a8 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -66,7 +66,7 @@
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 1b26e02..9836d5b 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -102,7 +102,7 @@
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
@@ -111,8 +111,4 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* FEC */
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
-
#endif
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 41ce3c1..79c6b10 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -107,7 +107,7 @@
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
#endif
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 0341322..805ae2a 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -75,7 +75,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h
index 318289b..0035889 100644
--- a/include/configs/imx8mn_var_som.h
+++ b/include/configs/imx8mn_var_som.h
@@ -64,7 +64,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
-#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index a482677..3cbe11a 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h
@@ -98,7 +98,7 @@
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
@@ -107,8 +107,4 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* FEC */
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
-
#endif
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
new file mode 100644
index 0000000..7d5403f
--- /dev/null
+++ b/include/configs/imx8mp_dhcom_pdk2.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __IMX8MP_DHCOM_PDK2_H
+#define __IMX8MP_DHCOM_PDK2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_1M
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x96FC00
+#define CONFIG_SPL_BSS_START_ADDR 0x0096FC00
+#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KiB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x4c000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 kiB */
+
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */
+
+#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* PHY needs a longer autonegotiation timeout after reset */
+#define PHY_ANEG_TIMEOUT 20000
+#define FEC_QUIRK_ENET_MAC
+
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "altbootcmd=run bootcmd ; reset\0" \
+ "bootlimit=3\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramdisk_addr_r=0x58000000\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ /* Give slow devices beyond USB HUB chance to come up. */ \
+ "usb_pgood_delay=2000\0" \
+ "dfu_alt_info=" \
+ /* RAM block at DRAM offset 256..768 MiB */ \
+ "ram ram0=ram ram 0x50000000 0x20000000&" \
+ /* 16 MiB SPI NOR */ \
+ "mtd nor0=sf raw 0x0 0x1000000\0" \
+ "dh_update_env=" \
+ "setenv dh_update_env true ; saveenv ; saveenv\0" \
+ "dh_update_sf_gen_fcfb=" \
+ "setexpr sfaddr ${loadaddr} - 0x1000 ; " \
+ "base ${sfaddr} ; " \
+ "mw 0 0 0x400 ; " \
+ "mw 0x400 0x42464346 ; " \
+ "mw 0x404 0x56010000 ; " \
+ "mw 0x40c 00030300 ; " \
+ "mw 0x444 0x00020101 ; " \
+ "mw 0x450 0x10000000 ; " \
+ "mw 0x480 0x0818040b ; " \
+ "mw 0x484 0x24043008 ; " \
+ "mw 0x5c0 0x100 ; " \
+ "mw 0x5c4 0x10000 ; " \
+ "base 0\0" \
+ "dh_update_sf_write_data=" \
+ "setexpr sfaddr ${loadaddr} - 0x1000 ; " \
+ "setexpr filesize ${filesize} + 0x1000 ; " \
+ "sf probe && sf update ${sfaddr} 0 ${filesize}\0" \
+ "dh_update_sd_to_sf=" \
+ "load mmc 0:1 ${loadaddr} boot/flash.bin && " \
+ "run dh_update_sf_gen_fcfb dh_update_sf_write_data\0" \
+ "dh_update_emmc_to_sf=" \
+ "load mmc 1:1 ${loadaddr} boot/flash.bin && " \
+ "run dh_update_sf_gen_fcfb dh_update_sf_write_data\0" \
+ BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(USB, usb, 0) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#endif
+
+#endif
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index cc8d65c..1e7c44c 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -32,7 +32,6 @@
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
-#define FEC_QUIRK_ENET_MAC
#define DWC_NET_PHYADDR 1
@@ -80,7 +79,7 @@
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index c5dd545..52e8ea8 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -51,7 +51,6 @@
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 4
-#define FEC_QUIRK_ENET_MAC
#define DWC_NET_PHYADDR 4
#ifdef CONFIG_DWC_ETH_QOS
@@ -169,8 +168,6 @@
#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
#endif
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index aa0396d..4120e4c 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h
@@ -106,4 +106,8 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* FEC */
+#define FEC_QUIRK_ENET_MAC
+
#endif
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
index 989486a..6eecfc8 100644
--- a/include/configs/imx8mq_cm.h
+++ b/include/configs/imx8mq_cm.h
@@ -71,7 +71,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
-#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index f7929e5..e31f413 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -37,7 +37,6 @@
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
#endif
#ifndef CONFIG_SPL_BUILD
@@ -78,7 +77,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
-#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
index f641011..57e45b0 100644
--- a/include/configs/imx8mq_phanbell.h
+++ b/include/configs/imx8mq_phanbell.h
@@ -31,7 +31,6 @@
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
#endif
#define CONFIG_MFG_ENV_SETTINGS \
@@ -106,7 +105,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
-#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h
index 1b429f7..231571b 100644
--- a/include/configs/kontron-sl-mx8mm.h
+++ b/include/configs/kontron-sl-mx8mm.h
@@ -28,7 +28,7 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Board and environment settings */
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#define CONFIG_HOSTNAME "kontron-mx8mm"
#ifdef CONFIG_USB_EHCI_HCD
@@ -70,8 +70,6 @@
#define CONFIG_MALLOC_F_ADDR 0x930000
#endif
-#define FEC_QUIRK_ENET_MAC
-
#define ENV_MEM_LAYOUT_SETTINGS \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_addr_r=0x42000000\0" \
diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h
index e8e9292..1834991 100644
--- a/include/configs/kontron_pitx_imx8m.h
+++ b/include/configs/kontron_pitx_imx8m.h
@@ -38,7 +38,6 @@
/* ENET1 Config */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
#define PHY_ANEG_TIMEOUT 20000
@@ -84,7 +83,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index 71f0c42..46fadd5 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -84,7 +84,7 @@
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* UART */
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 0c963b6..eb92c42 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -84,7 +84,7 @@
#define PHYS_SDRAM_SIZE 0x80000000
/* UART */
-#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h
index 9584527..1dc7d35 100644
--- a/include/configs/pico-imx8mq.h
+++ b/include/configs/pico-imx8mq.h
@@ -31,7 +31,6 @@
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
-#define FEC_QUIRK_ENET_MAC
#endif
/* Initial environment variables */
@@ -85,7 +84,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
-#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index da3dc95..cd950ad 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -84,7 +84,7 @@
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* UART */
-#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
@@ -95,7 +95,6 @@
/* ENET */
#define CONFIG_FEC_MXC_PHYADDR 7
-#define FEC_QUIRK_ENET_MAC
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
index 7b74077..470f64d 100644
--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h
@@ -36,7 +36,6 @@
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 7
-#define FEC_QUIRK_ENET_MAC
#define PHY_ANEG_TIMEOUT 20000
#endif /* CONFIG_CMD_NET */
@@ -101,7 +100,7 @@
#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)
/* UART */
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 7b6e3e2..d57c4ca 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -48,7 +48,11 @@
u32 rtmctl; /* misc. control register */
u32 rtscmisc; /* statistical check misc. register */
u32 rtpkrrng; /* poker range register */
-#define RTSDCTL_ENT_DLY_MIN 3200
+#ifdef CONFIG_MX6SX
+#define RTSDCTL_ENT_DLY 12000
+#else
+#define RTSDCTL_ENT_DLY 3200
+#endif
#define RTSDCTL_ENT_DLY_MAX 12800
union {
u32 rtpkrmax; /* PRGM=1: poker max. limit register */
diff --git a/include/power/pca9450.h b/include/power/pca9450.h
index 27703bb..fa0405fc 100644
--- a/include/power/pca9450.h
+++ b/include/power/pca9450.h
@@ -56,4 +56,15 @@
int power_pca9450_init(unsigned char bus, unsigned char addr);
+enum {
+ NXP_CHIP_TYPE_PCA9450A = 0,
+ NXP_CHIP_TYPE_PCA9450BC,
+ NXP_CHIP_TYPE_AMOUNT
+};
+
+#define PCA9450_DVS_BUCK_RUN_MASK 0x7f
+#define PCA9450_LDO12_MASK 0x07
+#define PCA9450_LDO34_MASK 0x1f
+#define PCA9450_LDO5_MASK 0x0f
+
#endif