| commit | 013f2d746955147439215a4939655c9ed6bdd866 | [log] [tgz] |
|---|---|---|
| author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | Sun Aug 03 05:32:48 2014 +0300 |
| committer | Hans de Goede <hdegoede@redhat.com> | Tue Aug 12 08:42:33 2014 +0200 |
| tree | fc8468aa8c6c2d1b1f245365bd4cc1aeee004e84 | |
| parent | 1a9717cbb3753ea93d156621b3082434b8417c9f [diff] |
sunxi: dram: Use divisor P=1 for PLL5 This configures the PLL5P clock frequency to something in the ballpark of 1GHz and allows more choices for MBUS and G2D clock frequency selection (using their own divisors). In particular, it enables the use of 2/3 clock speed ratio between MBUS and DRAM. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>