Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"
This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.
There isn't any need to modify the API for fsl_pci_init_port to pass the
status of host/agent(end-point) status. We can determine that
internally to fsl_pci_init_port. Revert the patch that makes the API
change.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 2b32234..933dd12 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -199,7 +199,7 @@
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno, pcie_ep);
+ &pcie3_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
@@ -231,7 +231,7 @@
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
@@ -251,7 +251,7 @@
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index 7736596..4c08f9e 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -71,7 +71,7 @@
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
@@ -90,7 +90,7 @@
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 9878fba..e38c014 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -227,7 +227,7 @@
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
/*
* The workaround doesn't work on p2020 because the location
@@ -267,7 +267,7 @@
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno, pcie_ep);
+ &pcie3_hose, first_free_busno);
} else {
printf(" PCIE3: disabled\n");
}
@@ -286,7 +286,7 @@
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf(" PCIE1: disabled\n");
}
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 5e3e176..194f6ab 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -359,7 +359,7 @@
SET_STD_PCI_INFO(pci_info[num], 1);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pci1_hose, first_free_busno, 0);
+ &pci1_hose, first_free_busno);
} else {
printf (" PCI: disabled\n");
}
@@ -378,7 +378,7 @@
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE at base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, 0);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE: disabled\n");
}
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 8fbab68..87944bf 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -413,27 +413,13 @@
}
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno, int pcie_ep)
+ struct pci_controller *hose, int busno)
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
- if (pcie_ep) {
- volatile pit_t *pi = &pci->pit[2];
-
- pci_setup_indirect(hose, (u32)&pci->cfg_addr,
- (u32)&pci->cfg_data);
- out_be32(&pi->pitar, 0);
- out_be32(&pi->piwbar, 0);
- out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
-
- fsl_pci_config_unlock(hose);
- return 0;
- }
-
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/
diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h
index 6b0c89b..2790da7 100644
--- a/include/asm-ppc/fsl_pci.h
+++ b/include/asm-ppc/fsl_pci.h
@@ -62,7 +62,6 @@
#define PIWAR_LOCAL 0x00f00000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE_SNOOP 0x00005000
-#define PIWAR_IWS_4K 0x0000000b
u32 res2[3];
} pit_t;
@@ -172,7 +171,7 @@
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno, int pcie_ep);
+ struct pci_controller *hose, int busno);
#define SET_STD_PCI_INFO(x, num) \
{ \