| commit | 0254006b29fcb960ef8c3188eab12a39845719f0 | [log] [tgz] |
|---|---|---|
| author | Yung-Ching LIN <yungching0725@gmail.com> | Wed Mar 29 01:51:24 2017 +0800 |
| committer | Stefano Babic <sbabic@denx.de> | Wed Apr 12 18:04:53 2017 +0200 |
| tree | 010fba28805385ab0c402b624bb1b651d20c38c8 | |
| parent | fc9ade56e3eb451683a58089e32e79abb69e240e [diff] |
board: advantech: dms-ba16: fix AR8033 reset timing issue Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet Signed-off-by: Ken Lin <yungching0725@gmail.com> Acked-by: Akshay Bhat <akshay.bhat@timesys.com>